static void timer_setup(void) { /* Enable TIM3 clock. */ rcc_periph_clock_enable(RCC_TIM3); timer_reset(TIM3); /* Timer global mode: - No divider, Alignment edge, Direction up */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM3); timer_set_period(TIM3, PERIOD); timer_disable_preload(TIM3); /* prescaler F_SYS/48 = TIM3 clock is 1 MHz */ timer_set_prescaler(TIM3,48); //timer_disable_oc_output(TIM3, TIM_OC2 | TIM_OC3 | TIM_OC4); timer_enable_oc_output(TIM3, TIM_OC1); timer_disable_oc_output(TIM3,TIM_OC2); timer_enable_oc_output(TIM3, TIM_OC3); //timer_enable_oc_output(TIM3, TIM_OC4); // motor ch1 timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1); // motor ch2 timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1); // motor ch3 timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1); // motor ch3 timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1); /* disable preload */ timer_disable_oc_preload(TIM3, TIM_OC1); timer_disable_oc_preload(TIM3, TIM_OC2); timer_disable_oc_preload(TIM3, TIM_OC3); timer_disable_oc_preload(TIM3, TIM_OC4); /* polarity */ timer_set_oc_polarity_high(TIM3,TIM_OC1); timer_set_oc_polarity_high(TIM3,TIM_OC2); timer_set_oc_polarity_high(TIM3,TIM_OC3); timer_set_oc_polarity_high(TIM3,TIM_OC4); //timer_enable_oc_clear(TIM3, TIM_OC1); //timer_set_oc_slow_mode(TIM3, TIM_OC1); timer_set_oc_value(TIM3, TIM_OC1, PULSE); timer_set_oc_value(TIM3, TIM_OC2, PULSE*3); timer_set_oc_value(TIM3, TIM_OC3, PULSE*2); timer_set_oc_value(TIM3, TIM_OC4, PULSE*4); //timer_generate_event(TIM3,TIM_EGR_CC1G); //timer_enable_update_event(TIM3); nvic_enable_irq(NVIC_TIM3_IRQ); timer_enable_irq(TIM3,TIM_DIER_CC1IE); timer_enable_irq(TIM3,TIM_DIER_CC2IE); timer_enable_irq(TIM3,TIM_DIER_CC3IE); timer_enable_irq(TIM3,TIM_DIER_CC4IE); //timer_enable_irq(TIM3,TIM_DIER_CC2IE); timer_enable_irq(TIM3,TIM_DIER_UIE); /* Set the timer trigger output (for the DAC) to the channel 1 output compare */ //timer_set_master_mode(TIM3, TIM_CR2_MMS_COMPARE_OC1REF); timer_enable_counter(TIM3); }
void tim_init(void) { /* Enable TIM1 clock. and Port E clock (for outputs) */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); //Set TIM1 channel (and complementary) output to alternate function push-pull'. //f4 TIM1=> GIO9: CH1, GPIO11: CH2, GPIO13: CH3 //f4 TIM1=> GIO8: CH1N, GPIO10: CH2N, GPIO12: CH3N gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO9 | GPIO11 | GPIO13); gpio_set_af(GPIOE, GPIO_AF1, GPIO9 | GPIO11 | GPIO13); gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO8 | GPIO10 | GPIO12); gpio_set_af(GPIOE, GPIO_AF1, GPIO8 | GPIO10 | GPIO12); /* Enable TIM1 commutation interrupt. */ //nvic_enable_irq(NVIC_TIM1_TRG_COM_TIM11_IRQ); //f4 /* Reset TIM1 peripheral. */ timer_reset(TIM1); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, //For dead time and filter sampling, not important for now. TIM_CR1_CMS_CENTER_3, //TIM_CR1_CMS_EDGE //TIM_CR1_CMS_CENTER_1 //TIM_CR1_CMS_CENTER_2 //TIM_CR1_CMS_CENTER_3 la frequencia del pwm se divide a la mitad. (frecuencia senoidal) TIM_CR1_DIR_UP); timer_set_prescaler(TIM1, PRESCALE); //1 = disabled (max speed) timer_set_repetition_counter(TIM1, 0); //disabled timer_enable_preload(TIM1); timer_continuous_mode(TIM1); /* Period (32kHz). */ timer_set_period(TIM1, PWM_PERIOD_ARR); //ARR (value compared against main counter to reload counter aka: period of counter) /* Configure break and deadtime. */ //timer_set_deadtime(TIM1, deadtime_percentage*pwm_period_ARR); timer_set_enabled_off_state_in_idle_mode(TIM1); timer_set_enabled_off_state_in_run_mode(TIM1); timer_disable_break(TIM1); timer_set_break_polarity_high(TIM1); timer_disable_break_automatic_output(TIM1); timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF); /* Disable outputs. */ timer_disable_oc_output(TIM1, TIM_OC1); timer_disable_oc_output(TIM1, TIM_OC1N); timer_disable_oc_output(TIM1, TIM_OC2); timer_disable_oc_output(TIM1, TIM_OC2N); timer_disable_oc_output(TIM1, TIM_OC3); timer_disable_oc_output(TIM1, TIM_OC3N); /* -- OC1 and OC1N configuration -- */ /* Configure global mode of line 1. */ timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); /* Configure OC1. */ timer_set_oc_polarity_high(TIM1, TIM_OC1); timer_set_oc_idle_state_unset(TIM1, TIM_OC1); //When idle (braked) put 0 on output /* Configure OC1N. */ timer_set_oc_polarity_high(TIM1, TIM_OC1N); timer_set_oc_idle_state_unset(TIM1, TIM_OC1N); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM1, TIM_OC1, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC2 and OC2N configuration -- */ /* Configure global mode of line 2. */ timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); /* Configure OC2. */ timer_set_oc_polarity_high(TIM1, TIM_OC2); timer_set_oc_idle_state_unset(TIM1, TIM_OC2); /* Configure OC2N. */ timer_set_oc_polarity_high(TIM1, TIM_OC2N); timer_set_oc_idle_state_unset(TIM1, TIM_OC2N); /* Set the capture compare value for OC2. */ timer_set_oc_value(TIM1, TIM_OC2, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC3 and OC3N configuration -- */ /* Configure global mode of line 3. */ timer_enable_oc_preload(TIM1, TIM_OC3); timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); /* Configure OC3. */ timer_set_oc_polarity_high(TIM1, TIM_OC3); timer_set_oc_idle_state_unset(TIM1, TIM_OC3); /* Configure OC3N. */ timer_set_oc_polarity_high(TIM1, TIM_OC3N); timer_set_oc_idle_state_unset(TIM1, TIM_OC3N); /* Set the capture compare value for OC3. */ timer_set_oc_value(TIM1, TIM_OC3, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);//100); /* Reenable outputs. */ timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_enable_oc_output(TIM1, TIM_OC3); timer_enable_oc_output(TIM1, TIM_OC3N); /* ---- */ /* ARR reload enable. */ timer_enable_preload(TIM1); /* * Enable preload of complementary channel configurations and * update on COM event. */ //timer_enable_preload_complementry_enable_bits(TIM1); timer_disable_preload_complementry_enable_bits(TIM1); /* Enable outputs in the break subsystem. */ timer_enable_break_main_output(TIM1); /* Generate update event to reload all registers before starting*/ timer_generate_event(TIM1, TIM_EGR_UG); /* Counter enable. */ timer_enable_counter(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_COMIE); /*********/ /*Capture compare interrupt*/ //enable capture compare interrupt timer_enable_update_event(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); //Capture/compare 1 interrupt enable /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); timer_enable_irq(TIM1, TIM_DIER_UIE); nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ); }
static void arch_timer_set_mode_virt(enum clock_event_mode mode, struct clock_event_device *clk) { timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk); }
static void arch_timer_set_mode_phys(enum clock_event_mode mode, struct clock_event_device *clk) { timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk); }
/** Set Timer configuration * @param[in] timer Timer register address base * @param[in] period period in us * @param[in] channels_mask output compare channels to enable */ void set_servo_timer(uint32_t timer, uint32_t period, uint8_t channels_mask) { // WARNING, this reset is only implemented for TIM1-8 in libopencm3!! timer_reset(timer); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ if ((timer == TIM9) || (timer == TIM12)) //There are no EDGE and DIR settings in TIM9 and TIM12 timer_set_mode(timer, TIM_CR1_CKD_CK_INT, 0, 0); else timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // By default the PWM_BASE_FREQ is set to 1MHz thus the timer tick period is 1uS uint32_t timer_clk = timer_get_frequency(timer); timer_set_prescaler(timer, (timer_clk / PWM_BASE_FREQ) -1); timer_disable_preload(timer); timer_continuous_mode(timer); timer_set_period(timer, (PWM_BASE_FREQ / period) - 1); /* Disable outputs and configure channel if needed. */ if (bit_is_set(channels_mask, 0)) { actuators_pwm_arch_channel_init(timer, TIM_OC1); } if (bit_is_set(channels_mask, 1)) { actuators_pwm_arch_channel_init(timer, TIM_OC2); } if (bit_is_set(channels_mask, 2)) { actuators_pwm_arch_channel_init(timer, TIM_OC3); } if (bit_is_set(channels_mask, 3)) { actuators_pwm_arch_channel_init(timer, TIM_OC4); } /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(timer, TIM_OC1, 1000); //timer_set_oc_value(timer, TIM_OC2, 1000); //timer_set_oc_value(timer, TIM_OC3, 1000); //timer_set_oc_value(timer, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(timer); /* Counter enable. */ timer_enable_counter(timer); }
void accel_highg_init() { uint8_t channel_array[16]; gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0 | GPIO1 | GPIO2); adc_set_dual_mode(ADC_CR1_DUALMOD_RSM); /* ADC1 + ADC2 dual mode */ adc_set_dual_mode(ADC_CR1_DUALMOD_ISM); adc_enable_external_trigger_injected(ADC1, ADC_CR2_JEXTSEL_TIM1_TRGO); adc_enable_external_trigger_injected(ADC3, ADC_CR2_JEXTSEL_TIM1_TRGO); adc_enable_dma(ADC1); adc_enable_dma(ADC3); adc_power_on(ADC1); adc_power_on(ADC2); adc_power_on(ADC3); adc_stab_sleep(); adc_reset_calibration(ADC1); adc_reset_calibration(ADC2); adc_reset_calibration(ADC3); adc_calibration(ADC1); adc_calibration(ADC2); adc_calibration(ADC3); memset(channel_array, 0, sizeof(channel_array)); channel_array[0] = 10; adc_set_injected_sequence(ADC1, 1, channel_array); channel_array[0] = 11; adc_set_injected_sequence(ADC2, 1, channel_array); channel_array[0] = 12; adc_set_injected_sequence(ADC3, 1, channel_array); timer_reset(TIM1); timer_enable_irq(TIM1, TIM_DIER_UIE); timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* 500Hz */ timer_set_prescaler(TIM1, 64); timer_set_period(TIM1, 2250); /* Generate TRGO */ timer_set_master_mode(TIM1, TIM_CR2_MMS_UPDATE); dma_set_peripheral_address(DMA1, DMA_CHANNEL5, (uint32_t) &ADC1_DR); dma_set_read_from_memory(DMA1, DMA_CHANNEL5); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL5); dma_set_peripheral_size(DMA1, DMA_CHANNEL5, DMA_CCR_PSIZE_32BIT); dma_set_memory_size(DMA1, DMA_CHANNEL5, DMA_CCR_MSIZE_32BIT); dma_set_priority(DMA1, DMA_CHANNEL5, DMA_CCR_PL_HIGH); dma_set_peripheral_address(DMA1, DMA_CHANNEL6, (uint32_t) &ADC3_DR); dma_set_read_from_peripheral(DMA1, DMA_CHANNEL6); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL6); dma_set_peripheral_size(DMA1, DMA_CHANNEL6, DMA_CCR_PSIZE_16BIT); dma_set_memory_size(DMA1, DMA_CHANNEL6, DMA_CCR_MSIZE_16BIT); dma_set_priority(DMA1, DMA_CHANNEL6, DMA_CCR_PL_HIGH); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL5); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL6); }
/* F1 MCUs have no GPIO_AFR[HL], so turn off PWM if there's a conflict * on this GPIO bit. */ static void disable_timer_if_necessary(timer_dev *dev, uint8 ch) { if (dev != NULL) { timer_set_mode(dev, ch, TIMER_DISABLED); } }
static void tim_setup(void) { /* Enable TIM2 clock. */ rcc_periph_clock_enable(RCC_TIM2); /* Enable TIM2 interrupt. */ nvic_enable_irq(NVIC_TIM2_IRQ); /* Reset TIM2 peripheral. */ timer_reset(TIM2); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Reset prescaler value. * Running the clock at 5kHz. */ /* * On STM32F4 the timers are not running directly from pure APB1 or * APB2 clock busses. The APB1 and APB2 clocks used for timers might * be the double of the APB1 and APB2 clocks. This depends on the * setting in DCKCFGR register. By default the behaviour is the * following: If the Prescaler APBx is greater than 1 the derived timer * APBx clocks will be double of the original APBx frequencies. Only if * the APBx prescaler is set to 1 the derived timer APBx will equal the * original APBx frequencies. * * In our case here the APB1 is devided by 4 system frequency and APB2 * divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will * be 2 x APB2. So when we try to calculate the prescaler value we have * to use rcc_apb1_freqency * 2!!! * * For additional information see reference manual for the stm32f4 * familiy of chips. Page 204 and 213 */ timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000)); /* Enable preload. */ timer_disable_preload(TIM2); /* Continous mode. */ timer_continuous_mode(TIM2); /* Period (36kHz). */ timer_set_period(TIM2, 65535); /* Disable outputs. */ timer_disable_oc_output(TIM2, TIM_OC1); timer_disable_oc_output(TIM2, TIM_OC2); timer_disable_oc_output(TIM2, TIM_OC3); timer_disable_oc_output(TIM2, TIM_OC4); /* -- OC1 configuration -- */ /* Configure global mode of line 1. */ timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM2, TIM_OC1, 1000); /* ---- */ /* ARR reload enable. */ timer_disable_preload(TIM2); /* Counter enable. */ timer_enable_counter(TIM2); /* Enable commutation interrupt. */ timer_enable_irq(TIM2, TIM_DIER_CC1IE); }
static void tim_setup(void) { /* Enable TIM1 clock. */ rcc_periph_clock_enable(RCC_TIM1); /* Configure TIM1_CH1 and TIM1_CH2 as inputs */ gpio_set_mode(GPIO_BANK_TIM1_CH1, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH1); gpio_set_mode(GPIO_BANK_TIM1_CH2, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH2); /* Enable TIM1 interrupt. */ nvic_enable_irq(NVIC_TIM1_CC_IRQ); /* Reset TIM1 peripheral. */ /* timer_reset(TIM1); */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* set prescaler value -> 1us */ timer_set_prescaler(TIM1, 72 - 1); timer_set_period(TIM1, 0xFFFF); timer_set_repetition_counter(TIM1, 0); /* Enable preload */ /* timer_disable_preload(TIM1); */ /* Continous mode */ timer_continuous_mode(TIM1); /* configure Channel 1 */ timer_ic_set_input(TIM1, TIM_IC1, TIM_IC_IN_TI1); timer_ic_set_filter(TIM1, TIM_IC1, TIM_IC_OFF); timer_ic_set_polarity(TIM1, TIM_IC1, TIM_IC_RISING); timer_ic_set_prescaler(TIM1, TIM_IC1, TIM_IC_PSC_OFF); timer_ic_enable(TIM1, TIM_IC1); timer_clear_flag(TIM1, TIM_SR_CC1IF); timer_enable_irq(TIM1, TIM_DIER_CC1IE); /* configure Channel 2 */ timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2); timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF); timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING); timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF); timer_ic_enable(TIM1, TIM_IC2); timer_clear_flag(TIM1, TIM_SR_CC2IF); timer_enable_irq(TIM1, TIM_DIER_CC2IE); timer_enable_counter(TIM1); #if 0 /* Disable outputs. */ timer_disable_oc_output(TIM1, TIM_OC1); timer_disable_oc_output(TIM1, TIM_OC2); timer_disable_oc_output(TIM1, TIM_OC3); timer_disable_oc_output(TIM1, TIM_OC4); /* -- OC1 configuration -- */ /* Configure global mode of line 1. */ timer_disable_oc_clear(TIM1, TIM_OC1); timer_disable_oc_preload(TIM1, TIM_OC1); timer_set_oc_slow_mode(TIM1, TIM_OC1); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM1, TIM_OC1, 1000); /* ---- */ /* ARR reload enable. */ timer_disable_preload(TIM1); /* Counter enable. */ timer_enable_counter(TIM1); /* Enable commutation interrupt. */ timer_enable_irq(TIM1, TIM_DIER_CC1IE); #endif }
/** Set Timer configuration */ static inline void set_servo_timer(uint32_t timer, uint32_t period, uint8_t channels_mask) { timer_reset(timer); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ if ((timer == TIM9) || (timer == TIM12)) //There are no EDGE and DIR settings in TIM9 and TIM12 timer_set_mode(timer, TIM_CR1_CKD_CK_INT, 0, 0); else timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // TIM1, 8 and 9 use APB2 clock, all others APB1 if (timer != TIM1 && timer != TIM8 && timer != TIM9) { timer_set_prescaler(timer, (TIMER_APB1_CLK / ONE_MHZ_CLK) - 1); // 1uS } else { // TIM9, 1 and 8 use APB2 clock timer_set_prescaler(timer, (TIMER_APB2_CLK / ONE_MHZ_CLK) - 1); } timer_disable_preload(timer); timer_continuous_mode(timer); timer_set_period(timer, (ONE_MHZ_CLK / period) - 1); /* Disable outputs and configure channel if needed. */ if (bit_is_set(channels_mask, 0)) { actuators_pwm_arch_channel_init(timer, TIM_OC1); } if (bit_is_set(channels_mask, 1)) { actuators_pwm_arch_channel_init(timer, TIM_OC2); } if (bit_is_set(channels_mask, 2)) { actuators_pwm_arch_channel_init(timer, TIM_OC3); } if (bit_is_set(channels_mask, 3)) { actuators_pwm_arch_channel_init(timer, TIM_OC4); } /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(timer, TIM_OC1, 1000); //timer_set_oc_value(timer, TIM_OC2, 1000); //timer_set_oc_value(timer, TIM_OC3, 1000); //timer_set_oc_value(timer, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(timer); /* Counter enable. */ timer_enable_counter(timer); }
void speaker_setMode(int channel, timer_mode mode) { timer_set_mode(SPEAKER_TIMER, (uint8)channel, (timer_mode)mode); }
void HardwareTimer::setMode(int channel, timer_mode mode) { timer_set_mode(this->dev, (uint8)channel, (timer_mode)mode); }
void pinMode(uint8 pin, WiringPinMode w_mode) { if (pin >= BOARD_NR_GPIO_PINS) { return; } gpio_pin_mode mode; // People always do the silly pin-toggle speed benchmark, so let's // accomodate them: unsigned flags = GPIO_MODEF_SPEED_HIGH; bool pwm = false; switch(w_mode) { case OUTPUT: mode = GPIO_MODE_OUTPUT; break; case OUTPUT_OPEN_DRAIN: mode = GPIO_MODE_OUTPUT; flags |= GPIO_MODEF_TYPE_OD; break; case INPUT: case INPUT_FLOATING: mode = GPIO_MODE_INPUT; break; case INPUT_ANALOG: mode = GPIO_MODE_ANALOG; break; case INPUT_PULLUP: mode = GPIO_MODE_INPUT; flags |= GPIO_MODEF_PUPD_PU; break; case INPUT_PULLDOWN: mode = GPIO_MODE_INPUT; flags |= GPIO_MODEF_PUPD_PD; break; case PWM: mode = GPIO_MODE_AF; pwm = true; break; case PWM_OPEN_DRAIN: mode = GPIO_MODE_AF; flags |= GPIO_MODEF_TYPE_OD; pwm = true; break; default: ASSERT(0); // Can't happen return; } const stm32_pin_info *info = &PIN_MAP[pin]; if (pwm) { /* If enabling PWM, tell the timer to do PWM, and tell the pin * to listen to the right timer. */ ASSERT(info->timer_device != NULL); if (info->timer_device == NULL) { return; } gpio_af timer_af = timer_get_af(info->timer_device); timer_set_mode(info->timer_device, info->timer_channel, TIMER_PWM); gpio_set_af(info->gpio_device, info->gpio_bit, timer_af); } gpio_set_modef(info->gpio_device, info->gpio_bit, mode, flags); }
/*--------------------------------------------------------------------*/ void hardware_setup(void) { /* Setup the clock to 72MHz from the 8MHz external crystal */ rcc_clock_setup_in_hse_8mhz_out_72mhz(); /* Enable GPIOA, GPIOB and GPIOC clocks. APB2 (High Speed Advanced Peripheral Bus) peripheral clock enable register (RCC_APB2ENR) Set RCC_APB2ENR_IOPBEN for port B, RCC_APB2ENR_IOPAEN for port A and RCC_APB2ENR_IOPAEN for Alternate Function clock */ rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); rcc_periph_clock_enable(RCC_AFIO); /* Digital Test output PC0 */ gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO0); /* ----------------- Timer 2 Interrupt and DAC control*/ /* Enable TIM2 clock. */ rcc_periph_clock_enable(RCC_TIM2); /* Enable TIM2 interrupt. */ nvic_enable_irq(NVIC_TIM2_IRQ); timer_reset(TIM2); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Continous mode. */ timer_continuous_mode(TIM2); timer_set_period(TIM2, 1000); /* Disable outputs. */ timer_disable_oc_output(TIM2, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4); /* Configure global mode of output channel 1, disabling the output. */ timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM2, TIM_OC1, 1000); /* ARR reload disable. */ timer_disable_preload(TIM2); /* Counter enable. */ timer_enable_counter(TIM2); /* Enable commutation interrupt. */ timer_enable_irq(TIM2, TIM_DIER_CC1IE); /* Set port PA4 for DAC1 to 'alternate function'. Output driver mode is ignored. */ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4); /* Enable the DAC clock on APB1 */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN); /* Setup the DAC, software trigger source. Assume the DAC has woken up by the time the first interrupt occurs */ dac_trigger_enable(CHANNEL_D); dac_set_trigger_source(DAC_CR_TSEL1_SW | DAC_CR_TSEL2_SW); dac_enable(CHANNEL_D); dac_load_data_buffer_dual(0, 0, RIGHT8); }
void hardware_setup(void) { /* Set the clock to 72MHz from the 8MHz external crystal */ rcc_clock_setup_in_hse_8mhz_out_72mhz(); /* Enable GPIOA, GPIOB and GPIOC clocks. APB2 (High Speed Advanced Peripheral Bus) peripheral clock enable register (RCC_APB2ENR) Set RCC_APB2ENR_IOPBEN for port B, RCC_APB2ENR_IOPAEN for port A and RCC_APB2ENR_IOPAEN for Alternate Function clock */ rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); rcc_periph_clock_enable(RCC_AFIO); /* Set ports PA8 (TIM1_CH1), PA9 (TIM1_CH2), PB13 (TIM1_CH1N), PB14 (TIM1_CH2N) for PWM, to 'alternate function output push-pull'. */ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8 | GPIO9); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO14); /* ------------------ Timer 1 PWM */ /* Enable TIM1 clock. */ rcc_periph_clock_enable(RCC_TIM1); /* Reset TIM1 peripheral. */ timer_reset(TIM1); /* Set Timer global mode: * - No division * - Alignment centre mode 1 (up/down counting, interrupt on downcount only) * - Direction up (when centre mode is set it is read only, changes by hardware) */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); /* Set Timer output compare mode: * - Channel 1 * - PWM mode 2 (output low when CNT < CCR1, high otherwise) */ timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2); timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM2); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_enable_break_main_output(TIM1); /* Set the polarity of OCN to be high to match that of the OC, for switching the low MOSFET through an inverting level shifter */ timer_set_oc_polarity_high(TIM1, TIM_OC2N); /* The ARR (auto-preload register) sets the PWM period to 62.5kHz from the 72 MHz clock.*/ timer_enable_preload(TIM1); timer_set_period(TIM1, PERIOD); /* The CCR1 (capture/compare register 1) sets the PWM duty cycle to default 50% */ timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_value(TIM1, TIM_OC1, (PERIOD*20)/100); timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_value(TIM1, TIM_OC2, (PERIOD*50)/100); /* Force an update to load the shadow registers */ timer_generate_event(TIM1, TIM_EGR_UG); /* Start the Counter. */ timer_enable_counter(TIM1); }