/**
* Where the magic starts.
*/
void main() {
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer.
//BCSCTL1 = CALBC1_1MHZ; // Set range.
//DCOCTL = CALDCO_1MHZ; // SMCLK = DCO = 1MHz
//BCSCTL2 &= ~(DIVS_3);
// Setup the PWM stuff, ADC, and interrupts.
setup_pwm();
setup_interrupts();
_BIS_SR(GIE); // TODO: Do (LPMX + GIE) for low-power + interrupts.
//__enable_interrupt();
// Initialize the shift register driver.
shift_register_setup();
shift_out(shift_default_on);
// Setup the LCD driver.
lcd_init(TRUE, TRUE);
// Initilalize the voltage regulator driver.
vreg_init();
// Go to the home screen.
print_screen(HOME_SCREEN);
while (TRUE) {
}
}
void main(void) {
volatile packet_t *p;
volatile uint8_t t=20;
uint8_t chan;
char c;
gpio_data(0);
gpio_pad_dir_set( 1ULL << LED );
/* read from the data register instead of the pad */
/* this is needed because the led clamps the voltage low */
gpio_data_sel( 1ULL << LED);
/* trim the reference osc. to 24MHz */
trim_xtal();
uart_init(UART1, 115200);
vreg_init();
maca_init();
/* sets up tx_on, should be a board specific item */
*GPIO_FUNC_SEL2 = (0x01 << ((44-16*2)*2));
gpio_pad_dir_set( 1ULL << 44 );
set_power(0x0f); /* 0dbm */
chan = 0;
set_channel(chan); /* channel 11 */
*MACA_MACPANID = 0xaaaa;
*MACA_MAC16ADDR = 0x1111;
*MACA_TXACKDELAY = 68; /* 68 puts the tx ack at about the correct spot */
set_prm_mode(AUTOACK);
print_welcome("rftest-rx");
while(1) {
/* call check_maca() periodically --- this works around */
/* a few lockup conditions */
check_maca();
if((p = rx_packet())) {
/* print and free the packet */
printf("autoack-rx --- ");
print_packet(p);
maca_free_packet(p);
}
if(uart1_can_get()) {
c = uart1_getc();
if(c == 'z') t++;
if(c == 'x') t--;
*MACA_TXACKDELAY = t;
printf("tx ack delay: %d\n\r", t);
}
}
}
void main(void) {
nvmType_t type=0;
nvmErr_t err;
uint32_t buf[WRITE_NBYTES/4];
uint32_t i;
uart_init(INC, MOD, SAMP);
print_welcome("nvm-write");
vreg_init();
if(NVM_INTERFACE == gNvmInternalInterface_c)
{
printf("Detecting internal nvm\n\r");
} else {
printf("Setting up gpio\r\n");
/* set SPI func */
GPIO->FUNC_SEL.GPIO_04 = 1;
GPIO->FUNC_SEL.GPIO_05 = 1;
GPIO->FUNC_SEL.GPIO_06 = 1;
GPIO->FUNC_SEL.GPIO_07 = 1;
printf("Detecting external nvm\n\r");
}
err = nvm_detect(NVM_INTERFACE, &type);
printf("nvm_detect returned: 0x%02x type is: 0x%08x\r\n", err, (unsigned int)type);
buf[0] = WRITEVAL0;
buf[1] = WRITEVAL1;
err = nvm_erase(NVM_INTERFACE, type, 1 << WRITE_ADDR/4096);
printf("nvm_erase returned: 0x%02x\r\n", err);
err = nvm_write(NVM_INTERFACE, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES);
printf("gnychis nvm_write returned: 0x%02x\r\n", err);
printf("writing\n\r");
for(i=0; i<WRITE_NBYTES/4; i++) {
printf("0x%08x\r\n", (unsigned int)buf[i]);
buf[i] = 0x00000000; /* clear buf for the read */
}
err = nvm_read(NVM_INTERFACE, type, (uint8_t *)buf, WRITE_ADDR, WRITE_NBYTES);
printf("nvm_read returned: 0x%02x\r\n", err);
printf("reading\r\n");
for(i=0; i<WRITE_NBYTES/4; i++) {
printf("0x%08x\r\n", (unsigned int)buf[i]);
}
while(1) {continue;};
}
static int __init snddev_icodec_init(void)
{
s32 rc;
struct snddev_icodec_drv_state *icodec_drv = &snddev_icodec_drv;
rc = platform_driver_register(&snddev_icodec_driver);
if (IS_ERR_VALUE(rc)) {
pr_err("%s: platform_driver_register for snddev icodec failed\n",
__func__);
goto error_snddev_icodec_driver;
}
rc = platform_driver_register(&msm_cdcclk_ctl_driver);
if (IS_ERR_VALUE(rc)) {
pr_err("%s: platform_driver_register for msm snddev failed\n",
__func__);
goto error_msm_cdcclk_ctl_driver;
}
rc = platform_driver_register(&msm_icodec_gpio_driver);
if (IS_ERR_VALUE(rc)) {
pr_err("%s: platform_driver_register for msm snddev gpio failed\n",
__func__);
goto error_msm_icodec_gpio_driver;
}
mutex_init(&icodec_drv->rx_lock);
mutex_init(&icodec_drv->lb_lock);
mutex_init(&icodec_drv->tx_lock);
icodec_drv->rx_active = 0;
icodec_drv->tx_active = 0;
icodec_drv->snddev_vreg = vreg_init();
pm_qos_add_request(&icodec_drv->tx_pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
pm_qos_add_request(&icodec_drv->rx_pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
return 0;
error_msm_icodec_gpio_driver:
platform_driver_unregister(&msm_cdcclk_ctl_driver);
error_msm_cdcclk_ctl_driver:
platform_driver_unregister(&snddev_icodec_driver);
error_snddev_icodec_driver:
return -ENODEV;
}
static int __init snddev_icodec_init(void)
{
s32 rc;
struct snddev_icodec_drv_state *icodec_drv = &snddev_icodec_drv;
rc = platform_driver_register(&snddev_icodec_driver);
if (IS_ERR_VALUE(rc)) {
pr_err("%s: platform_driver_register for snddev icodec failed\n",
__func__);
goto error_snddev_icodec_driver;
}
rc = platform_driver_register(&msm_cdcclk_ctl_driver);
if (IS_ERR_VALUE(rc)) {
pr_err("%s: platform_driver_register for msm snddev failed\n",
__func__);
goto error_msm_cdcclk_ctl_driver;
}
rc = platform_driver_register(&msm_icodec_gpio_driver);
if (IS_ERR_VALUE(rc)) {
pr_err("%s: platform_driver_register for msm snddev gpio failed\n",
__func__);
goto error_msm_icodec_gpio_driver;
}
mutex_init(&icodec_drv->rx_lock);
mutex_init(&icodec_drv->lb_lock);
mutex_init(&icodec_drv->tx_lock);
icodec_drv->rx_active = 0;
icodec_drv->tx_active = 0;
icodec_drv->snddev_vreg = vreg_init();
wake_lock_init(&icodec_drv->tx_idlelock, WAKE_LOCK_IDLE,
"snddev_tx_idle");
wake_lock_init(&icodec_drv->rx_idlelock, WAKE_LOCK_IDLE,
"snddev_rx_idle");
return 0;
error_msm_icodec_gpio_driver:
platform_driver_unregister(&msm_cdcclk_ctl_driver);
error_msm_cdcclk_ctl_driver:
platform_driver_unregister(&snddev_icodec_driver);
error_snddev_icodec_driver:
return -ENODEV;
}
void main(void) {
volatile packet_t *p;
char c;
uint16_t r=30; /* start reception 100us before ack should arrive */
uint16_t end=180; /* 750 us receive window*/
/* trim the reference osc. to 24MHz */
trim_xtal();
uart_init(UART1, 115200);
vreg_init();
maca_init();
set_channel(0); /* channel 11 */
// set_power(0x0f); /* 0xf = -1dbm, see 3-22 */
// set_power(0x11); /* 0x11 = 3dbm, see 3-22 */
set_power(0x12); /* 0x12 is the highest, not documented */
/* sets up tx_on, should be a board specific item */
GPIO->FUNC_SEL_44 = 1;
GPIO->PAD_DIR_SET_44 = 1;
GPIO->FUNC_SEL_45 = 2;
GPIO->PAD_DIR_SET_45 = 1;
*MACA_RXACKDELAY = r;
printf("rx warmup: %d\n\r", (int)(*MACA_WARMUP & 0xfff));
*MACA_RXEND = end;
printf("rx end: %d\n\r", (int)(*MACA_RXEND & 0xfff));
set_prm_mode(AUTOACK);
print_welcome("rftest-tx");
while(1) {
/* call check_maca() periodically --- this works around */
/* a few lockup conditions */
check_maca();
while((p = rx_packet())) {
if(p) {
printf("RX: ");
print_packet(p);
free_packet(p);
}
}
if(uart1_can_get()) {
c = uart1_getc();
switch(c) {
case 'z':
r++;
if(r > 4095) { r = 0; }
*MACA_RXACKDELAY = r;
printf("rx ack delay: %d\n\r", r);
break;
case 'x':
if(r == 0) { r = 4095; } else { r--; }
*MACA_RXACKDELAY = r;
printf("rx ack delay: %d\n\r", r);
break;
case 'q':
end++;
if(r > 4095) { r = 0; }
*MACA_RXEND = end;
printf("rx end: %d\n\r", end);
break;
case 'w':
end--;
if(r == 0) { r = 4095; } else { r--; }
*MACA_RXEND = end;
printf("rx end: %d\n\r", end);
break;
default:
p = get_free_packet();
if(p) {
fill_packet(p);
printf("autoack-tx --- ");
print_packet(p);
tx_packet(p);
}
break;
}
}
}
}
void main(void) {
volatile packet_t *p;
#ifdef CARRIER_SENSE
volatile uint32_t i;
#endif
uint16_t r=30; /* start reception 100us before ack should arrive */
uint16_t end=180; /* 750 us receive window*/
/* trim the reference osc. to 24MHz */
trim_xtal();
uart_init(INC, MOD, SAMP);
vreg_init();
maca_init();
///* Setup the timer */
*TMR_ENBL = 0; /* tmrs reset to enabled */
*TMR0_SCTRL = 0;
*TMR0_LOAD = 0; /* reload to zero */
*TMR0_COMP_UP = 18750; /* trigger a reload at the end */
*TMR0_CMPLD1 = 18750; /* compare 1 triggered reload level, 10HZ maybe? */
*TMR0_CNTR = 0; /* reset count register */
*TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
*TMR_ENBL = 0xf; /* enable all the timers --- why not? */
set_channel(CHANNEL); /* channel 11 */
set_power(0x12); /* 0x12 is the highest, not documented */
/* sets up tx_on, should be a board specific item */
GPIO->FUNC_SEL_44 = 1;
GPIO->PAD_DIR_SET_44 = 1;
GPIO->FUNC_SEL_45 = 2;
GPIO->PAD_DIR_SET_45 = 1;
*MACA_RXACKDELAY = r;
*MACA_RXEND = end;
set_prm_mode(AUTOACK);
while(1) {
if((*TMR0_SCTRL >> 15) != 0)
tick();
/* call check_maca() periodically --- this works around */
/* a few lockup conditions */
check_maca();
while((p = rx_packet())) {
if(p) free_packet(p);
}
p = get_free_packet();
if(p) {
fill_packet(p);
#ifdef CARRIER_SENSE
for(i=0; i<POWER_DELAY; i++) {continue;}
while(get_power()>74) {}
#endif
#ifdef BLOCKING_TX
blocking_tx_packet(p);
#else
tx_packet(p);
#endif
current_pkts++;
#if defined(RANDOM_WAIT_TIME) || defined(FIXED_WAIT)
random_wait();
#endif
}
}
}
int main(void) {
nvmType_t type=0;
nvmErr_t err;
volatile uint8_t c;
volatile uint32_t i;
volatile uint32_t buf[4];
volatile uint32_t len=0;
volatile uint32_t state = SCAN_X;
volatile uint32_t addr,data;
uart_init(UART1, 115200);
disable_irq(UART1);
vreg_init();
dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err);
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)nvm_base, NVM_BASE, 0x100);
dbg_putstr("nvm_read returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* erase the flash */
nvm_setsvar(0);
err = nvm_erase(gNvmInternalInterface_c, type, 0x40000000);
dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)nvm_base, NVM_BASE, 0x100);
dbg_putstr("nvm_write returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* say we are ready */
len = 0;
putstr("ready");
flushrx();
/* read the length */
for(i=0; i<4; i++) {
c = uart1_getc();
/* bail if the first byte of the length is zero */
len += (c<<(i*8));
}
dbg_putstr("len: ");
dbg_put_hex32(len);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
putstr("flasher done\n\r");
state = SCAN_X; addr=0;
while((c=getc())) {
if(state == SCAN_X) {
/* read until we see an 'x' */
if(c==0) { break; }
if(c!='x'){ continue; }
/* go to read_chars once we have an 'x' */
state = READ_CHARS;
i = 0;
}
if(state == READ_CHARS) {
/* read all the chars up to a ',' */
((uint8_t *)buf)[i++] = c;
/* after reading a ',' */
/* goto PROCESS state */
if((c == ',') || (c == 0)) { state = PROCESS; }
}
if(state == PROCESS) {
if(addr==0) {
/*interpret the string as the starting address */
addr = to_u32(buf);
} else {
/* string is data to write */
data = to_u32(buf);
putstr("writing addr ");
put_hex32(NVM_BASE+addr);
putstr(" data ");
put_hex32(data);
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&data, NVM_BASE+addr, 4);
addr += 4;
putstr(" err ");
put_hex32(err);
putstr("\n\r");
}
/* look for the next 'x' */
state=SCAN_X;
}
}
putstr("process flasher done\n\r");
while(1) {continue;};
}
void main(void) {
nvmType_t type=0;
nvmErr_t err;
volatile uint8_t c;
volatile uint32_t i;
volatile uint32_t buf[4];
volatile uint32_t len=0;
volatile uint32_t state = SCAN_X;
volatile uint32_t addr,data;
uart_init(INC, MOD, SAMP);
disable_irq(UART1);
vreg_init();
dbg_putstr("Detecting internal nvm\n\r");
err = nvm_detect(gNvmInternalInterface_c, &type);
dbg_putstr("nvm_detect returned: 0x");
dbg_put_hex(err);
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* erase the flash */
err = nvm_erase(gNvmInternalInterface_c, type, 0x7fffffff);
dbg_putstr("nvm_erase returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* say we are ready */
len = 0;
putstr("ready");
flushrx();
/* read the length */
for(i=0; i<4; i++) {
c = uart1_getc();
/* bail if the first byte of the length is zero */
len += (c<<(i*8));
}
dbg_putstr("len: ");
dbg_put_hex32(len);
dbg_putstr("\n\r");
/* write the OKOK magic */
#if BOOT_OK
((uint8_t *)buf)[0] = 'O'; ((uint8_t *)buf)[1] = 'K'; ((uint8_t *)buf)[2] = 'O'; ((uint8_t *)buf)[3] = 'K';
#elif BOOT_SECURE
((uint8_t *)buf)[0] = 'S'; ((uint8_t *)buf)[1] = 'E'; ((uint8_t *)buf)[2] = 'C'; ((uint8_t *)buf)[3] = 'U';
#else
((uint8_t *)buf)[0] = 'N'; ((uint8_t *)buf)[1] = 'O'; ((uint8_t *)buf)[2] = 'N'; ((uint8_t *)buf)[3] = 'O';
#endif
dbg_putstr(" type is: 0x");
dbg_put_hex32(type);
dbg_putstr("\n\r");
/* don't make a valid boot image if the received length is zero */
if(len == 0) {
((uint8_t *)buf)[0] = 'N';
((uint8_t *)buf)[1] = 'O';
((uint8_t *)buf)[2] = 'N';
((uint8_t *)buf)[3] = 'O';
}
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, 0, 4);
dbg_putstr("nvm_write returned: 0x");
dbg_put_hex(err);
dbg_putstr("\n\r");
/* write the length */
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&len, 4, 4);
/* read a byte, write a byte */
for(i=0; i<len; i++) {
c = getc();
err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&c, 8+i, 1);
}
putstr("flasher done\n\r");
state = SCAN_X; addr=0;
while((c=getc())) {
if(state == SCAN_X) {
/* read until we see an 'x' */
if(c==0) { break; }
if(c!='x'){ continue; }
/* go to read_chars once we have an 'x' */
state = READ_CHARS;
i = 0;
}
if(state == READ_CHARS) {
/* read all the chars up to a ',' */
((uint8_t *)buf)[i++] = c;
/* after reading a ',' */
/* goto PROCESS state */
if((c == ',') || (c == 0)) { state = PROCESS; }
}
if(state == PROCESS) {
if(addr==0) {
/*interpret the string as the starting address */
addr = to_u32(buf);
} else {
/* string is data to write */
data = to_u32(buf);
putstr("writing addr ");
put_hex32(addr);
putstr(" data ");
put_hex32(data);
putstr("\n\r");
err = nvm_write(gNvmInternalInterface_c, 1, (uint8_t *)&data, addr, 4);
addr += 4;
}
/* look for the next 'x' */
state=SCAN_X;
}
}
while(1) {continue;};
}