void gamate_state::machine_start()
{
m_cart_ptr = memregion("maincpu")->base() + 0x6000;
if (m_cart->exists())
{
// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r));
m_cart_ptr = m_cart->get_rom_base();
m_bankmulti->set_base(m_cart->get_rom_base()+1);
m_bank->set_base(m_cart->get_rom_base()+0x4000); // bankswitched games in reality no offset
}
// m_bios[0xdf1]=0xea; m_bios[0xdf2]=0xea; // default bios: $47 protection readback
card_protection.set=false;
bank_multi=0;
card_protection.unprotected=false;
timer2->enable(TRUE);
timer2->reset(m_maincpu->cycles_to_attotime(1000));
#if 0
save_item(NAME(m_video.data));
save_item(NAME(m_video.index));
save_item(NAME(m_video.x));
save_item(NAME(m_video.y));
save_item(NAME(m_video.mode));
save_item(NAME(m_video.delayed));
save_item(NAME(m_video.pixels));
save_item(NAME(m_ports));
save_item(NAME(m_ram));
#endif
}
void nanos_state::machine_reset()
{
address_space &space = m_maincpu->space(AS_PROGRAM);
space.install_write_bank(0x0000, 0x0fff, "bank3");
space.install_write_bank(0x1000, 0xffff, "bank2");
m_bank1->set_base(m_region_maincpu->base());
m_bank2->set_base(m_ram->pointer() + 0x1000);
m_bank3->set_base(m_ram->pointer());
machine().device<floppy_connector>("upd765:0")->get_device()->mon_w(false);
}
void oric_state::machine_start()
{
machine_start_common();
m_bank_c000_r->set_base(m_rom->base());
m_bank_e000_r->set_base(m_rom->base() + 0x2000);
m_bank_f800_r->set_base(m_rom->base() + 0x3800);
}
void atm_state::atm_update_memory()
{
UINT8 *messram = m_ram->pointer();
m_screen_location = messram + ((m_port_7ffd_data & 8) ? (7<<14) : (5<<14));
m_bank4->set_base(messram + ((m_port_7ffd_data & 0x07) * 0x4000));
if (m_beta->started() && m_beta->is_active() && !( m_port_7ffd_data & 0x10 ) )
m_ROMSelection = 3;
else
/* ROM switching */
m_ROMSelection = BIT(m_port_7ffd_data, 4) ;
/* rom 0 is 128K rom, rom 1 is 48 BASIC */
m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]);
}
void odyssey2_state::switch_banks()
{
switch ( m_cart_size )
{
case 12288:
/* 12KB cart support (for instance, KTAA as released) */
m_bank1->set_base( m_user1->base() + (m_p1 & 0x03) * 0xC00 );
m_bank2->set_base( m_user1->base() + (m_p1 & 0x03) * 0xC00 + 0x800 );
break;
case 16384:
/* 16KB cart support (for instance, full sized version KTAA) */
m_bank1->set_base( m_user1->base() + (m_p1 & 0x03) * 0x1000 + 0x400 );
m_bank2->set_base( m_user1->base() + (m_p1 & 0x03) * 0x1000 + 0xC00 );
break;
default:
m_bank1->set_base( m_user1->base() + (m_p1 & 0x03) * 0x800 );
m_bank2->set_base( m_user1->base() + (m_p1 & 0x03) * 0x800 );
break;
}
}
void scv_state::scv_set_banks()
{
m_cart_ram_enabled = false;
switch( m_cart_rom_size )
{
case 0:
case 0x2000:
m_bank0->set_base( m_cart_rom );
m_bank1->set_base( m_cart_rom );
m_bank2->set_base( m_cart_rom );
m_bank3->set_base( m_cart_rom );
m_bank4->set_base( m_cart_rom + 0x1000 );
break;
case 0x4000:
m_bank0->set_base( m_cart_rom );
m_bank1->set_base( m_cart_rom + 0x2000 );
m_bank2->set_base( m_cart_rom );
m_bank3->set_base( m_cart_rom + 0x2000 );
m_bank4->set_base( m_cart_rom + 0x3000 );
break;
case 0x8000:
m_bank0->set_base( m_cart_rom );
m_bank1->set_base( m_cart_rom + 0x2000 );
m_bank2->set_base( m_cart_rom + 0x4000 );
m_bank3->set_base( m_cart_rom + 0x6000 );
m_bank4->set_base( m_cart_rom + 0x7000 );
break;
case 0x10000:
m_bank0->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0x8000 : 0 ) );
m_bank1->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xa000 : 0x2000 ) );
m_bank2->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xc000 : 0x4000 ) );
m_bank3->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xe000 : 0x6000 ) );
m_bank4->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xf000 : 0x7000 ) );
break;
case 0x20000: /* Pole Position 2 */
int base = ( ( m_portc >> 5 ) & 0x03 ) * 0x8000 ;
m_bank0->set_base( m_cart_rom + base + 0 );
m_bank1->set_base( m_cart_rom + base + 0x2000 );
m_bank2->set_base( m_cart_rom + base + 0x4000 );
m_bank3->set_base( m_cart_rom + base + 0x6000 );
m_bank4->set_base( m_cart_rom + base + 0x7000 );
/* On-cart RAM is enabled when PC6 is high */
if ( m_cart_ram && m_portc & 0x40 )
{
m_cart_ram_enabled = true;
m_bank4->set_base( m_cart_ram );
}
break;
}
/* Check if cartridge RAM is available and should be enabled */
if ( m_cart_rom_size < 0x20000 && m_cart_ram && m_cart_ram_size && ( m_portc & 0x20 ) )
{
if ( m_cart_ram_size == 0x1000 )
{
m_bank4->set_base( m_cart_ram );
}
else
{
m_bank3->set_base( m_cart_ram );
m_bank4->set_base( m_cart_ram + 0x1000 );
}
m_cart_ram_enabled = true;
}
}
void sfkick_state::sfkick_remap_banks()
{
/* 0000-3fff */
switch(m_bank_cfg&3)
{
case 0: /* bios */
{
UINT8 *mem = m_region_bios->base();
m_bank1->set_base(mem);
m_bank2->set_base(mem+0x2000);
}
break;
case 1: /* ext rom */
{
UINT8 *mem = m_region_extrom->base();
m_bank1->set_base(mem+0x4000);
m_bank2->set_base(mem+0x6000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank1->set_base(mem+0x2000*m_bank[0]);
m_bank2->set_base(mem+0x2000*m_bank[1]);
}
break;
case 3: /* unknown */
{
UINT8 *mem = m_region_banked->base();
m_bank1->set_base(mem+0x18000);
m_bank2->set_base(mem+0x18000);
}
break;
}
/* 4000-7fff */
switch((m_bank_cfg>>2)&3)
{
case 0: /* bios - upper part */
{
UINT8 *mem = m_region_bios->base();
m_bank3->set_base(mem+0x4000);
m_bank4->set_base(mem+0x6000);
}
break;
case 1: /* unknown */
case 3:
{
UINT8 *mem = m_region_banked->base();
m_bank3->set_base(mem+0x18000);
m_bank4->set_base(mem+0x18000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank3->set_base(mem+0x2000*m_bank[2]);
m_bank4->set_base(mem+0x2000*m_bank[3]);
}
break;
}
/* 8000-bfff */
switch((m_bank_cfg>>4)&3)
{
case 0: /* cartridge */
{
UINT8 *mem = m_region_cartridge->base();
m_bank5->set_base(mem+0x4000);
m_bank6->set_base(mem+0x6000);
}
break;
case 1: /* unknown */
case 3:
{
UINT8 *mem = m_region_banked->base();
m_bank5->set_base(mem+0x18000);
m_bank6->set_base(mem+0x18000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank5->set_base(mem+0x2000*m_bank[4]);
m_bank6->set_base(mem+0x2000*m_bank[5]);
}
break;
}
/* c000-ffff */
switch((m_bank_cfg>>6)&3)
{
case 0: /* unknown */
case 1:
{
UINT8 *mem = m_region_banked->base();
m_bank7->set_base(mem+0x18000);
m_bank8->set_base(mem+0x18000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank7->set_base(mem+0x2000*m_bank[6]);
m_bank8->set_base(mem+0x2000*m_bank[7]);
}
break;
case 3: /* RAM */
{
m_bank7->set_base(m_main_mem.get());
m_bank8->set_base(m_main_mem.get()+0x2000);
}
break;
}
}