static void reset_registers(void) { uint32_t vectortable = read_word(VECTOR_TABLE_OFFSET); // R[0..12] = bits(32) UNKNOWN {nop} SW(&sp_main,read_word(vectortable) & 0xfffffffc); // sp_process = ((bits(30) UNKNOWN):'00') SW(&sp_process, SR(&sp_process) & ~0x3); CORE_reg_write(LR_REG, 0xFFFFFFFF); uint32_t tmp = read_word(vectortable+4); bool tbit = tmp & 0x1; CORE_reg_write(PC_REG, tmp & 0xfffffffe); if (! (tmp & 0x1) ) { WARN("Reset vector %08x at %08x invalid\n", tmp, vectortable+4); CORE_ERR_unpredictable("Thumb bit must be set for M-series\n"); } // ASPR = bits(32) UNKNOWN {nop} union ipsr_t ipsr = CORE_ipsr_read(); ipsr.bits.exception = 0; CORE_ipsr_write(ipsr); union epsr_t epsr = CORE_epsr_read(); epsr.bits.T = tbit; epsr.bits.ICI_IT_top = 0; epsr.bits.ICI_IT_bot = 0; CORE_epsr_write(epsr); }
static void reset_registers(void) { DBG2("begin\n"); uint32_t vectortable = read_word(VECTOR_TABLE_OFFSET); // R[0..12] = bits(32) UNKNOWN {nop} SW(&sp_main,read_word(vectortable) & 0xfffffffc); // sp_process = ((bits(30) UNKNOWN):'00') SW(&sp_process, SR(&sp_process) & ~0x3); CORE_reg_write(LR_REG, 0xFFFFFFFF); uint32_t tmp = read_word(vectortable+4); bool tbit = tmp & 0x1; CORE_reg_write(PC_REG, tmp & 0xfffffffe); if (!tbit) { WARN("Reset vector %08x at %08x invalid\n", tmp, vectortable+4); CORE_ERR_unpredictable("Thumb bit must be set for M-series\n"); } CORE_CurrentMode_write(Mode_Thread); // ASPR = bits(32) UNKNOWN {nop} union ipsr_t ipsr_temp = CORE_ipsr_read(); ipsr_temp.bits.exception = 0; CORE_ipsr_write(ipsr_temp); union epsr_t epsr_temp = CORE_epsr_read(); epsr_temp.bits.T = tbit; epsr_temp.bits.ICI_IT_top = 0; epsr_temp.bits.ICI_IT_bot = 0; CORE_epsr_write(epsr_temp); /// // B1.4.3: The special-purpose mask registers SW(&physical_primask, 0); SW(&physical_faultmask, 0); SW(&physical_basepri, 0); SW(&physical_control.storage, 0); DBG2("end\n"); }
EXPORT void CORE_xPSR_write(uint32_t xPSR) { union ipsr_t i = CORE_ipsr_read(); union epsr_t e = CORE_epsr_read(); union apsr_t a = CORE_apsr_read(); i.storage &= ~xPSR_ipsr_mask; i.storage |= xPSR & xPSR_ipsr_mask; CORE_ipsr_write(i); e.storage &= ~xPSR_epsr_mask; e.storage |= xPSR & xPSR_epsr_mask; CORE_epsr_write(e); uint32_t apsr_mask; if (HaveDSPExt()) apsr_mask = xPSR_apsr_dsp_mask; else apsr_mask = xPSR_apsr_nodsp_mask; a.storage &= ~apsr_mask; a.storage |= xPSR & apsr_mask; CORE_apsr_write(a); }