/* Low level init of the MAC and PHY */ STATIC err_t low_level_init(struct netif *netif) { lpc_enetdata_t *lpc_enetif = netif->state; err_t err = ERR_OK; #if defined(USE_RMII) Chip_ENET_Init(LPC_ETHERNET, true); #else Chip_ENET_Init(LPC_ETHERNET, false); #endif /* Initialize the PHY */ Chip_ENET_SetupMII(LPC_ETHERNET, Chip_ENET_FindMIIDiv(LPC_ETHERNET, 2500000), LPC_PHYDEF_PHYADDR); #if defined(USE_RMII) if (lpc_phy_init(true, msDelay) != SUCCESS) { return ERROR; } #else if (lpc_phy_init(false, msDelay) != SUCCESS) { return ERROR; } #endif /* Save station address */ Chip_ENET_SetADDR(LPC_ETHERNET, netif->hwaddr); /* Setup transmit and receive descriptors */ if (lpc_tx_setup(lpc_enetif) != ERR_OK) { return ERR_BUF; } if (lpc_rx_setup(lpc_enetif) != ERR_OK) { return ERR_BUF; } /* Enable packet reception */ #if IP_SOF_BROADCAST_RECV Chip_ENET_EnableRXFilter(LPC_ETHERNET, ENET_RXFILTERCTRL_APE | ENET_RXFILTERCTRL_ABE); #else Chip_ENET_EnableRXFilter(ENET_RXFILTERCTRL_APE); #endif /* Clear and enable rx/tx interrupts */ Chip_ENET_EnableInt(LPC_ETHERNET, RXINTGROUP | TXINTGROUP); /* Enable RX and TX */ Chip_ENET_TXEnable(LPC_ETHERNET); Chip_ENET_RXEnable(LPC_ETHERNET); return err; }
/* Low level init of the MAC and PHY */ static err_t low_level_init(struct netif *netif) { struct lpc_enetdata *lpc_netifdata = netif->state; /* Initialize via Chip ENET function */ Chip_ENET_Init(LPC_ETHERNET); /* Save MAC address */ Chip_ENET_SetADDR(LPC_ETHERNET, netif->hwaddr); /* Initial MAC configuration for checksum offload, full duplex, 100Mbps, disable receive own in half duplex, inter-frame gap of 64-bits */ LPC_ETHERNET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM | MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3); /* Setup filter */ #if IP_SOF_BROADCAST_RECV LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA; #else LPC_ETHERNET->MAC_FRAME_FILTER = 0; /* Only matching MAC address */ #endif /* Initialize the PHY */ #if defined(USE_RMII) if (lpc_phy_init(true, msDelay) != SUCCESS) { return ERROR; } intMask = RDES_CE | RDES_DE | RDES_RE | RDES_RWT | RDES_LC | RDES_OE | RDES_SAF | RDES_AFM; #else if (lpc_phy_init(false, msDelay) != SUCCESS) { return ERROR; } intMask = RDES_CE | RDES_RE | RDES_RWT | RDES_LC | RDES_OE | RDES_SAF | RDES_AFM; #endif /* Setup transmit and receive descriptors */ if (lpc_tx_setup(lpc_netifdata) != ERR_OK) { return ERR_BUF; } if (lpc_rx_setup(lpc_netifdata) != ERR_OK) { return ERR_BUF; } /* Flush transmit FIFO */ LPC_ETHERNET->DMA_OP_MODE = DMA_OM_FTF; /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at 64 bytes */ LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0); /* Clear all MAC interrupts */ LPC_ETHERNET->DMA_STAT = DMA_ST_ALL; /* Enable MAC interrupts */ LPC_ETHERNET->DMA_INT_EN = #if NO_SYS == 1 0; #else DMA_IE_TIE | DMA_IE_OVE | DMA_IE_UNE | DMA_IE_RIE | DMA_IE_NIE | DMA_IE_AIE | DMA_IE_TUE | DMA_IE_RUE; #endif /* Enable receive and transmit DMA processes */ LPC_ETHERNET->DMA_OP_MODE |= DMA_OM_ST | DMA_OM_SR; /* Enable packet reception */ LPC_ETHERNET->MAC_CONFIG |= MAC_CFG_RE | MAC_CFG_TE; /* Start receive polling */ LPC_ETHERNET->DMA_REC_POLL_DEMAND = 1; return ERR_OK; }
void tapdev_init(void) { Chip_ENET_Init(LPC_ETHERNET, useRMMI); }