/* * Initialize a SBSA generic Watchdog platform device info from GTDT */ static int __init gtdt_import_sbsa_gwdt(struct acpi_gtdt_watchdog *wd, int index) { struct platform_device *pdev; int irq = map_gt_gsi(wd->timer_interrupt, wd->timer_flags); int no_irq = 1; /* * According to SBSA specification the size of refresh and control * frames of SBSA Generic Watchdog is SZ_4K(Offset 0x000 – 0xFFF). */ struct resource res[] = { DEFINE_RES_MEM(wd->control_frame_address, SZ_4K), DEFINE_RES_MEM(wd->refresh_frame_address, SZ_4K), DEFINE_RES_IRQ(irq), }; pr_debug("found a Watchdog (0x%llx/0x%llx gsi:%u flags:0x%x).\n", wd->refresh_frame_address, wd->control_frame_address, wd->timer_interrupt, wd->timer_flags); if (!(wd->refresh_frame_address && wd->control_frame_address)) { pr_err(FW_BUG "failed to get the Watchdog base address.\n"); return -EINVAL; } if (!wd->timer_interrupt) pr_warn(FW_BUG "failed to get the Watchdog interrupt.\n"); else if (irq <= 0) pr_warn("failed to map the Watchdog interrupt.\n"); else no_irq = 0; /* * Add a platform device named "sbsa-gwdt" to match the platform driver. * "sbsa-gwdt": SBSA(Server Base System Architecture) Generic Watchdog * The platform driver (like drivers/watchdog/sbsa_gwdt.c)can get device * info below by matching this name. */ pdev = platform_device_register_simple("sbsa-gwdt", index, res, ARRAY_SIZE(res) - no_irq); if (IS_ERR(pdev)) { acpi_unregister_gsi(wd->timer_interrupt); return PTR_ERR(pdev); } return 0; }
static struct platform_device *db8500_add_msp_i2s(struct device *parent, int id, resource_size_t base, int irq, struct msp_i2s_platform_data *pdata) { struct platform_device *pdev; struct resource res[] = { DEFINE_RES_MEM(base, SZ_4K), DEFINE_RES_IRQ(irq), }; pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n", id, irq); pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); if (!pdev) { pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n", id); return NULL; } return pdev; }
#include <linux/sh_dma.h> #include <linux/sh_intc.h> #include <linux/usb/ohci_pdriver.h> #include <cpu/dma-register.h> #include <asm/mmzone.h> static struct plat_sci_port scif0_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .type = PORT_SCIF, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xffea0000, 0x100), DEFINE_RES_IRQ(evt2irq(0x700)), DEFINE_RES_IRQ(evt2irq(0x720)), DEFINE_RES_IRQ(evt2irq(0x760)), DEFINE_RES_IRQ(evt2irq(0x740)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, };
/* Dummy supplies, where voltage doesn't matter */ static struct regulator_consumer_supply dummy_supplies[] = { REGULATOR_SUPPLY("vddvario", "smsc911x"), REGULATOR_SUPPLY("vdd33a", "smsc911x"), }; static struct smsc911x_platform_config smsc911x_data __initdata = { .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, .flags = SMSC911X_USE_32BIT, .phy_interface = PHY_INTERFACE_MODE_MII, }; static struct resource smsc911x_resources[] __initdata = { DEFINE_RES_MEM(0x18300000, 0x1000), DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ }; #if IS_ENABLED(CONFIG_USB_RENESAS_USBHS_UDC) /* * When USB1 is Func */ static int usbhsf_get_id(struct platform_device *pdev) { return USBHS_GADGET; } #define SUSPMODE 0x102 static int usbhsf_power_ctrl(struct platform_device *pdev, void __iomem *base, int enable) {
#define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ .sense_bitfield_width = 2, }; static struct resource irqpin0_resources[] = { DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ }; static struct platform_device irqpin0_device = { .name = "renesas_intc_irqpin", .id = 0, .resource = irqpin0_resources, .num_resources = ARRAY_SIZE(irqpin0_resources), .dev = { .platform_data = &irqpin0_platform_data, }, };
static struct resource ep93xx_rtc_resource[] = { DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), }; static struct platform_device ep93xx_rtc_device = { .name = "ep93xx-rtc", .id = -1, .num_resources = ARRAY_SIZE(ep93xx_rtc_resource), .resource = ep93xx_rtc_resource, }; static struct resource ep93xx_ohci_resources[] = { DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), DEFINE_RES_IRQ(IRQ_EP93XX_USB), }; static struct platform_device ep93xx_ohci_device = { .name = "ep93xx-ohci", .id = -1, .dev = { .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, .num_resources = ARRAY_SIZE(ep93xx_ohci_resources), .resource = ep93xx_ohci_resources, };
} static struct emac_platform_data am35xx_emac_pdata = { .ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET, .ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE, .hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR, .version = EMAC_VERSION_2, .interrupt_enable = am35xx_enable_emac_int, .interrupt_disable = am35xx_disable_emac_int, }; static struct resource am35xx_emac_resources[] = { DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000), DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ), DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ), DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ), DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ), }; static struct platform_device am35xx_emac_device = { .name = "davinci_emac", .id = -1, .num_resources = ARRAY_SIZE(am35xx_emac_resources), .resource = am35xx_emac_resources, .dev = { .platform_data = &am35xx_emac_pdata, }, };
#include <linux/serial.h> #include <linux/sh_timer.h> #include <linux/sh_intc.h> #include <linux/io.h> #include <linux/serial_sci.h> #include <linux/usb/ohci_pdriver.h> static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_REIE, .type = PORT_SCIF, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xffe00000, 0x100), DEFINE_RES_IRQ(evt2irq(0x700)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_REIE, .type = PORT_SCIF,
static struct regulator_consumer_supply vcc_sdhi1_consumers[] = { REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"), }; /* MMCIF */ static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, .slave_id_tx = SHDMA_SLAVE_MMCIF0_TX, .slave_id_rx = SHDMA_SLAVE_MMCIF0_RX, .ccs_unsupported = true, }; static const struct resource mmcif0_resources[] __initconst = { DEFINE_RES_MEM(0xee200000, 0x100), DEFINE_RES_IRQ(gic_spi(169)), }; /* SDHI0 */ static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = { .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, }; static const struct resource sdhi0_resources[] __initconst = { DEFINE_RES_MEM(0xee100000, 0x100), DEFINE_RES_IRQ(gic_spi(165)), }; /* SDHI1 */ static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
[2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI), }; struct platform_device s5p_device_onenand = { .name = "s5pc110-onenand", .id = -1, .num_resources = ARRAY_SIZE(s5p_onenand_resources), .resource = s5p_onenand_resources, }; #endif /* CONFIG_S5P_DEV_ONENAND */ /* PMU */ #ifdef CONFIG_PLAT_S5P static struct resource s5p_pmu_resource[] = { DEFINE_RES_IRQ(IRQ_PMU) }; static struct platform_device s5p_device_pmu = { .name = "arm-pmu", .id = ARM_PMU_DEVICE_CPU, .num_resources = ARRAY_SIZE(s5p_pmu_resource), .resource = s5p_pmu_resource, }; static int __init s5p_pmu_init(void) { platform_device_register(&s5p_device_pmu); return 0; } arch_initcall(s5p_pmu_init);
}; static struct platform_device mx21ads_nor_mtd_device = { .name = "physmap-flash", .id = 0, .dev = { .platform_data = &mx21ads_flash_data, }, .num_resources = 1, .resource = &mx21ads_flash_resource, }; static struct resource mx21ads_cs8900_resources[] __initdata = { DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), /* irq number is run-time assigned */ DEFINE_RES_IRQ(-1), }; static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = { .name = "cs89x0", .id = 0, .res = mx21ads_cs8900_resources, .num_res = ARRAY_SIZE(mx21ads_cs8900_resources), }; static const struct imxuart_platform_data uart_pdata_rts __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static const struct imxuart_platform_data uart_pdata_norts __initconst = { };
{ 0xfffe0808, 0, 16, /* PINTER */ { 0, 0, 0, 0, 0, 0, 0, 0, PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, }; static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, mask_registers, prio_registers, NULL); static struct plat_sci_port scif0_platform_data = { .scscr = SCSCR_REIE, .type = PORT_SCIF, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xfffe8000, 0x100), DEFINE_RES_IRQ(240), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { .scscr = SCSCR_REIE, .type = PORT_SCIF,
{ unsigned int v; v = __raw_readl(EP93XX_SYSCON_SYSCFG); v &= EP93XX_SYSCON_SYSCFG_REV_MASK; v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; return v; } EXPORT_SYMBOL_GPL(ep93xx_chip_revision); /************************************************************************* * EP93xx GPIO *************************************************************************/ static struct resource ep93xx_gpio_resource[] = { DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), }; static struct platform_device ep93xx_gpio_device = { .name = "gpio-ep93xx", .id = -1, .num_resources = ARRAY_SIZE(ep93xx_gpio_resource), .resource = ep93xx_gpio_resource,
{ platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, ARRAY_SIZE(pfc_resources)); } static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ }; static struct resource irqpin0_resources[] = { DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */ DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */ }; static struct platform_device irqpin0_device = { .name = "renesas_intc_irqpin", .id = 0, .resource = irqpin0_resources, .num_resources = ARRAY_SIZE(irqpin0_resources), .dev = {
.num_resources = ARRAY_SIZE(rtc_resources), .resource = rtc_resources, }; static struct plat_sci_port scif0_platform_data = { .port_reg = 0xa4000136, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_TE | SCSCR_RE, .type = PORT_SCI, .ops = &sh770x_sci_port_ops, .regshift = 1, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xfffffe80, 0x10), DEFINE_RES_IRQ(evt2irq(0x4e0)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) static struct plat_sci_port scif1_platform_data = {
*--------------------------------------------------------------- * EHCI *--------------------------------------------------------------- */ #define SW_EHCI_NAME "sw-ehci" static const char ehci_name[] = SW_EHCI_NAME; static struct sw_hci_hcd sw_ehci1; static struct sw_hci_hcd sw_ehci2; static u64 sw_ehci_dmamask = DMA_BIT_MASK(32); static struct resource sw_ehci1_resources[] = { DEFINE_RES_MEM(SW_PA_USB1_IO_BASE + SW_USB_EHCI_BASE_OFFSET, SW_USB_EHCI_LEN), DEFINE_RES_IRQ(SW_INT_IRQNO_USB1) }; static struct resource sw_ehci2_resources[] = { DEFINE_RES_MEM(SW_PA_USB2_IO_BASE + SW_USB_EHCI_BASE_OFFSET, SW_USB_EHCI_LEN), DEFINE_RES_IRQ(SW_INT_IRQNO_USB2) }; static struct platform_device sw_usb_ehci_device[] = { [0] = { .name = ehci_name, .id = 1, .dev = { .dma_mask = &sw_ehci_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &sw_ehci1,
}; /* Fixed 3.3V regulator to be used by MMCIF */ static struct regulator_consumer_supply fixed3v3_power_consumers[] = { REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"), }; /* MMCIF */ static struct sh_mmcif_plat_data mmcif1_pdata __initdata = { .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, }; static struct resource mmcif1_resources[] __initdata = { DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), DEFINE_RES_IRQ(gic_spi(170)), }; /* Ether */ static struct sh_eth_plat_data ether_pdata __initdata = { .phy = 0x1, .edmac_endian = EDMAC_LITTLE_ENDIAN, .phy_interface = PHY_INTERFACE_MODE_RMII, .ether_link_active_low = 1, }; static struct resource ether_resources[] __initdata = { DEFINE_RES_MEM(0xee700000, 0x400), DEFINE_RES_IRQ(gic_spi(162)), };
SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); static struct sh_timer_config cmt1_platform_data = { .channels_mask = 0x3f, }; static struct resource cmt1_resources[] = { DEFINE_RES_MEM(0xe6138000, 0x200), DEFINE_RES_IRQ(gic_spi(65)), }; static struct platform_device cmt1_device = { .name = "sh-cmt-48", .id = 1, .dev = { .platform_data = &cmt1_platform_data, }, .resource = cmt1_resources, .num_resources = ARRAY_SIZE(cmt1_resources), }; /* TMU */ static struct sh_timer_config tmu0_platform_data = { .channels_mask = 7,
R8A7790_GPIO(2); R8A7790_GPIO(3); R8A7790_GPIO(4); R8A7790_GPIO(5); #define r8a7790_register_gpio(idx) \ platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ r8a7790_gpio##idx##_resources, \ ARRAY_SIZE(r8a7790_gpio##idx##_resources), \ &r8a7790_gpio##idx##_platform_data, \ sizeof(r8a7790_gpio##idx##_platform_data)) static struct resource i2c_resources[] __initdata = { /* I2C0 */ DEFINE_RES_MEM(0xE6508000, 0x40), DEFINE_RES_IRQ(gic_spi(287)), /* I2C1 */ DEFINE_RES_MEM(0xE6518000, 0x40), DEFINE_RES_IRQ(gic_spi(288)), /* I2C2 */ DEFINE_RES_MEM(0xE6530000, 0x40), DEFINE_RES_IRQ(gic_spi(286)), /* I2C3 */ DEFINE_RES_MEM(0xE6540000, 0x40), DEFINE_RES_IRQ(gic_spi(290)), }; #define r8a7790_register_i2c(idx) \ platform_device_register_simple( \ "i2c-rcar", idx, \
}; void sa11x0_register_mtd(struct flash_platform_data *flash, struct resource *res, int nr) { flash->name = "sa1100"; sa11x0mtd_device.resource = res; sa11x0mtd_device.num_resources = nr; sa11x0_register_device(&sa11x0mtd_device, flash); } static struct resource sa11x0ir_resources[] = { DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24), DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c), DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04), DEFINE_RES_IRQ(IRQ_Ser2ICP), }; static struct platform_device sa11x0ir_device = { .name = "sa11x0-ir", .id = -1, .num_resources = ARRAY_SIZE(sa11x0ir_resources), .resource = sa11x0ir_resources, }; void sa11x0_register_irda(struct irda_platform_data *irda) { sa11x0_register_device(&sa11x0ir_device, irda); } static struct resource sa1100_rtc_resources[] = {
.flags = 0, }, }, }, }; static const struct rcar_du_platform_data lager_du_pdata __initconst = { .encoders = lager_du_encoders, .num_encoders = ARRAY_SIZE(lager_du_encoders), }; static const struct resource du_resources[] __initconst = { DEFINE_RES_MEM(0xfeb00000, 0x70000), DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"), DEFINE_RES_IRQ(gic_spi(256)), DEFINE_RES_IRQ(gic_spi(268)), DEFINE_RES_IRQ(gic_spi(269)), }; static void __init lager_add_du_device(void) { struct platform_device_info info = { .name = "rcar-du-r8a7790", .id = -1, .res = du_resources, .num_res = ARRAY_SIZE(du_resources), .data = &lager_du_pdata, .size_data = sizeof(lager_du_pdata), .dma_mask = DMA_BIT_MASK(32), };
/* SYSCON3 */ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64), }; static void __init clps711x_add_syscon(void) { unsigned i; for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++) platform_device_register_simple("syscon", i + 1, &clps711x_syscon_res[i], 1); } static const struct resource clps711x_uart1_res[] __initconst = { DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR1, SZ_128), DEFINE_RES_IRQ(IRQ_UTXINT1), DEFINE_RES_IRQ(IRQ_URXINT1), }; static const struct resource clps711x_uart2_res[] __initconst = { DEFINE_RES_MEM(CLPS711X_PHYS_BASE + UARTDR2, SZ_128), DEFINE_RES_IRQ(IRQ_UTXINT2), DEFINE_RES_IRQ(IRQ_URXINT2), }; static void __init clps711x_add_uart(void) { platform_device_register_simple("clps711x-uart", 0, clps711x_uart1_res, ARRAY_SIZE(clps711x_uart1_res)); platform_device_register_simple("clps711x-uart", 1, clps711x_uart2_res, ARRAY_SIZE(clps711x_uart2_res));
R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ #define r8a73a4_register_scif(index) \ platform_device_register_resndata(NULL, "sh-sci", index, \ scif##index##_resources, \ ARRAY_SIZE(scif##index##_resources), \ &scif##index##_platform_data, \ sizeof(scif##index##_platform_data)) static const struct renesas_irqc_config irqc0_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ }; static const struct resource irqc0_resources[] = { DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
#include "common.h" #define VIDEORAM_SIZE SZ_128K #define EDB7211_LCD_DC_DC_EN CLPS711X_GPIO(3, 1) #define EDB7211_LCDEN CLPS711X_GPIO(3, 2) #define EDB7211_LCDBL CLPS711X_GPIO(3, 3) #define EDB7211_FLASH0_BASE (CS0_PHYS_BASE) #define EDB7211_FLASH1_BASE (CS1_PHYS_BASE) #define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define EDB7211_CS8900_IRQ (IRQ_EINT3) static struct resource edb7211_cs8900_resource[] __initdata = { DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(EDB7211_CS8900_IRQ), }; static struct mtd_partition edb7211_flash_partitions[] __initdata = { { .name = "Flash", .offset = 0, .size = MTDPART_SIZ_FULL, }, }; static struct physmap_flash_data edb7211_flash_pdata __initdata = { .width = 4, .parts = edb7211_flash_partitions, .nr_parts = ARRAY_SIZE(edb7211_flash_partitions), };
DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), }; static const struct resource axp22x_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_RIS_EDGE, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_PEK_FAL_EDGE, "PEK_DBF"), }; static const struct resource axp288_power_button_resources[] = { DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKP, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP288_IRQ_POKN, "PEK_DBF"), }; static const struct resource axp288_fuel_gauge_resources[] = { DEFINE_RES_IRQ(AXP288_IRQ_QWBTU), DEFINE_RES_IRQ(AXP288_IRQ_WBTU), DEFINE_RES_IRQ(AXP288_IRQ_QWBTO), DEFINE_RES_IRQ(AXP288_IRQ_WBTO), DEFINE_RES_IRQ(AXP288_IRQ_WL2), DEFINE_RES_IRQ(AXP288_IRQ_WL1), }; static const struct resource axp803_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"), }; static const struct resource axp809_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_RIS_EDGE, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP809_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
#include <linux/sh_timer.h> #include <mach/common.h> #include <mach/irqs.h> #include <mach/r7s72100.h> #include <asm/mach/arch.h> static struct sh_timer_config mtu2_0_platform_data __initdata = { .name = "MTU2_0", .timer_bit = 0, .channel_offset = -0x80, .clockevent_rating = 200, }; static struct resource mtu2_0_resources[] __initdata = { DEFINE_RES_MEM(0xfcff0300, 0x27), DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */ }; #define r7s72100_register_mtu2(idx) \ platform_device_register_resndata(&platform_bus, "sh_mtu2", \ idx, mtu2_##idx##_resources, \ ARRAY_SIZE(mtu2_##idx##_resources), \ &mtu2_##idx##_platform_data, \ sizeof(struct sh_timer_config)) void __init r7s72100_add_dt_devices(void) { r7s72100_register_mtu2(0); } #ifdef CONFIG_USE_OF
#include <linux/serial_sci.h> #include <linux/sh_dma.h> #include <linux/sh_timer.h> #include <linux/sh_intc.h> #include <cpu/dma-register.h> static struct plat_sci_port scif0_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, .type = PORT_SCIF, .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xffe00000, 0x100), DEFINE_RES_IRQ(evt2irq(0x700)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
#define r8a7778_register_scif(index) \ platform_device_register_resndata(&platform_bus, "sh-sci", index, \ scif##index##_resources, \ ARRAY_SIZE(scif##index##_resources), \ &scif##index##_platform_data, \ sizeof(scif##index##_platform_data)) /* TMU */ static struct sh_timer_config sh_tmu0_platform_data = { .channels_mask = 7, }; static struct resource sh_tmu0_resources[] = { DEFINE_RES_MEM(0xffd80000, 0x30), DEFINE_RES_IRQ(gic_iid(0x40)), DEFINE_RES_IRQ(gic_iid(0x41)), DEFINE_RES_IRQ(gic_iid(0x42)), }; #define r8a7778_register_tmu(idx) \ platform_device_register_resndata( \ &platform_bus, "sh-tmu", idx, \ sh_tmu##idx##_resources, \ ARRAY_SIZE(sh_tmu##idx##_resources), \ &sh_tmu##idx##_platform_data, \ sizeof(sh_tmu##idx##_platform_data)) int r8a7778_usb_phy_power(bool enable) { static struct usb_phy *phy = NULL;
#define INT2NTSR0 IOMEM(0xfe700060) #define INT2NTSR1 IOMEM(0xfe700064) static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ .sense_bitfield_width = 2, }; static struct resource irqpin0_resources[] __initdata = { DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ }; void __init r8a7779_init_irq_extpin_dt(int irlm) { void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); u32 tmp; if (!icr0) { pr_warn("r8a7779: unable to setup external irq pin mode\n"); return; }
.vsync_end = 777, .vtotal = 806, .flags = 0, }, }, }, }; static const struct rcar_du_platform_data du_pdata __initconst = { .encoders = du_encoders, .num_encoders = ARRAY_SIZE(du_encoders), }; static const struct resource du_resources[] __initconst = { DEFINE_RES_MEM(0xfff80000, 0x40000), DEFINE_RES_IRQ(gic_iid(0x3f)), }; static void __init marzen_add_du_device(void) { struct platform_device_info info = { .name = "rcar-du-r8a7779", .id = -1, .res = du_resources, .num_res = ARRAY_SIZE(du_resources), .data = &du_pdata, .size_data = sizeof(du_pdata), .dma_mask = DMA_BIT_MASK(32), }; platform_device_register_full(&info);