gpio_res[1].flags = IORESOURCE_MEM; for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) { gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0]; gpio_res[0].end = gpio_res[0].start; gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1]; gpio_res[1].end = gpio_res[1].start; platform_device_register_simple("clps711x-gpio", i, gpio_res, ARRAY_SIZE(gpio_res)); } } const struct resource clps711x_syscon_res[] __initconst = { /* SYSCON1, SYSFLG1 */ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128), /* SYSCON2, SYSFLG2 */ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128), /* SYSCON3 */ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64), }; static void __init clps711x_add_syscon(void) { unsigned i; for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++) platform_device_register_simple("clps711x-syscon", i + 1, &clps711x_syscon_res[i], 1); }
.dev = { .platform_data = &dma_platform_data, }, }; /* Serial */ static struct plat_sci_port scif0_platform_data = { .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .type = PORT_SCIF, .ops = &sh7722_sci_port_ops, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xffe00000, 0x100), DEFINE_RES_IRQ(evt2irq(0xc00)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { .flags = UPF_BOOT_AUTOCONF,
R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); #define r8a7778_register_scif(index) \ platform_device_register_resndata(NULL, "sh-sci", index, \ scif##index##_resources, \ ARRAY_SIZE(scif##index##_resources), \ &scif##index##_platform_data, \ sizeof(scif##index##_platform_data)) /* TMU */ static struct sh_timer_config sh_tmu0_platform_data = { .channels_mask = 7, }; static struct resource sh_tmu0_resources[] = { DEFINE_RES_MEM(0xffd80000, 0x30), DEFINE_RES_IRQ(gic_iid(0x40)), DEFINE_RES_IRQ(gic_iid(0x41)), DEFINE_RES_IRQ(gic_iid(0x42)), }; #define r8a7778_register_tmu(idx) \ platform_device_register_resndata( \ NULL, "sh-tmu", idx, \ sh_tmu##idx##_resources, \ ARRAY_SIZE(sh_tmu##idx##_resources), \ &sh_tmu##idx##_platform_data, \ sizeof(sh_tmu##idx##_platform_data)) int r8a7778_usb_phy_power(bool enable) {
int i915_gem_init_stolen(struct drm_i915_private *dev_priv) { resource_size_t reserved_base, stolen_top; resource_size_t reserved_total, reserved_size; mutex_init(&dev_priv->mm.stolen_lock); if (intel_vgpu_active(dev_priv)) { DRM_INFO("iGVT-g active, disabling use of stolen memory\n"); return 0; } if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) { DRM_INFO("DMAR active, disabling use of stolen memory\n"); return 0; } if (resource_size(&intel_graphics_stolen_res) == 0) return 0; dev_priv->dsm = intel_graphics_stolen_res; if (i915_adjust_stolen(dev_priv, &dev_priv->dsm)) return 0; GEM_BUG_ON(dev_priv->dsm.start == 0); GEM_BUG_ON(dev_priv->dsm.end <= dev_priv->dsm.start); stolen_top = dev_priv->dsm.end + 1; reserved_base = stolen_top; reserved_size = 0; switch (INTEL_GEN(dev_priv)) { case 2: case 3: break; case 4: if (!IS_G4X(dev_priv)) break; /* fall through */ case 5: g4x_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); break; case 6: gen6_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); break; case 7: if (IS_VALLEYVIEW(dev_priv)) vlv_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); else gen7_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); break; case 8: case 9: case 10: if (IS_LP(dev_priv)) chv_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); else bdw_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); break; case 11: default: icl_get_stolen_reserved(dev_priv, &reserved_base, &reserved_size); break; } /* * Our expectation is that the reserved space is at the top of the * stolen region and *never* at the bottom. If we see !reserved_base, * it likely means we failed to read the registers correctly. */ if (!reserved_base) { DRM_ERROR("inconsistent reservation %pa + %pa; ignoring\n", &reserved_base, &reserved_size); reserved_base = stolen_top; reserved_size = 0; } dev_priv->dsm_reserved = (struct resource) DEFINE_RES_MEM(reserved_base, reserved_size); if (!resource_contains(&dev_priv->dsm, &dev_priv->dsm_reserved)) { DRM_ERROR("Stolen reserved area %pR outside stolen memory %pR\n", &dev_priv->dsm_reserved, &dev_priv->dsm); return 0; } /* It is possible for the reserved area to end before the end of stolen * memory, so just consider the start. */ reserved_total = stolen_top - reserved_base; DRM_DEBUG_DRIVER("Memory reserved for graphics device: %lluK, usable: %lluK\n", (u64)resource_size(&dev_priv->dsm) >> 10, ((u64)resource_size(&dev_priv->dsm) - reserved_total) >> 10); dev_priv->stolen_usable_size = resource_size(&dev_priv->dsm) - reserved_total; /* Basic memrange allocator for stolen space. */ drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->stolen_usable_size); return 0; }
.dev = { .platform_data = &dma_platform_data, }, }; /* Serial */ static struct plat_sci_port scif0_platform_data = { .port_reg = SCIx_NOT_SUPPORTED, .flags = UPF_BOOT_AUTOCONF, .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, .type = PORT_SCIF, .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, }; static struct resource scif0_resources[] = { DEFINE_RES_MEM(0xffe00000, 0x100), DEFINE_RES_IRQ(evt2irq(0xc00)), }; static struct platform_device scif0_device = { .name = "sh-sci", .id = 0, .resource = scif0_resources, .num_resources = ARRAY_SIZE(scif0_resources), .dev = { .platform_data = &scif0_platform_data, }, }; static struct plat_sci_port scif1_platform_data = { .port_reg = SCIx_NOT_SUPPORTED,
SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00)); SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20)); SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40)); SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60)); SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20)); SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40)); SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60)); /* CMT */ static struct sh_timer_config cmt2_platform_data = { .channels_mask = 0x20, }; static struct resource cmt2_resources[] = { DEFINE_RES_MEM(0xe6130000, 0x50), DEFINE_RES_IRQ(evt2irq(0x0b80)), }; static struct platform_device cmt2_device = { .name = "sh-cmt-32-fast", .id = 2, .dev = { .platform_data = &cmt2_platform_data, }, .resource = cmt2_resources, .num_resources = ARRAY_SIZE(cmt2_resources), }; /* TMU */ static struct sh_timer_config tmu0_platform_data = {
}, { .name = "jffs", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_APPEND, } }; #endif static struct flash_platform_data assabet_flash_data = { .map_name = "cfi_probe", .parts = assabet_partitions, .nr_parts = ARRAY_SIZE(assabet_partitions), }; static struct resource assabet_flash_resources[] = { DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), }; /* * Assabet IrDA support code. */ static int assabet_irda_set_power(struct device *dev, unsigned int state) { static unsigned int bcr_state[4] = { ASSABET_BCR_IRDA_MD0, ASSABET_BCR_IRDA_MD1|ASSABET_BCR_IRDA_MD0, ASSABET_BCR_IRDA_MD1, 0
.shp_2_mcu_addr = 891, .mcu_2_shp_addr = 960, .uartsh_2_mcu_addr = 1032, .spdif_2_mcu_addr = 1100, .mcu_2_spdif_addr = 1134, .firi_2_mcu_addr = 1193, .mcu_2_firi_addr = 1290, }; static struct sdma_platform_data imx53_sdma_pdata __initdata = { .fw_name = "sdma-imx53.bin", .script_addrs = &imx53_sdma_script, }; static const struct resource imx50_audmux_res[] __initconst = { DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K), }; static const struct resource imx51_audmux_res[] __initconst = { DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), }; static const struct resource imx53_audmux_res[] __initconst = { DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K), }; void __init imx50_soc_init(void) { /* i.mx50 has the i.mx31 type gpio */ mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
.end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, .flags = IORESOURCE_MEM, }; static struct platform_device mx21ads_nor_mtd_device = { .name = "physmap-flash", .id = 0, .dev = { .platform_data = &mx21ads_flash_data, }, .num_resources = 1, .resource = &mx21ads_flash_resource, }; static const struct resource mx21ads_cs8900_resources[] __initconst = { DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ), }; static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = { .name = "cs89x0", .id = 0, .res = mx21ads_cs8900_resources, .num_res = ARRAY_SIZE(mx21ads_cs8900_resources), }; static const struct imxuart_platform_data uart_pdata_rts __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static const struct imxuart_platform_data uart_pdata_norts __initconst = {
mapbase, SZ_512 - 1, NO_IRQ); platform_device_register(&orion_spi); } void __init orion_spi_1_init(unsigned long mapbase) { fill_resources(&orion_spi_1, &orion_spi_1_resources, mapbase, SZ_512 - 1, NO_IRQ); platform_device_register(&orion_spi_1); } /***************************************************************************** * Watchdog ****************************************************************************/ static struct resource orion_wdt_resource[] = { DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), }; static struct platform_device orion_wdt_device = { .name = "orion_wdt", .id = -1, .num_resources = ARRAY_SIZE(orion_wdt_resource), .resource = orion_wdt_resource, }; void __init orion_wdt_init(void) { platform_device_register(&orion_wdt_device); }
.vactive = 768, .vfront_porch = 3, .vback_porch = 29, .vsync_len = 6, }, }, }, }; static struct rcar_du_platform_data koelsch_du_pdata = { .encoders = koelsch_du_encoders, .num_encoders = ARRAY_SIZE(koelsch_du_encoders), }; static const struct resource du_resources[] __initconst = { DEFINE_RES_MEM(0xfeb00000, 0x40000), DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), DEFINE_RES_IRQ(gic_spi(256)), DEFINE_RES_IRQ(gic_spi(268)), }; static void __init koelsch_add_du_device(void) { struct platform_device_info info = { .name = "rcar-du-r8a7791", .id = -1, .res = du_resources, .num_res = ARRAY_SIZE(du_resources), .data = &koelsch_du_pdata, .size_data = sizeof(koelsch_du_pdata), .dma_mask = DMA_BIT_MASK(32),
.pfn = __phys_to_pfn(0xf0100000), .length = PAGE_SIZE, .type = MT_DEVICE_NONSHARED }, #endif }; void __init r8a7740_map_io(void) { debug_ll_io_init(); iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc)); } /* PFC */ static const struct resource pfc_resources[] = { DEFINE_RES_MEM(0xe6050000, 0x8000), DEFINE_RES_MEM(0xe605800c, 0x0020), }; void __init r8a7740_pinmux_init(void) { platform_device_register_simple("pfc-r8a7740", -1, pfc_resources, ARRAY_SIZE(pfc_resources)); } static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ }; static struct resource irqpin0_resources[] = { DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
#include "common.h" #define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define AUTCPU12_CS8900_IRQ (IRQ_EINT3) #define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000) #define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10) #define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO) #define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */ #define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2) #define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3) #define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3) static struct resource autcpu12_cs8900_resource[] __initdata = { DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ), }; static struct resource autcpu12_nvram_resource[] __initdata = { DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"), }; static struct platform_device autcpu12_nvram_pdev __initdata = { .name = "autcpu12_nvram", .id = -1, .resource = autcpu12_nvram_resource, .num_resources = ARRAY_SIZE(autcpu12_nvram_resource), }; static struct resource autcpu12_nand_resource[] __initdata = {
.vsync_start = 771, .vsync_end = 777, .vtotal = 806, .flags = 0, }, }, }, }; static const struct rcar_du_platform_data du_pdata __initconst = { .encoders = du_encoders, .num_encoders = ARRAY_SIZE(du_encoders), }; static const struct resource du_resources[] __initconst = { DEFINE_RES_MEM(0xfff80000, 0x40000), DEFINE_RES_IRQ(gic_iid(0x3f)), }; static void __init marzen_add_du_device(void) { struct platform_device_info info = { .name = "rcar-du-r8a7779", .id = -1, .res = du_resources, .num_res = ARRAY_SIZE(du_resources), .data = &du_pdata, .size_data = sizeof(du_pdata), .dma_mask = DMA_BIT_MASK(32), };
.mcu_2_shp_addr = 1048, .ata_2_mcu_addr = 1560, .mcu_2_ata_addr = 1479, .app_2_per_addr = 1189, .app_2_mcu_addr = 770, .shp_2_per_addr = 1407, .shp_2_mcu_addr = 979, }; static struct sdma_platform_data imx25_sdma_pdata __initdata = { .fw_name = "sdma-imx25.bin", .script_addrs = &imx25_sdma_script, }; static const struct resource imx25_audmux_res[] __initconst = { DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K), }; void __init imx25_soc_init(void) { /* i.mx25 has the i.mx35 type gpio */ mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0); mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); pinctrl_provide_dummies(); /* i.mx25 has the i.mx35 type sdma */ imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); /* i.mx25 has the i.mx31 type audmux */ platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
void __init rcar_gen2_pm_init(void) { void __iomem *p; u32 bar; static int once; struct device_node *np, *cpus; bool has_a7 = false; bool has_a15 = false; struct resource res; int error; if (once++) return; cpus = of_find_node_by_path("/cpus"); if (!cpus) return; for_each_child_of_node(cpus, np) { if (of_device_is_compatible(np, "arm,cortex-a15")) has_a15 = true; else if (of_device_is_compatible(np, "arm,cortex-a7")) has_a7 = true; } np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram"); if (!np) { /* No smp-sram in DT, fall back to hardcoded address */ res = (struct resource)DEFINE_RES_MEM(ICRAM1, shmobile_boot_size); goto map; } error = of_address_to_resource(np, 0, &res); if (error) { pr_err("Failed to get smp-sram address: %d\n", error); return; } map: /* RAM for jump stub, because BAR requires 256KB aligned address */ if (res.start & (256 * 1024 - 1) || resource_size(&res) < shmobile_boot_size) { pr_err("Invalid smp-sram region\n"); return; } p = ioremap(res.start, resource_size(&res)); if (!p) return; /* * install the reset vector, use the largest version if we have enough * memory available */ if (resource_size(&res) >= shmobile_boot_size_gen2) { shmobile_boot_cpu_gen2 = read_cpuid_mpidr(); memcpy_toio(p, shmobile_boot_vector_gen2, shmobile_boot_size_gen2); } else { memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); } iounmap(p); /* setup reset vectors */ p = ioremap_nocache(RST, 0x63); bar = phys_to_sbar(res.start); if (has_a15) { writel_relaxed(bar, p + CA15BAR); writel_relaxed(bar | SBAR_BAREN, p + CA15BAR); /* de-assert reset for CA15 CPUs */ writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~CA15RESCNT_CPUS) | CA15RESCNT_CODE, p + CA15RESCNT); } if (has_a7) { writel_relaxed(bar, p + CA7BAR); writel_relaxed(bar | SBAR_BAREN, p + CA7BAR); /* de-assert reset for CA7 CPUs */ writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~CA7RESCNT_CPUS) | CA7RESCNT_CODE, p + CA7RESCNT); } iounmap(p); shmobile_smp_apmu_suspend_init(); }
#define EDB7211_FLASH1_BASE (CS1_PHYS_BASE) #define EDB7211_CS8900_BASE (CS2_PHYS_BASE + 0x300) #define EDB7211_CS8900_IRQ (IRQ_EINT3) /* The extra 8 lines of the keyboard matrix */ #define EDB7211_EXTKBD_BASE (CS3_PHYS_BASE) static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = { .sda_pin = EDB7211_I2C_SDA, .scl_pin = EDB7211_I2C_SCL, .scl_is_output_only = 1, }; static struct resource edb7211_cs8900_resource[] __initdata = { DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K), DEFINE_RES_IRQ(EDB7211_CS8900_IRQ), }; static struct mtd_partition edb7211_flash_partitions[] __initdata = { { .name = "Flash", .offset = 0, .size = MTDPART_SIZ_FULL, }, }; static struct physmap_flash_data edb7211_flash_pdata __initdata = { .width = 4, .parts = edb7211_flash_partitions, .nr_parts = ARRAY_SIZE(edb7211_flash_partitions),
void __init imx27_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX27); mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), MX27_NUM_GPIO_PORT); } void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); } static const struct resource imx27_audmux_res[] __initconst = { DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K), }; void __init imx27_soc_init(void) { /* i.mx27 has the i.mx21 type gpio */ mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); imx_add_imx_dma(); /* imx27 has the imx21 type audmux */ platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
mapbase, SZ_512 - 1, NO_IRQ); platform_device_register(&orion_spi); } void __init orion_spi_1_init(unsigned long mapbase) { fill_resources(&orion_spi_1, &orion_spi_1_resources, mapbase, SZ_512 - 1, NO_IRQ); platform_device_register(&orion_spi_1); } /***************************************************************************** * Watchdog ****************************************************************************/ static struct resource orion_wdt_resource = DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x28); static struct platform_device orion_wdt_device = { .name = "orion_wdt", .id = -1, .num_resources = 1, .resource = &orion_wdt_resource, }; void __init orion_wdt_init(void) { platform_device_register(&orion_wdt_device); } /***************************************************************************** * XOR
.name = "ep93xx-fb", .id = -1, .dev = { .platform_data = &ep93xxfb_data, .coherent_dma_mask = DMA_BIT_MASK(32), .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask, }, .num_resources = ARRAY_SIZE(ep93xx_fb_resource), .resource = ep93xx_fb_resource, }; /* The backlight use a single register in the framebuffer's register space */ #define EP93XX_RASTER_REG_BRIGHTNESS 0x20 static struct resource ep93xx_bl_resources[] = { DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE + EP93XX_RASTER_REG_BRIGHTNESS, 0x04), }; static struct platform_device ep93xx_bl_device = { .name = "ep93xx-bl", .id = -1, .num_resources = ARRAY_SIZE(ep93xx_bl_resources), .resource = ep93xx_bl_resources, }; /** * ep93xx_register_fb - Register the framebuffer platform device. * @data: platform specific framebuffer configuration (__initdata) */ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) {
iotable_init(rpc_io_desc, ARRAY_SIZE(rpc_io_desc)); /* * Turn off floppy. */ writeb(0xc, PCIO_BASE + (0x3f2 << 2)); /* * RiscPC can't handle half-word loads and stores */ elf_hwcap &= ~HWCAP_HALF; } static struct resource acornfb_resources[] = { /* VIDC */ DEFINE_RES_MEM(0x03400000, 0x00200000), DEFINE_RES_IRQ(IRQ_VSYNCPULSE), }; static struct platform_device acornfb_device = { .name = "acornfb", .id = -1, .dev = { .coherent_dma_mask = 0xffffffff, }, .num_resources = ARRAY_SIZE(acornfb_resources), .resource = acornfb_resources, }; static struct resource iomd_resources[] = { DEFINE_RES_MEM(0x03200000, 0x10000),
#include <asm/mach/arch.h> #include "common.h" #include "irqs.h" #include "r7s72100.h" /* Ether */ static const struct sh_eth_plat_data ether_pdata __initconst = { .phy = 0x00, /* PD60610 */ .edmac_endian = EDMAC_LITTLE_ENDIAN, .phy_interface = PHY_INTERFACE_MODE_MII, .no_ether_link = 1 }; static const struct resource ether_resources[] __initconst = { DEFINE_RES_MEM(0xe8203000, 0x800), DEFINE_RES_MEM(0xe8204800, 0x200), DEFINE_RES_IRQ(gic_iid(359)), }; static const struct platform_device_info ether_info __initconst = { .name = "r7s72100-ether", .id = -1, .res = ether_resources, .num_res = ARRAY_SIZE(ether_resources), .data = ðer_pdata, .size_data = sizeof(ether_pdata), .dma_mask = DMA_BIT_MASK(32), }; /* RSPI */
static int i915_adjust_stolen(struct drm_i915_private *dev_priv, struct resource *dsm) { struct i915_ggtt *ggtt = &dev_priv->ggtt; struct resource *r; if (dsm->start == 0 || dsm->end <= dsm->start) return -EINVAL; /* * TODO: We have yet too encounter the case where the GTT wasn't at the * end of stolen. With that assumption we could simplify this. */ /* Make sure we don't clobber the GTT if it's within stolen memory */ if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) { struct resource stolen[2] = {*dsm, *dsm}; struct resource ggtt_res; resource_size_t ggtt_start; ggtt_start = I915_READ(PGTBL_CTL); if (IS_GEN(dev_priv, 4)) ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) | (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; else ggtt_start &= PGTBL_ADDRESS_LO_MASK; ggtt_res = (struct resource) DEFINE_RES_MEM(ggtt_start, ggtt_total_entries(ggtt) * 4); if (ggtt_res.start >= stolen[0].start && ggtt_res.start < stolen[0].end) stolen[0].end = ggtt_res.start; if (ggtt_res.end > stolen[1].start && ggtt_res.end <= stolen[1].end) stolen[1].start = ggtt_res.end; /* Pick the larger of the two chunks */ if (resource_size(&stolen[0]) > resource_size(&stolen[1])) *dsm = stolen[0]; else *dsm = stolen[1]; if (stolen[0].start != stolen[1].start || stolen[0].end != stolen[1].end) { DRM_DEBUG_DRIVER("GTT within stolen memory at %pR\n", &ggtt_res); DRM_DEBUG_DRIVER("Stolen memory adjusted to %pR\n", dsm); } } /* * Verify that nothing else uses this physical address. Stolen * memory should be reserved by the BIOS and hidden from the * kernel. So if the region is already marked as busy, something * is seriously wrong. */ r = devm_request_mem_region(dev_priv->drm.dev, dsm->start, resource_size(dsm), "Graphics Stolen Memory"); if (r == NULL) { /* * One more attempt but this time requesting region from * start + 1, as we have seen that this resolves the region * conflict with the PCI Bus. * This is a BIOS w/a: Some BIOS wrap stolen in the root * PCI bus, but have an off-by-one error. Hence retry the * reservation starting from 1 instead of 0. * There's also BIOS with off-by-one on the other end. */ r = devm_request_mem_region(dev_priv->drm.dev, dsm->start + 1, resource_size(dsm) - 2, "Graphics Stolen Memory"); /* * GEN3 firmware likes to smash pci bridges into the stolen * range. Apparently this works. */ if (r == NULL && !IS_GEN(dev_priv, 3)) { DRM_ERROR("conflict detected with stolen region: %pR\n", dsm); return -EBUSY; } } return 0; }
void __init orion_spi_1_init(unsigned long mapbase, unsigned long tclk) { orion_spi_1_plat_data.tclk = tclk; fill_resources(&orion_spi_1, &orion_spi_1_resources, mapbase, SZ_512 - 1, NO_IRQ); platform_device_register(&orion_spi_1); } /***************************************************************************** * Watchdog ****************************************************************************/ static struct orion_wdt_platform_data orion_wdt_data; static struct resource orion_wdt_resource = DEFINE_RES_MEM(TIMER_VIRT_BASE, 0x28); static struct platform_device orion_wdt_device = { .name = "orion_wdt", .id = -1, .dev = { .platform_data = &orion_wdt_data, }, .resource = &orion_wdt_resource, .num_resources = 1, }; void __init orion_wdt_init(unsigned long tclk) { orion_wdt_data.tclk = tclk; platform_device_register(&orion_wdt_device);
static struct platform_device ipmmu_device = { .name = "ipmmu", .id = -1, .dev = { .platform_data = &ipmmu_platform_data, }, .resource = ipmmu_resources, .num_resources = ARRAY_SIZE(ipmmu_resources), }; static struct renesas_intc_irqpin_config irqpin0_platform_data = { .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ }; static struct resource irqpin0_resources[] = { DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ }; static struct platform_device irqpin0_device = {
}, { .name = "SIMpad root jffs2", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_APPEND, } }; static struct flash_platform_data simpad_flash_data = { .map_name = "cfi_probe", .parts = simpad_partitions, .nr_parts = ARRAY_SIZE(simpad_partitions), }; static struct resource simpad_flash_resources [] = { DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M), DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M), }; static struct ucb1x00_plat_data simpad_ucb1x00_data = { .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, }; static struct mcp_plat_data simpad_mcp_data = { .mccr0 = MCCR0_ADM, .sclk_rate = 11981000, .codec_pdata = &simpad_ucb1x00_data, };
*/ unsigned int ep93xx_chip_revision(void) { unsigned int v; v = __raw_readl(EP93XX_SYSCON_SYSCFG); v &= EP93XX_SYSCON_SYSCFG_REV_MASK; v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT; return v; } /************************************************************************* * EP93xx GPIO *************************************************************************/ static struct resource ep93xx_gpio_resource[] = { DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), }; static struct platform_device ep93xx_gpio_device = { .name = "gpio-ep93xx", .id = -1, .num_resources = ARRAY_SIZE(ep93xx_gpio_resource), .resource = ep93xx_gpio_resource, }; /************************************************************************* * EP93xx peripheral handling *************************************************************************/ #define EP93XX_UART_MCR_OFFSET (0x0100) static void ep93xx_uart_set_mctrl(struct amba_device *dev,
.num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources), .resource = s3c64xx_onenand1_resources, }; void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) { s3c_set_platdata(pdata, sizeof(struct onenand_platform_data), &s3c64xx_device_onenand1); } #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */ /* PWM Timer */ #ifdef CONFIG_SAMSUNG_DEV_PWM static struct resource samsung_pwm_resource[] = { DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K), }; struct platform_device samsung_device_pwm = { .name = "samsung-pwm", .id = -1, .num_resources = ARRAY_SIZE(samsung_pwm_resource), .resource = samsung_pwm_resource, }; void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { samsung_device_pwm.dev.platform_data = pd; } #endif /* CONFIG_SAMSUNG_DEV_PWM */
#include <plat/regs-serial.h> #include <linux/platform_data/i2c-s3c2410.h> #include <plat/devs.h> #include <plat/cpu.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/map.h> #include <linux/mtd/physmap.h> #include <plat/samsung-time.h> #include "common.h" static struct resource tct_hammer_nor_resource = DEFINE_RES_MEM(0x00000000, SZ_16M); static struct mtd_partition tct_hammer_mtd_partitions[] = { { .name = "System", .size = 0x240000, .offset = 0, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "JFFS2", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_APPEND, } }; static struct physmap_flash_data tct_hammer_flash_data = {
.vsync_start = 771, .vsync_end = 777, .vtotal = 806, .flags = 0, }, }, }, }; static const struct rcar_du_platform_data lager_du_pdata __initconst = { .encoders = lager_du_encoders, .num_encoders = ARRAY_SIZE(lager_du_encoders), }; static const struct resource du_resources[] __initconst = { DEFINE_RES_MEM(0xfeb00000, 0x70000), DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"), DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"), DEFINE_RES_IRQ(gic_spi(256)), DEFINE_RES_IRQ(gic_spi(268)), DEFINE_RES_IRQ(gic_spi(269)), }; static void __init lager_add_du_device(void) { struct platform_device_info info = { .name = "rcar-du-r8a7790", .id = -1, .res = du_resources, .num_res = ARRAY_SIZE(du_resources), .data = &lager_du_pdata,