/****************************************************************************** * @fn HalDMAInit * * @brief DMA Interrupt Service Routine * * @param None * * @return None *****************************************************************************/ HAL_ISR_FUNCTION( halDmaIsr, DMA_VECTOR ) { extern void HalUARTIsrDMA(void); DMAIF = 0; #if HAL_UART_DMA if (HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX)) { HalUARTIsrDMA(); } #endif // HAL_UART_DMA #if (defined HAL_SPI) && (HAL_SPI == TRUE) if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_RX ) ) { HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_RX ); HalSpiRxIsr(); } if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_TX ) ) { HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_TX ); HalSpiTxIsr(); } #endif // (defined HAL_SPI) && (HAL_SPI == TRUE) #if (defined HAL_IRGEN) && (HAL_IRGEN == TRUE) if ( HAL_IRGEN == TRUE && HAL_DMA_CHECK_IRQ( HAL_IRGEN_DMA_CH ) ) { HAL_DMA_CLEAR_IRQ( HAL_IRGEN_DMA_CH ); HalIrGenDmaIsr(); } #endif // (defined HAL_IRGEN) && (HAL_IRGEN == TRUE) }
/****************************************************************************** * @fn HalDMAInit * * @brief DMA Interrupt Service Routine * * @param None * * @return None *****************************************************************************/ HAL_ISR_FUNCTION( halDmaIsr, DMA_VECTOR ) { DMAIF = 0; if (ZNP_CFG1_UART == znpCfg1) { if (HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX)) { extern void HalUARTIsrDMA(void); HalUARTIsrDMA(); } } else { if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_RX ) ) { HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_RX ); HalSpiRxIsr(); } if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_TX ) ) { HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_TX ); HalSpiTxIsr(); } } }
/****************************************************************************** * @fn HalDMAInit * * @brief DMA Interrupt Service Routine * * @param None * * @return None *****************************************************************************/ HAL_ISR_FUNCTION( halDmaIsr, DMA_VECTOR ) { HAL_ENTER_ISR(); DMAIF = 0; if (ZNP_CFG1_UART == znpCfg1) { if (HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX)) { extern void HalUARTIsrDMA(void); HalUARTIsrDMA(); } } #if (defined HAL_SPI) && (HAL_SPI == TRUE) else { if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_RX ) ) { HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_RX ); HalSpiRxIsr(); } if ( HAL_DMA_CHECK_IRQ( HAL_DMA_CH_TX ) ) { HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_TX ); HalSpiTxIsr(); } } #endif // #if (defined HAL_SPI) && (HAL_SPI == TRUE) HAL_EXIT_ISR(); }
/************************************************************************************************** * @fn sblRun * * @brief Serial Boot run code for the SPI transport. * * input parameters * * None. * * output parameters * * None. * * @return None. */ static void sblRun(void) { halUARTCfg_t uartConfig; uartConfig.callBackFunc = sblRxCB; HAL_DMA_SET_ADDR_DESC1234(dmaCh1234); HalUARTInitSPI(); HalUARTOpenSPI(&uartConfig); while (1) { if (PxIFG & SPI_RDYIn_BIT) { spiRdyIn(); } HalUARTPollSPI(); if (HAL_DMA_CHECK_IRQ(HAL_SPI_CH_TX)) { HAL_DMA_CLEAR_IRQ(HAL_SPI_CH_TX); HalUART_DMAIsrSPI(); if (sblReset) { HAL_SYSTEM_RESET(); } } } }
/************************************************************************************************** * @fn npSpiMonitor * * @brief This function monitors the SPI signals for error conditions and for the end of a * transaction. If an error is detected it attempts to recover. * * input parameters * * None. * * output parameters * * None. * * @return None. ************************************************************************************************** */ void npSpiMonitor(void) { switch (halSpiState) { case NP_SPI_SYNCH: break; case NP_SPI_IDLE: NP_SPI_ASSERT((NP_RDYIn_IFG & NP_RDYIn_BIT) == 0); break; case NP_SPI_WAIT_RX: NP_SPI_ASSERT((HAL_DMA_CHECK_IRQ(HAL_DMA_CH_RX)) == 0); break; case NP_SPI_WAIT_TX: NP_SPI_ASSERT((HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX)) == 0); break; case NP_SPI_WAIT_AREQ: break; default: NP_SPI_ASSERT(0); break; } if (halSpiState == NP_SPI_IDLE) { /* Poll for MRDY in case it was set before slave had setup the ISR. * Also, async responses may get queued, so flush them out here. */ if ((NP_RDYIn == 0) || (npSpiReadyCallback())) { npSpiAReqReady(); } } }
/****************************************************************************** * @fn sspAesEncryptHW * * @brief Encrypts 16 byte block using AES encryption engine * * input parameters * * @param AesKey - Pointer to AES Key. * @param Cstate - Pointer to input data. * * output parameters * * @param Cstate - Pointer to encrypted data. * * @return None * */ void sspAesEncryptHW( uint8 *AesKey, uint8 *Cstate ) { (void)AesKey; #if (defined HAL_AES_DMA) && (HAL_AES_DMA == TRUE) /* Setup DMA for AES encryption */ AesDmaSetup( Cstate, STATE_BLENGTH, Cstate, STATE_BLENGTH ); AES_SET_ENCR_DECR_KEY_IV( AES_ENCRYPT ); /* Kick it off, block until DMA is done */ AES_START(); while( !HAL_DMA_CHECK_IRQ( HAL_DMA_AES_OUT ) ); #else /* Set ECB mode for AES encryption */ AES_SETMODE(ECB); AES_SET_ENCR_DECR_KEY_IV( AES_ENCRYPT ); /* Load and start the block */ AesStartBlock( Cstate, Cstate ); #endif }
/****************************************************************************** * @fn HalUARTPollDMA * * @brief Poll a USART module implemented by DMA. * * @param none * * @return none *****************************************************************************/ static void HalUARTPollDMA(void) { uint16 cnt = 0; uint8 evt = 0; if (HAL_UART_DMA_NEW_RX_BYTE(dmaCfg.rxHead)) { rxIdx_t tail = findTail(); // If the DMA has transferred in more Rx bytes, reset the Rx idle timer. if (dmaCfg.rxTail != tail) { dmaCfg.rxTail = tail; // Re-sync the shadow on any 1st byte(s) received. if (dmaCfg.rxTick == 0) { dmaCfg.rxShdw = ST0; } dmaCfg.rxTick = HAL_UART_DMA_IDLE; } else if (dmaCfg.rxTick) { // Use the LSB of the sleep timer (ST0 must be read first anyway). uint8 decr = ST0 - dmaCfg.rxShdw; if (dmaCfg.rxTick > decr) { dmaCfg.rxTick -= decr; dmaCfg.rxShdw = ST0; } else { dmaCfg.rxTick = 0; } } cnt = HalUARTRxAvailDMA(); } else { dmaCfg.rxTick = 0; } if (cnt >= HAL_UART_DMA_FULL) { evt = HAL_UART_RX_FULL; } else if (cnt >= HAL_UART_DMA_HIGH) { evt = HAL_UART_RX_ABOUT_FULL; PxOUT |= HAL_UART_Px_RTS; // Disable Rx flow. } else if (cnt && !dmaCfg.rxTick) { evt = HAL_UART_RX_TIMEOUT; } if (dmaCfg.txMT) { dmaCfg.txMT = FALSE; evt |= HAL_UART_TX_EMPTY; } if (dmaCfg.txShdwValid) { uint8 decr = ST0; decr -= dmaCfg.txShdw; if (decr > dmaCfg.txTick) { // No protection for txShdwValid is required // because while the shadow was valid, DMA ISR cannot be triggered // to cause concurrent access to this variable. dmaCfg.txShdwValid = FALSE; } } if (dmaCfg.txDMAPending && !dmaCfg.txShdwValid) { // UART TX DMA is expected to be fired and enough time has lapsed since last DMA ISR // to know that DBUF can be overwritten halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX); halIntState_t intState; // Clear the DMA pending flag dmaCfg.txDMAPending = FALSE; HAL_DMA_SET_SOURCE(ch, dmaCfg.txBuf[dmaCfg.txSel]); HAL_DMA_SET_LEN(ch, dmaCfg.txIdx[dmaCfg.txSel]); dmaCfg.txSel ^= 1; HAL_ENTER_CRITICAL_SECTION(intState); HAL_DMA_ARM_CH(HAL_DMA_CH_TX); do { asm("NOP"); } while (!HAL_DMA_CH_ARMED(HAL_DMA_CH_TX)); HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_TX); HAL_DMA_MAN_TRIGGER(HAL_DMA_CH_TX); HAL_EXIT_CRITICAL_SECTION(intState); } else { halIntState_t his; HAL_ENTER_CRITICAL_SECTION(his); if ((dmaCfg.txIdx[dmaCfg.txSel] != 0) && !HAL_DMA_CH_ARMED(HAL_DMA_CH_TX) && !HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX)) { HAL_EXIT_CRITICAL_SECTION(his); HalUARTIsrDMA(); } else { HAL_EXIT_CRITICAL_SECTION(his); } } if (evt && (dmaCfg.uartCB != NULL)) { dmaCfg.uartCB(HAL_UART_DMA-1, evt); } }