/****************************************************************************** * @fn aesDmaInit * * @brief Initilize DMA for AES engine * * input parameters * * @param None * * @return None */ void aesDmaInit( void ) { halDMADesc_t *ch; /* Fill in DMA channel 1 descriptor and define it as input */ ch = HAL_DMA_GET_DESC1234( HAL_DMA_AES_IN ); HAL_DMA_SET_DEST( ch, HAL_AES_IN_ADDR ); /* Input of the AES module */ HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); /* Using the length field */ HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE ); /* One byte is transferred each time */ HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE ); /* A single byte is transferred each time */ HAL_DMA_SET_TRIG_SRC( ch, HAL_DMA_TRIG_ENC_DW ); /* Setting the AES module to generate the DMA trigger */ HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 ); /* The address for data fetch is incremented by 1 byte */ HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 ); /* The destination address is constant */ HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE ); /* The DMA complete interrupt flag is not set at completion */ HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); /* Transferring all 8 bits in each byte */ HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH ); /* DMA has priority */ /* Fill in DMA channel 2 descriptor and define it as output */ ch = HAL_DMA_GET_DESC1234( HAL_DMA_AES_OUT ); HAL_DMA_SET_SOURCE( ch, HAL_AES_OUT_ADDR ); /* Start address of the segment */ HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); /* Using the length field */ HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE ); /* One byte is transferred each time */ HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE ); /* A single byte is transferred each time */ HAL_DMA_SET_TRIG_SRC( ch, HAL_DMA_TRIG_ENC_UP ); /* Setting the AES module to generate the DMA trigger */ HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 ); /* The address for data fetch is constant */ HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 ); /* The destination address is incremented by 1 byte */ HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE ); /* The DMA complete interrupt flag is not set at completion */ HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); /* Transferring all 8 bits in each byte */ HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH ); /* DMA has priority */ }
/****************************************************************************** * @fn AesDmaSetup * * @brief Sets up DMA of 16 byte block using CC2540 HW aes encryption engine * * input parameters * * @param Cstate - Pointer to output data. * @param msg_out_len - message out length * @param msg_in - pointer to input data. * @param msg_in_len - message in length * * output parameters * * @param Cstate - Pointer to encrypted data. * * @return None * */ void AesDmaSetup( uint8 *Cstate, uint16 msg_out_len, uint8 *msg_in, uint16 msg_in_len ) { halDMADesc_t *ch; /* Modify descriptors for channel 1 */ ch = HAL_DMA_GET_DESC1234( HAL_DMA_AES_IN ); HAL_DMA_SET_SOURCE( ch, msg_in ); HAL_DMA_SET_LEN( ch, msg_in_len ); /* Modify descriptors for channel 2 */ ch = HAL_DMA_GET_DESC1234( HAL_DMA_AES_OUT ); HAL_DMA_SET_DEST( ch, Cstate ); HAL_DMA_SET_LEN( ch, msg_out_len ); /* Arm DMA channels 1 and 2 */ HAL_DMA_CLEAR_IRQ( HAL_DMA_AES_IN ); HAL_DMA_ARM_CH( HAL_DMA_AES_IN ); do { asm("NOP"); } while (!HAL_DMA_CH_ARMED(HAL_DMA_AES_IN)); HAL_DMA_CLEAR_IRQ( HAL_DMA_AES_OUT ); HAL_DMA_ARM_CH( HAL_DMA_AES_OUT ); do { asm("NOP"); } while (!HAL_DMA_CH_ARMED(HAL_DMA_AES_OUT)); }
/****************************************************************************** * @fn AesLoadKey * * @brief Writes the key into the CC2540 * * input parameters * * @param AesKey - Pointer to AES Key. * * @return None */ void AesLoadKey( uint8 *AesKey ) { #if (defined HAL_AES_DMA) && (HAL_AES_DMA == TRUE) halDMADesc_t *ch = HAL_DMA_GET_DESC1234( HAL_DMA_AES_IN ); /* Modify descriptors for channel 1 */ HAL_DMA_SET_SOURCE( ch, AesKey ); HAL_DMA_SET_LEN( ch, KEY_BLENGTH ); /* Arm DMA channel 1 */ HAL_DMA_CLEAR_IRQ( HAL_DMA_AES_IN ); HAL_DMA_ARM_CH( HAL_DMA_AES_IN ); do { asm("NOP"); } while (!HAL_DMA_CH_ARMED(HAL_DMA_AES_IN)); /* Set AES mode */ AES_SET_ENCR_DECR_KEY_IV( AES_LOAD_KEY ); /* Kick it off, block until AES is ready */ AES_START(); while( !(ENCCS & 0x08) ); #else /* Set AES mode */ AES_SET_ENCR_DECR_KEY_IV( AES_LOAD_KEY ); /* Load the block */ AesLoadBlock( AesKey ); #endif }
/****************************************************************************** * @fn HalUARTArmTxDMA * * @brief Arm the Tx DMA channel. * * @param None * * @return None *****************************************************************************/ static void HalUARTArmTxDMA(void) { halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX); HAL_DMA_SET_SOURCE(ch, dmaCfg.txBuf[dmaCfg.txSel]); HAL_DMA_SET_LEN(ch, dmaCfg.txIdx[dmaCfg.txSel]); dmaCfg.txSel ^= 1; dmaCfg.txTrig = 1; HAL_DMA_ARM_CH(HAL_DMA_CH_TX); HalUARTPollTxTrigDMA(); if (DMA_PM) { HAL_UART_DMA_SET_RDY_OUT(); } }
/****************************************************************************** * @fn HalUARTArmTxDMA * * @brief Arm the Tx DMA channel. * * @param None * * @return None *****************************************************************************/ static void HalUARTArmTxDMA(void) { halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX); HAL_DMA_SET_SOURCE(ch, dmaCfg.txBuf[dmaCfg.txSel]); HAL_DMA_SET_LEN(ch, dmaCfg.txIdx[dmaCfg.txSel]); dmaCfg.txSel ^= 1; dmaCfg.txTrig = 1; HAL_DMA_ARM_CH(HAL_DMA_CH_TX); /* Time to arm each DMA channel is 9 cycles as per the user's guide */ asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); asm("nop"); HalUARTPollTxTrigDMA(); if (DMA_PM) { HAL_UART_DMA_SET_RDY_OUT(); } }
/************************************************************************************************** * @fn npSpiTxIsr * * @brief This function handles the DMA Tx complete interrupt. * * input parameters * * None. * * output parameters * * None. * * @return None. ************************************************************************************************** */ void HalSpiTxIsr(void) { halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX); uint16 src; HAL_SPI_DBG_LOG(0x20); NP_SPI_ASSERT(halSpiState == NP_SPI_WAIT_TX); HAL_DMA_GET_SOURCE( ch, src ); if ((uint8 *)src != halSpiBuf) { osal_msg_deallocate((uint8 *)src); } halSpiState = NP_SPI_IDLE; // Callback is required so that client can schedule to call npSpiMonitor // function. npSpiTxCompleteCallback(); }
/************************************************************************************************** * @fn HalUARTWriteSPI * * @brief Transmit data bytes as a SPI packet. * * input parameters * * @param buf - pointer to the memory of the data bytes to send. * @param len - the length of the data bytes to send. * * output parameters * * None. * * @return Zero for any error; otherwise, 'len'. */ static spiLen_t HalUARTWriteSPI(uint8 *buf, spiLen_t len) { // Already in Tx or Rx transaction #ifdef RBA_UART_TO_SPI // The RBA Bridge is not written to handle re-writes so we must // just let it write if (spiTxLen != 0) #else //!RBA_UART_TO_SPI if (spiTxLen != 0 || SPI_RDY_OUT()) #endif { return 0; } if (len > SPI_MAX_DAT_LEN) { len = SPI_MAX_DAT_LEN; } spiTxLen = len; writeActive = 1; #if defined HAL_SPI_MASTER spiTxPkt[SPI_LEN_IDX] = len; (void)memcpy(spiTxPkt + SPI_DAT_IDX, buf, len); spiCalcFcs(spiTxPkt); spiTxPkt[SPI_SOF_IDX] = SPI_SOF; halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_SPI_CH_TX); HAL_DMA_SET_LEN(ch, SPI_PKT_LEN(spiTxPkt)); /* DMA TX might need padding */ /* Abort any pending DMA operations */ HAL_DMA_ABORT_CH( HAL_SPI_CH_RX ); spiRxIdx = 0; (void)memset(spiRxBuf, (DMA_PAD ^ 0xFF), SPI_MAX_PKT_LEN * sizeof(uint16)); HAL_DMA_ARM_CH(HAL_SPI_CH_RX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); /* Abort any pending DMA operations */ HAL_DMA_ABORT_CH( HAL_SPI_CH_TX ); HAL_DMA_ARM_CH(HAL_SPI_CH_TX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); SPI_SET_CSn_OUT(); while((!SPI_RDY_IN()) && (!spiRdyIsr) ); HAL_DMA_MAN_TRIGGER(HAL_SPI_CH_TX); #elif !defined HAL_SPI_MASTER #ifdef POWER_SAVING /* Disable POWER SAVING when transmission is initiated */ CLEAR_SLEEP_MODE(); #endif HAL_DMA_ARM_CH(HAL_SPI_CH_RX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); spiTxPkt[SPI_LEN_IDX] = len; (void)memcpy(spiTxPkt + SPI_DAT_IDX, buf, len); spiCalcFcs(spiTxPkt); spiTxPkt[SPI_SOF_IDX] = SPI_SOF; halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_SPI_CH_TX); HAL_DMA_SET_LEN(ch, SPI_PKT_LEN(spiTxPkt) + 1); /* slave DMA TX might drop the last byte */ HAL_DMA_ARM_CH(HAL_SPI_CH_TX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); SPI_SET_RDY_OUT(); #endif return len; }
/************************************************************************************************** * @fn HalUARTInitSPI * * @brief Initialize the SPI UART Transport. * * input parameters * * None. * * output parameters * * None. * * @return None. */ static void HalUARTInitSPI(void) { #if (HAL_UART_SPI == 1) PERCFG &= ~HAL_UART_PERCFG_BIT; /* Set UART0 I/O to Alt. 1 location on P0 */ #else PERCFG |= HAL_UART_PERCFG_BIT; /* Set UART1 I/O to Alt. 2 location on P1 */ #endif #if defined HAL_SPI_MASTER PxSEL |= HAL_UART_Px_SEL_M; /* SPI-Master peripheral select */ UxCSR = 0; /* Mode is SPI-Master Mode */ UxGCR = 15; /* Cfg for the max Rx/Tx baud of 2-MHz */ UxBAUD = 255; #elif !defined HAL_SPI_MASTER PxSEL |= HAL_UART_Px_SEL_S; /* SPI-Slave peripheral select */ UxCSR = CSR_SLAVE; /* Mode is SPI-Slave Mode */ #endif UxUCR = UCR_FLUSH; /* Flush it */ UxGCR |= BV(5); /* Set bit order to MSB */ P2DIR &= ~P2DIR_PRIPO; P2DIR |= HAL_UART_PRIPO; /* Setup GPIO for interrupts by falling edge on SPI_RDY_IN */ PxIEN |= SPI_RDYIn_BIT; PICTL |= PICTL_BIT; SPI_CLR_RDY_OUT(); PxDIR |= SPI_RDYOut_BIT; /* Setup Tx by DMA */ halDMADesc_t *ch = HAL_DMA_GET_DESC1234( HAL_SPI_CH_TX ); /* Abort any pending DMA operations (in case of a soft reset) */ HAL_DMA_ABORT_CH( HAL_SPI_CH_TX ); /* The start address of the destination */ HAL_DMA_SET_DEST( ch, DMA_UxDBUF ); /* Using the length field to determine how many bytes to transfer */ HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); /* One byte is transferred each time */ HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE ); /* The bytes are transferred 1-by-1 on Tx Complete trigger */ HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE ); HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_TX ); /* The source address is incremented by 1 byte after each transfer */ HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 ); HAL_DMA_SET_SOURCE( ch, spiTxPkt ); /* The destination address is constant - the Tx Data Buffer */ HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 ); /* The DMA Tx done is serviced by ISR */ HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_ENABLE ); /* Xfer all 8 bits of a byte xfer */ HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); /* DMA has highest priority for memory access */ HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH ); /* Setup Rx by DMA */ ch = HAL_DMA_GET_DESC1234( HAL_SPI_CH_RX ); /* Abort any pending DMA operations (in case of a soft reset) */ HAL_DMA_ABORT_CH( HAL_SPI_CH_RX ); /* The start address of the source */ HAL_DMA_SET_SOURCE( ch, DMA_UxDBUF ); /* Using the length field to determine how many bytes to transfer */ HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); /* The trick is to cfg DMA to xfer 2 bytes for every 1 byte of Rx. * The byte after the Rx Data Buffer is the Baud Cfg Register, * which always has a known value. So init Rx buffer to inverse of that * known value. DMA word xfer will flip the bytes, so every valid Rx byte * in the Rx buffer will be preceded by a DMA_PAD char equal to the * Baud Cfg Register value. */ HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_WORD ); /* The bytes are transferred 1-by-1 on Rx Complete trigger */ HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE_REPEATED ); HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_RX ); /* The source address is constant - the Rx Data Buffer */ HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 ); /* The destination address is incremented by 1 word after each transfer */ HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 ); HAL_DMA_SET_DEST( ch, spiRxBuf ); HAL_DMA_SET_LEN( ch, SPI_MAX_PKT_LEN ); /* The DMA is to be polled and shall not issue an IRQ upon completion */ HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE ); /* Xfer all 8 bits of a byte xfer */ HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); /* DMA has highest priority for memory access */ HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH ); volatile uint8 dummy = *(volatile uint8 *)DMA_UxDBUF; /* Clear the DMA Rx trigger */ HAL_DMA_CLEAR_IRQ(HAL_SPI_CH_RX); HAL_DMA_ARM_CH(HAL_SPI_CH_RX); (void)memset(spiRxBuf, (DMA_PAD ^ 0xFF), SPI_MAX_PKT_LEN * sizeof(uint16)); }
/****************************************************************************** * @fn HalUARTInitDMA * * @brief Initialize the UART * * @param none * * @return none *****************************************************************************/ static void HalUARTInitDMA(void) { halDMADesc_t *ch; #if (HAL_UART_DMA == 1) PERCFG &= ~HAL_UART_PERCFG_BIT; // Set UART0 I/O to Alt. 1 location on P0. #else PERCFG |= HAL_UART_PERCFG_BIT; // Set UART1 I/O to Alt. 2 location on P1. #endif PxSEL |= HAL_UART_Px_SEL; // Enable Peripheral control of Rx/Tx on Px. p0.2 P0.3 set peripheral //i0 setting UxCSR = CSR_MODE; // Mode is UART Mode. UxUCR = UCR_FLUSH; // Flush it. P2DIR &= ~P2DIR_PRIPO; //ÓÅÏȼ¶ P2DIR |= HAL_UART_PRIPO; if (DMA_PM) { // Setup GPIO for interrupts by falling edge on DMA_RDY_IN. PxIEN |= DMA_RDYIn_BIT; PICTL |= PICTL_BIT; HAL_UART_DMA_CLR_RDY_OUT(); PxDIR |= DMA_RDYOut_BIT; } #if !HAL_UART_TX_BY_ISR // Setup Tx by DMA. ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX ); // Abort any pending DMA operations (in case of a soft reset). HAL_DMA_ABORT_CH( HAL_DMA_CH_TX ); // The start address of the destination. HAL_DMA_SET_DEST( ch, DMA_UxDBUF ); // Using the length field to determine how many bytes to transfer. HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); // One byte is transferred each time. HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE ); // The bytes are transferred 1-by-1 on Tx Complete trigger. HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE ); HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_TX ); // The source address is incremented by 1 byte after each transfer. HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 ); // The destination address is constant - the Tx Data Buffer. HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 ); // The DMA Tx done is serviced by ISR in order to maintain full thruput. HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_ENABLE ); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); // DMA has highest priority for memory access. HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH); #endif // Setup Rx by DMA. ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX ); // Abort any pending DMA operations (in case of a soft reset). HAL_DMA_ABORT_CH( HAL_DMA_CH_RX ); // The start address of the source. HAL_DMA_SET_SOURCE( ch, DMA_UxDBUF ); // Using the length field to determine how many bytes to transfer. HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); /* The trick is to cfg DMA to xfer 2 bytes for every 1 byte of Rx. * The byte after the Rx Data Buffer is the Baud Cfg Register, * which always has a known value. So init Rx buffer to inverse of that * known value. DMA word xfer will flip the bytes, so every valid Rx byte * in the Rx buffer will be preceded by a DMA_PAD char equal to the * Baud Cfg Register value. */ HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_WORD ); // The bytes are transferred 1-by-1 on Rx Complete trigger. HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE_REPEATED ); HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_RX ); // The source address is constant - the Rx Data Buffer. HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 ); // The destination address is incremented by 1 word after each transfer. HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 ); HAL_DMA_SET_DEST( ch, dmaCfg.rxBuf ); HAL_DMA_SET_LEN( ch, HAL_UART_DMA_RX_MAX ); // The DMA is to be polled and shall not issue an IRQ upon completion. HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE ); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); // DMA has highest priority for memory access. HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH); volatile uint8 dummy = *(volatile uint8 *)DMA_UxDBUF; // Clear the DMA Rx trigger. HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_RX); HAL_DMA_ARM_CH(HAL_DMA_CH_RX); (void)memset(dmaCfg.rxBuf, (DMA_PAD ^ 0xFF), HAL_UART_DMA_RX_MAX * sizeof(uint16)); }
/************************************************************************************************** * @fn HalUARTWriteSPI * * @brief Transmit data bytes as a SPI packet. * * input parameters * * @param buf - pointer to the memory of the data bytes to send. * @param len - the length of the data bytes to send. * * output parameters * * None. * * @return Zero for any error; otherwise, 'len'. */ static spiLen_t HalUARTWriteSPI(uint8 *buf, spiLen_t len) { if (spiTxLen != 0) { return 0; } if (len > SPI_MAX_DAT_LEN) { len = SPI_MAX_DAT_LEN; } spiTxLen = len; #if defined HAL_SPI_MASTER spiRdyIsr = 0; spiTxPkt[SPI_LEN_IDX] = len; (void)memcpy(spiTxPkt + SPI_DAT_IDX, buf, len); spiCalcFcs(spiTxPkt); spiTxPkt[SPI_SOF_IDX] = SPI_SOF; halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_SPI_CH_TX); HAL_DMA_SET_LEN(ch, SPI_PKT_LEN(spiTxPkt)); /* DMA TX might need padding */ /* Abort any pending DMA operations */ HAL_DMA_ABORT_CH( HAL_SPI_CH_RX ); spiRxIdx = 0; (void)memset(spiRxBuf, (DMA_PAD ^ 0xFF), SPI_MAX_PKT_LEN * sizeof(uint16)); HAL_DMA_ARM_CH(HAL_SPI_CH_RX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); /* Abort any pending DMA operations */ HAL_DMA_ABORT_CH( HAL_SPI_CH_TX ); HAL_DMA_ARM_CH(HAL_SPI_CH_TX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); SPI_SET_CSn_OUT(); while((!SPI_RDY_IN()) && (!spiRdyIsr) ); HAL_DMA_MAN_TRIGGER(HAL_SPI_CH_TX); #elif !defined HAL_SPI_MASTER #ifdef POWER_SAVING /* Disable POWER SAVING when transmission is initiated */ CLEAR_SLEEP_MODE(); #endif SPI_CLR_RDY_OUT(); HAL_DMA_ARM_CH(HAL_SPI_CH_RX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); if ( SPI_RDY_IN() ) { SPI_SET_RDY_OUT(); } spiTxPkt[SPI_LEN_IDX] = len; (void)memcpy(spiTxPkt + SPI_DAT_IDX, buf, len); spiCalcFcs(spiTxPkt); spiTxPkt[SPI_SOF_IDX] = SPI_SOF; halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_SPI_CH_TX); HAL_DMA_SET_LEN(ch, SPI_PKT_LEN(spiTxPkt) + 1); /* slave DMA TX might drop the last byte */ HAL_DMA_ARM_CH(HAL_SPI_CH_TX); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); asm("NOP"); SPI_SET_RDY_OUT(); #endif return len; }
/************************************************************************************************** * @fn HalSpiDmaInit * * @brief This function initializes the DMA for the SPI driver. * * input parameters * * None. * * output parameters * * None. * * @return None. ************************************************************************************************** */ static void HalSpiDmaInit(void) { halDMADesc_t *ch; // Setup Tx by DMA ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX); // The start address of the source and destination. HAL_DMA_SET_SOURCE(ch, halSpiBuf); HAL_DMA_SET_DEST(ch, DMA_UDBUF); // Transfer the first byte + the number of bytes indicated by the first byte + 2 more bytes. HAL_DMA_SET_VLEN(ch, HAL_DMA_VLEN_1_P_VALOFFIRST_P_2); HAL_DMA_SET_LEN(ch, HAL_SPI_BUF_LEN); // One byte is transferred each time. HAL_DMA_SET_WORD_SIZE(ch, HAL_DMA_WORDSIZE_BYTE); // The bytes are transferred 1-by-1 on Tx Complete trigger. HAL_DMA_SET_TRIG_MODE(ch, HAL_DMA_TMODE_SINGLE); HAL_DMA_SET_TRIG_SRC(ch, DMATRIG_TX); // The source address is incremented by 1 byte after each transfer. HAL_DMA_SET_SRC_INC(ch, HAL_DMA_SRCINC_1); // The destination address is constant - the Tx Data Buffer. HAL_DMA_SET_DST_INC(ch, HAL_DMA_DSTINC_0); // The DMA shall issue an IRQ upon completion. HAL_DMA_SET_IRQ(ch, HAL_DMA_IRQMASK_ENABLE); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8(ch, HAL_DMA_M8_USE_8_BITS); // DMA has highest priority for memory access. HAL_DMA_SET_PRIORITY(ch, HAL_DMA_PRI_HIGH); ////////////////////////////////////////////////////////////////////////////// // Setup Rx by DMA. ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_RX); // The start address of the source and destination. HAL_DMA_SET_SOURCE(ch, DMA_UDBUF); HAL_DMA_SET_DEST(ch, halSpiBuf); // Transfer the first byte + the number of bytes indicated by the first byte + 2 more bytes. HAL_DMA_SET_VLEN(ch, HAL_DMA_VLEN_1_P_VALOFFIRST_P_2); HAL_DMA_SET_LEN(ch, HAL_SPI_BUF_LEN); HAL_DMA_SET_WORD_SIZE(ch, HAL_DMA_WORDSIZE_BYTE); // The bytes are transferred 1-by-1 on Rx Complete trigger. HAL_DMA_SET_TRIG_MODE(ch, HAL_DMA_TMODE_SINGLE); HAL_DMA_SET_TRIG_SRC(ch, DMATRIG_RX); // The source address is constant - the Rx Data Buffer. HAL_DMA_SET_SRC_INC(ch, HAL_DMA_SRCINC_0); // The destination address is incremented by 1 byte after each transfer. HAL_DMA_SET_DST_INC(ch, HAL_DMA_DSTINC_1); // The DMA shall issue an IRQ upon completion. HAL_DMA_SET_IRQ(ch, HAL_DMA_IRQMASK_ENABLE); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8(ch, HAL_DMA_M8_USE_8_BITS); // DMA has highest priority for memory access. HAL_DMA_SET_PRIORITY(ch, HAL_DMA_PRI_HIGH); }
/****************************************************************************** * @fn HalUARTPollDMA * * @brief Poll a USART module implemented by DMA. * * @param none * * @return none *****************************************************************************/ static void HalUARTPollDMA(void) { uint16 cnt = 0; uint8 evt = 0; if (HAL_UART_DMA_NEW_RX_BYTE(dmaCfg.rxHead)) { rxIdx_t tail = findTail(); // If the DMA has transferred in more Rx bytes, reset the Rx idle timer. if (dmaCfg.rxTail != tail) { dmaCfg.rxTail = tail; // Re-sync the shadow on any 1st byte(s) received. if (dmaCfg.rxTick == 0) { dmaCfg.rxShdw = ST0; } dmaCfg.rxTick = HAL_UART_DMA_IDLE; } else if (dmaCfg.rxTick) { // Use the LSB of the sleep timer (ST0 must be read first anyway). uint8 decr = ST0 - dmaCfg.rxShdw; if (dmaCfg.rxTick > decr) { dmaCfg.rxTick -= decr; dmaCfg.rxShdw = ST0; } else { dmaCfg.rxTick = 0; } } cnt = HalUARTRxAvailDMA(); } else { dmaCfg.rxTick = 0; } if (cnt >= HAL_UART_DMA_FULL) { evt = HAL_UART_RX_FULL; } else if (cnt >= HAL_UART_DMA_HIGH) { evt = HAL_UART_RX_ABOUT_FULL; PxOUT |= HAL_UART_Px_RTS; // Disable Rx flow. } else if (cnt && !dmaCfg.rxTick) { evt = HAL_UART_RX_TIMEOUT; } if (dmaCfg.txMT) { dmaCfg.txMT = FALSE; evt |= HAL_UART_TX_EMPTY; } if (dmaCfg.txShdwValid) { uint8 decr = ST0; decr -= dmaCfg.txShdw; if (decr > dmaCfg.txTick) { // No protection for txShdwValid is required // because while the shadow was valid, DMA ISR cannot be triggered // to cause concurrent access to this variable. dmaCfg.txShdwValid = FALSE; } } if (dmaCfg.txDMAPending && !dmaCfg.txShdwValid) { // UART TX DMA is expected to be fired and enough time has lapsed since last DMA ISR // to know that DBUF can be overwritten halDMADesc_t *ch = HAL_DMA_GET_DESC1234(HAL_DMA_CH_TX); halIntState_t intState; // Clear the DMA pending flag dmaCfg.txDMAPending = FALSE; HAL_DMA_SET_SOURCE(ch, dmaCfg.txBuf[dmaCfg.txSel]); HAL_DMA_SET_LEN(ch, dmaCfg.txIdx[dmaCfg.txSel]); dmaCfg.txSel ^= 1; HAL_ENTER_CRITICAL_SECTION(intState); HAL_DMA_ARM_CH(HAL_DMA_CH_TX); do { asm("NOP"); } while (!HAL_DMA_CH_ARMED(HAL_DMA_CH_TX)); HAL_DMA_CLEAR_IRQ(HAL_DMA_CH_TX); HAL_DMA_MAN_TRIGGER(HAL_DMA_CH_TX); HAL_EXIT_CRITICAL_SECTION(intState); } else { halIntState_t his; HAL_ENTER_CRITICAL_SECTION(his); if ((dmaCfg.txIdx[dmaCfg.txSel] != 0) && !HAL_DMA_CH_ARMED(HAL_DMA_CH_TX) && !HAL_DMA_CHECK_IRQ(HAL_DMA_CH_TX)) { HAL_EXIT_CRITICAL_SECTION(his); HalUARTIsrDMA(); } else { HAL_EXIT_CRITICAL_SECTION(his); } } if (evt && (dmaCfg.uartCB != NULL)) { dmaCfg.uartCB(HAL_UART_DMA-1, evt); } }
/****************************************************************************** * @fn HalUARTInitDMA * * @brief Initialize the UART * * @param none * * @return none *****************************************************************************/ static void HalUARTInitDMA(void) { halDMADesc_t *ch; P2DIR &= ~P2DIR_PRIPO; P2DIR |= HAL_UART_PRIPO; #if (HAL_UART_DMA == 1) PERCFG &= ~HAL_UART_PERCFG_BIT; // Set UART0 I/O to Alt. 1 location on P0. #else PERCFG |= HAL_UART_PERCFG_BIT; // Set UART1 I/O to Alt. 2 location on P1. #endif PxSEL |= HAL_UART_Px_RX_TX; // Enable Tx and Rx on P1. ADCCFG &= ~HAL_UART_Px_RX_TX; // Make sure ADC doesnt use this. UxCSR = CSR_MODE; // Mode is UART Mode. UxUCR = UCR_FLUSH; // Flush it. // Setup Tx by DMA. ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX ); // The start address of the destination. HAL_DMA_SET_DEST( ch, DMA_UDBUF ); // Using the length field to determine how many bytes to transfer. HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); // One byte is transferred each time. HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE ); // The bytes are transferred 1-by-1 on Tx Complete trigger. HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE ); HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_TX ); // The source address is incremented by 1 byte after each transfer. HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 ); // The destination address is constant - the Tx Data Buffer. HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 ); // The DMA Tx done is serviced by ISR in order to maintain full thruput. HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_ENABLE ); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); // DMA has highest priority for memory access. HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH ); // Setup Rx by DMA. ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX ); // The start address of the source. HAL_DMA_SET_SOURCE( ch, DMA_UDBUF ); // Using the length field to determine how many bytes to transfer. HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN ); /* The trick is to cfg DMA to xfer 2 bytes for every 1 byte of Rx. * The byte after the Rx Data Buffer is the Baud Cfg Register, * which always has a known value. So init Rx buffer to inverse of that * known value. DMA word xfer will flip the bytes, so every valid Rx byte * in the Rx buffer will be preceded by a DMA_PAD char equal to the * Baud Cfg Register value. */ HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_WORD ); // The bytes are transferred 1-by-1 on Rx Complete trigger. HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE_REPEATED ); HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_RX ); // The source address is constant - the Rx Data Buffer. HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 ); // The destination address is incremented by 1 word after each transfer. HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 ); HAL_DMA_SET_DEST( ch, dmaCfg.rxBuf ); HAL_DMA_SET_LEN( ch, HAL_UART_DMA_RX_MAX ); // The DMA is to be polled and shall not issue an IRQ upon completion. HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE ); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS ); // DMA has highest priority for memory access. HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH ); }
/****************************************************************************** * @fn HalIrGenInitNec * * @brief Initialize driver * * input parameters * * None. * * output parameters * * None. * * @return None. * */ void HalIrGenInitNec(void) { // Set TICKSPD:4M CLKCONCMD &= ~HAL_IRGEN_CLKCON_TICKSPD_MASK; CLKCONCMD |= HAL_IRGEN_TICKSPD_4MHZ; // Select port direction to output: P1.1 set output(1) P1DIR |= HAL_IRGEN_P1SEL_PORT; // Initially clear the port so that there will be no conflict P1 &= ~HAL_IRGEN_P1SEL_PORT; // Select port function to peripheral: P1.1 set Peripherial(1) P1SEL |= HAL_IRGEN_P1SEL_PORT; // Select alternative 2 location for T1 CH1 output (P1.1) PERCFG |= HAL_IRGEN_PERCFG_T1CFG; // -- set up bit signal generation timer -- // -- run timer once to make sure output is deactivated // Halt timer 1:Suspended T1CTL = HAL_IRGEN_T1CTL_MODE_SUSPEND; // Set up timer 1 channel 0 to compare mode 4 T1CCTL0 = HAL_IRGEN_TxCCTLx_CMP_CLR_SET | HAL_IRGEN_TxCCTLx_MODE_COMPARE; // Set up timer 1 channel 1 to compare mode 4 T1CCTL1 = HAL_IRGEN_TxCCTLx_CMP_CLR_SET | HAL_IRGEN_TxCCTLx_MODE_COMPARE; // Run one timer 1 until output is pulled low. // T1CNTL = 0; // Set up timer comparators for single carrier pulse output T1CC0L = 2; T1CC0H = 0; T1CC1L = 1; T1CC1H = 0; // Clear timer 1 // this will activate the output pin so start timer immediately. T1CNTL = 0; // Start timer 1: Set Modulo Mode T1CTL = HAL_IRGEN_BIT_TIMING_PRESCALER_DIV1 | HAL_IRGEN_T1CTL_MODE_MODULO; // Wait till the single bit is cleared while (T1CNTL == 0); // Stop timer 1 T1CTL = HAL_IRGEN_T1CTL_MODE_SUSPEND; #ifdef HAL_IRGEN_CARRIER // -- set up carrier signal generation timer -- // Clear counter and halt the timer T3CTL = HAL_IRGEN_T3CTL_CLR; // Set up timer 3 channel 0 to compare mode 4 T3CCTL0 = HAL_IRGEN_TxCCTLx_CMP_CLR_SET | HAL_IRGEN_TxCCTLx_MODE_COMPARE; // Set up timer 3 channel 1 to compare mode 4 T3CCTL1 = HAL_IRGEN_TxCCTLx_CMP_CLR_SET | HAL_IRGEN_TxCCTLx_MODE_COMPARE; // Configure 38kHz carrier with 33% duty cycle T3CC0 = HAL_IRGEN_NEC_CARRIER_DUTY_CYCLE; T3CC1 = HAL_IRGEN_NEC_CARRIER_ACTIVE_PER; // Combine carrier signal (Timer 1 CH 1 and Timer 3 CH 1 output) IRCTL |= 1; #endif // HAL_IRGEN_CARRIER // -- Configure DMA -- // Select proper DMA channel descriptor structure // Set up DMA channel for CC0 #if HAL_IRGEN_DMA_CH_CC0 == 0 pDmaDescCc0 = HAL_DMA_GET_DESC0(); #else pDmaDescCc0 = HAL_DMA_GET_DESC1234(HAL_IRGEN_DMA_CH_CC0); #endif // The start address of the destination. HAL_DMA_SET_DEST(pDmaDescCc0, HAL_IRGEN_T1CC0L_ADDR); // Using the length field to determine how many bytes to transfer. HAL_DMA_SET_VLEN(pDmaDescCc0, HAL_DMA_VLEN_USE_LEN); // Two bytes are transferred each time. HAL_DMA_SET_WORD_SIZE(pDmaDescCc0, HAL_DMA_WORDSIZE_WORD); // One word is transferred each time . HAL_DMA_SET_TRIG_MODE(pDmaDescCc0, HAL_DMA_TMODE_SINGLE); // Timer 1 channel 1 trigger DMA xfer HAL_DMA_SET_TRIG_SRC(pDmaDescCc0, HAL_DMA_TRIG_T1_CH1); // The source address is incremented by 1 word after each transfer. HAL_DMA_SET_SRC_INC(pDmaDescCc0, HAL_DMA_SRCINC_1); // The destination address is constant - T1CC0. HAL_DMA_SET_DST_INC(pDmaDescCc0, HAL_DMA_DSTINC_0); // IRQ handler is set up to tigger on CC1 HAL_DMA_SET_IRQ(pDmaDescCc0, HAL_DMA_IRQMASK_DISABLE); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8(pDmaDescCc0, HAL_DMA_M8_USE_8_BITS); // Set highest priority HAL_DMA_SET_PRIORITY(pDmaDescCc0, HAL_DMA_PRI_HIGH); // Set source data stream HAL_DMA_SET_SOURCE(pDmaDescCc0, &halIrGenCc0Buf[0]); // Set up DMA channel for CC1 #if HAL_IRGEN_DMA_CH_CC1 == 0 pDmaDescCc1 = HAL_DMA_GET_DESC0(); #else pDmaDescCc1 = HAL_DMA_GET_DESC1234(HAL_IRGEN_DMA_CH_CC1); #endif // The start address of the destination. HAL_DMA_SET_DEST(pDmaDescCc1, HAL_IRGEN_T1CC1L_ADDR); // Using the length field to determine how many bytes to transfer. HAL_DMA_SET_VLEN(pDmaDescCc1, HAL_DMA_VLEN_USE_LEN); // Two bytes are transferred each time. HAL_DMA_SET_WORD_SIZE(pDmaDescCc1, HAL_DMA_WORDSIZE_WORD); // One word is transferred each time HAL_DMA_SET_TRIG_MODE( pDmaDescCc1, HAL_DMA_TMODE_SINGLE ); // Timer 1 channel 1 trigger HAL_DMA_SET_TRIG_SRC(pDmaDescCc1, HAL_DMA_TRIG_T1_CH1); // The source address is not incremented since active periode is constant. HAL_DMA_SET_SRC_INC(pDmaDescCc1, HAL_DMA_SRCINC_0); // The destination address is constant - T1CC1. HAL_DMA_SET_DST_INC(pDmaDescCc1, HAL_DMA_DSTINC_0); // IRQ handler is set up so that sleep enable/disable can be determined. HAL_DMA_SET_IRQ(pDmaDescCc1, HAL_DMA_IRQMASK_ENABLE); // Xfer all 8 bits of a byte xfer. HAL_DMA_SET_M8(pDmaDescCc1, HAL_DMA_M8_USE_8_BITS); // Set highest priority HAL_DMA_SET_PRIORITY(pDmaDescCc1, HAL_DMA_PRI_HIGH); // Set source data stream. It is always constant. HAL_DMA_SET_SOURCE(pDmaDescCc1, &halIrGenCc1); // Timer is not running halIrGenTimerRunning = FALSE; }