/* remember to add cleanup code (above) if you add anything here */ static int ehci_mem_init(struct ehci_hcd *ehci, gfp_t flags) { int i; g_usb_pool_count = 0; g_debug_qtd_allocated = 0; g_debug_qH_allocated = 0; g_alloc_map = 0; if (cpu_is_mx37()) use_iram_qtd = 0; else use_iram_qtd = 1; usb_pool_initialize(USB_IRAM_BASE_ADDR + IRAM_TD_SIZE * IRAM_NTD * 2, USB_IRAM_SIZE - IRAM_TD_SIZE * IRAM_NTD * 2, 32); if (!ehci->iram_buffer[0]) { ehci->iram_buffer[0] = alloc_iram_buf(); ehci->iram_buffer_v[0] = IO_ADDRESS(ehci->iram_buffer[0]); ehci->iram_buffer[1] = alloc_iram_buf(); ehci->iram_buffer_v[1] = IO_ADDRESS(ehci->iram_buffer[1]); } /* QTDs for control/bulk/intr transfers */ ehci->qtd_pool = dma_pool_create("ehci_qtd", ehci_to_hcd(ehci)->self.controller, sizeof(struct ehci_qtd), 32/* byte alignment (for hw parts) */ , 4096 /* can't cross 4K */); if (!ehci->qtd_pool) goto fail; /* QHs for control/bulk/intr transfers */ ehci->qh_pool = dma_pool_create("ehci_qh", ehci_to_hcd(ehci)->self.controller, sizeof(struct ehci_qh), 32 /* byte alignment (for hw parts) */ , 4096 /* can't cross 4K */); if (!ehci->qh_pool) goto fail; ehci->async = ehci_qh_alloc(ehci, flags); if (!ehci->async) goto fail; /* ITD for high speed ISO transfers */ ehci->itd_pool = dma_pool_create("ehci_itd", ehci_to_hcd(ehci)->self.controller, sizeof(struct ehci_itd), 32/* byte alignment (for hw parts) */ , 4096 /* can't cross 4K */); if (!ehci->itd_pool) goto fail; /* SITD for full/low speed split ISO transfers */ ehci->sitd_pool = dma_pool_create("ehci_sitd", ehci_to_hcd(ehci)->self.controller, sizeof(struct ehci_sitd), 32/* byte alignment (for hw parts) */ , 4096 /* can't cross 4K */); if (!ehci->sitd_pool) goto fail; ehci->periodic = (__le32 *) dma_alloc_coherent(ehci_to_hcd(ehci)->self.controller, ehci->periodic_size * sizeof(__le32), &ehci->periodic_dma, 0); if (ehci->periodic == NULL) goto fail; for (i = 0; i < ehci->periodic_size; i++) ehci->periodic[i] = EHCI_LIST_END(ehci); /* software shadow of hardware table */ ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags); if (ehci->pshadow != NULL) return 0; fail: ehci_dbg(ehci, "couldn't init memory\n"); ehci_mem_cleanup(ehci); return -ENOMEM; }
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long old_boot_vector; unsigned long boot_vector; unsigned long timeout; #ifndef CONFIG_TRUSTED_FOUNDATIONS u32 reg; static void __iomem *vector_base = (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100); #endif /* * set synchronisation state between this boot processor * and the secondary one */ spin_lock(&boot_lock); /* set the reset vector to point to the secondary_startup routine */ #ifdef CONFIG_HOTPLUG_CPU if (cpumask_test_cpu(cpu, cpu_init_mask)) boot_vector = virt_to_phys(tegra_hotplug_startup); else #endif boot_vector = virt_to_phys(tegra_secondary_startup); smp_wmb(); #ifdef CONFIG_TRUSTED_FOUNDATIONS callGenericSMC(0xFFFFFFFC, 0xFFFFFFE5, boot_vector); #else old_boot_vector = readl(vector_base); writel(boot_vector, vector_base); /* enable cpu clock on cpu */ reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); writel(reg & ~(1<<(8+cpu)), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); reg = 0x1111<<cpu; writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); /* unhalt the cpu */ writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14 + 0x8*(cpu-1)); timeout = jiffies + HZ; while (time_before(jiffies, timeout)) { if (readl(vector_base) != boot_vector) break; udelay(10); } /* put the old boot vector back */ writel(old_boot_vector, vector_base); #endif /* * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ spin_unlock(&boot_lock); return 0; }
* http://armlinux.simtec.co.uk/ * Ben Dooks <*****@*****.**> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ #include "tegra_soc.h" int en_dmic; /* i2s controller */ static void *das_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); struct tegra_i2s_info { struct platform_device *pdev; struct tegra_audio_platform_data *pdata; struct clk *i2s_clk; struct clk *dap_mclk; struct clk *audio_sync_clk; phys_addr_t i2s_phys; void __iomem *i2s_base; unsigned long dma_req_sel; int irq; /* Control for whole I2S (Data format, etc.) */ unsigned int bit_format;
int davinci_i2s_probe(struct platform_device *pdev) { int tmp, link_cnt; int count = 0; int backup_count = 0; struct snd_soc_device *socdev = platform_get_drvdata(pdev); struct snd_soc_machine *machine = socdev->machine; struct snd_soc_cpu_dai *cpu_dai; struct davinci_audio_dev *dev; struct resource *mem, *ioarea; struct evm_snd_platform_data *parray = pdev->dev.platform_data; struct evm_snd_platform_data *pdata; struct davinci_pcm_dma_params *dma_data; int ret = 0; dev = kzalloc(sizeof(struct davinci_audio_dev) * machine->num_links, GFP_KERNEL); if (!dev) return -ENOMEM; dma_data = kzalloc(sizeof(struct davinci_pcm_dma_params) * (machine->num_links << 1), GFP_KERNEL); if (!dma_data) goto err_release_dev; for (link_cnt = 0; link_cnt < machine->num_links; link_cnt++) { mem = platform_get_resource(pdev, IORESOURCE_MEM, link_cnt); if (!mem) { dev_err(&pdev->dev, "no mem resource?\n"); ret = -ENODEV; backup_count = 0; goto err_release_data; } ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, pdev->name); if (!ioarea) { dev_err(&pdev->dev, "Audio region already claimed\n"); ret = -EBUSY; backup_count = 1; goto err_release_data; } cpu_dai = machine->dai_link[link_cnt].cpu_dai; cpu_dai->private_data = &dev[link_cnt]; pdata = &parray[link_cnt]; dev[link_cnt].clk = clk_get(&pdev->dev, pdata->clk_name); if (IS_ERR(dev[link_cnt].clk)) { ret = -ENODEV; backup_count = 2; goto err_release_data; } clk_enable(dev[link_cnt].clk); dev[link_cnt].base = (void __iomem *)IO_ADDRESS(mem->start); dev[link_cnt].op_mode = pdata->op_mode; dev[link_cnt].tdm_slots = pdata->tdm_slots; dev[link_cnt].num_serializer = pdata->num_serializer; dev[link_cnt].serial_dir = pdata->serial_dir; dev[link_cnt].codec_fmt = pdata->codec_fmt; dma_data[count].name = "I2S PCM Stereo out"; dma_data[count].channel = pdata->tx_dma_ch; dma_data[count].eventq_no = pdata->eventq_no; dma_data[count].dma_addr = (dma_addr_t) (pdata->tx_dma_offset + io_v2p(dev[link_cnt].base)); dev[link_cnt].dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &dma_data[count]; count++; dma_data[count].name = "I2S PCM Stereo in"; dma_data[count].channel = pdata->rx_dma_ch; dma_data[count].eventq_no = pdata->eventq_no; dma_data[count].dma_addr = (dma_addr_t)(pdata->rx_dma_offset + io_v2p(dev[link_cnt].base)); dev[link_cnt].dma_params[SNDRV_PCM_STREAM_CAPTURE] = &dma_data[count]; count++; } return 0; err_release_data: for (tmp = link_cnt; tmp >= 0; tmp--) { if (backup_count > 2) clk_disable(dev[tmp].clk); if (backup_count > 1) { mem = platform_get_resource(pdev, IORESOURCE_MEM, tmp); release_mem_region(mem->start, (mem->end - mem->start) + 1); } backup_count = 3; } kfree(dma_data); err_release_dev: kfree(dev); return ret; }
.vendor = "Dell", .product = "Streak7", .nluns = 2, }; static struct platform_device tegra_usb_fsg_device = { .name = "usb_mass_storage", .id = -1, .dev = { .platform_data = &tegra_usb_fsg_platform, }, }; static struct plat_serial8250_port debug_uart_platform_data[] = { { .membase = IO_ADDRESS(TEGRA_UARTA_BASE), .mapbase = TEGRA_UARTA_BASE, .irq = INT_UARTA, .flags = UPF_BOOT_AUTOCONF, .iotype = UPIO_MEM, .regshift = 2, .uartclk = 216000000, }, { .flags = 0, } }; static struct platform_device debug_uart = { .name = "serial8250",
static __init void da850_evm_init(void) { int ret; ret = da850_register_gpio(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); ret = pmic_tps65070_init(); if (ret) pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); ret = da850_register_edma(da850_edma_rsv); if (ret) pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); ret = davinci_cfg_reg_list(da850_i2c0_pins); if (ret) pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret); ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); if (ret) pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret); ret = da8xx_register_watchdog(); if (ret) pr_warn("%s: watchdog registration failed: %d\n", __func__, ret); if (HAS_MMC) { ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins); if (ret) pr_warn("%s: MMCSD0 mux setup failed: %d\n", __func__, ret); ret = gpio_request(DA850_MMCSD_CD_PIN, "MMC CD\n"); if (ret) pr_warn("%s: can not open GPIO %d\n", __func__, DA850_MMCSD_CD_PIN); gpio_direction_input(DA850_MMCSD_CD_PIN); ret = gpio_request(DA850_MMCSD_WP_PIN, "MMC WP\n"); if (ret) pr_warn("%s: can not open GPIO %d\n", __func__, DA850_MMCSD_WP_PIN); gpio_direction_input(DA850_MMCSD_WP_PIN); ret = da8xx_register_mmcsd0(&da850_mmc_config); if (ret) pr_warn("%s: MMCSD0 registration failed: %d\n", __func__, ret); ret = da850_wl12xx_init(); if (ret) pr_warn("%s: WL12xx initialization failed: %d\n", __func__, ret); } davinci_serial_init(da8xx_serial_device); i2c_register_board_info(1, da850_evm_i2c_devices, ARRAY_SIZE(da850_evm_i2c_devices)); /* * shut down uart 0 and 1; they are not used on the board and * accessing them causes endless "too much work in irq53" messages * with arago fs */ __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); ret = davinci_cfg_reg_list(da850_evm_mcasp_pins); if (ret) pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret); da850_evm_snd_data.sram_pool = sram_get_gen_pool(); da8xx_register_mcasp(0, &da850_evm_snd_data); ret = davinci_cfg_reg_list(da850_lcdcntl_pins); if (ret) pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret); ret = da8xx_register_uio_pruss(); if (ret) pr_warn("da850_evm_init: pruss initialization failed: %d\n", ret); /* Handle board specific muxing for LCD here */ ret = davinci_cfg_reg_list(da850_evm_lcdc_pins); if (ret) pr_warn("%s: EVM specific LCD mux setup failed: %d\n", __func__, ret); ret = da850_lcd_hw_init(); if (ret) pr_warn("%s: LCD initialization failed: %d\n", __func__, ret); sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl, ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); if (ret) pr_warn("%s: LCDC registration failed: %d\n", __func__, ret); ret = da8xx_register_rtc(); if (ret) pr_warn("%s: RTC setup failed: %d\n", __func__, ret); ret = da850_evm_init_cpufreq(); if (ret) pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret); ret = da8xx_register_cpuidle(); if (ret) pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret); ret = da850_register_pm(&da850_pm_device); if (ret) pr_warn("%s: suspend registration failed: %d\n", __func__, ret); da850_vpif_init(); ret = spi_register_board_info(da850evm_spi_info, ARRAY_SIZE(da850evm_spi_info)); if (ret) pr_warn("%s: spi info registration failed: %d\n", __func__, ret); ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info)); if (ret) pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret); ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE); if (ret) pr_warn("%s: SATA registration failed: %d\n", __func__, ret); da850_evm_setup_mac_addr(); ret = da8xx_register_rproc(); if (ret) pr_warn("%s: dsp/rproc registration failed: %d\n", __func__, ret); }
* TMR3 - used as general CPU timer. * TMR4 - used for LP2 wakeup. */ #define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE) #define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE) #define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE) #define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE) #define timer_writel(value, reg) \ __raw_writel(value, (u32)timer_reg_base + (reg)) #define timer_readl(reg) \ __raw_readl((u32)timer_reg_base + (reg)) static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); #ifdef CONFIG_PM_SLEEP static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id) { timer_writel(1<<30, TIMER4_OFFSET + TIMER_PCR); return IRQ_HANDLED; } static struct irqaction tegra_lp2wake_irq = { .name = "timer_lp2wake", .flags = IRQF_DISABLED, .handler = tegra_lp2wake_interrupt, .dev_id = NULL, .irq = INT_TMR4, };
static int tegra_uart_probe(struct platform_device *pdev) { struct tegra_uart_port *t; struct uart_port *u; struct resource *resource; int ret; char name[64]; if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr) { pr_err("Invalid Uart instance (%d)\n", pdev->id); return -ENODEV; } t = kzalloc(sizeof(struct tegra_uart_port), GFP_KERNEL); if (!t) { pr_err("%s: Failed to allocate memory\n", __func__); return -ENOMEM; } u = &t->uport; u->dev = &pdev->dev; platform_set_drvdata(pdev, u); u->line = pdev->id; u->ops = &tegra_uart_ops; u->type = ~PORT_UNKNOWN; u->fifosize = 32; resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (unlikely(!resource)) return -ENXIO; u->mapbase = resource->start; u->membase = IO_ADDRESS(u->mapbase); if (unlikely(!u->membase)) return -ENOMEM; u->irq = platform_get_irq(pdev, 0); if (unlikely(u->irq < 0)) return -ENXIO; u->regshift = 2; t->clk = clk_get(&pdev->dev, NULL); if (IS_ERR_OR_NULL(t->clk)) { dev_err(&pdev->dev, "Couldn't get the clock\n"); goto fail; } ret = uart_add_one_port(&tegra_uart_driver, u); if (ret) { pr_err("%s: Failed(%d) to add uart port %s%d\n", __func__, ret, tegra_uart_driver.dev_name, u->line); kfree(t); platform_set_drvdata(pdev, NULL); return ret; } snprintf(name, sizeof(name), "tegra_hsuart_%d", u->line); pr_info("Registered UART port %s%d\n", tegra_uart_driver.dev_name, u->line); t->uart_state = TEGRA_UART_CLOSED; return ret; fail: kfree(t); return -ENODEV; }
static int __devinit nmk_gpio_probe(struct platform_device *dev) { struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; struct nmk_gpio_chip *nmk_chip; struct gpio_chip *chip; struct resource *res; struct clk *clk; int secondary_irq; int irq; int ret; if (!pdata) return -ENODEV; res = platform_get_resource(dev, IORESOURCE_MEM, 0); if (!res) { ret = -ENOENT; goto out; } irq = platform_get_irq(dev, 0); if (irq < 0) { ret = irq; goto out; } secondary_irq = platform_get_irq(dev, 1); if (secondary_irq >= 0 && !pdata->get_secondary_status) { ret = -EINVAL; goto out; } if (request_mem_region(res->start, resource_size(res), dev_name(&dev->dev)) == NULL) { ret = -EBUSY; goto out; } clk = clk_get(&dev->dev, NULL); if (IS_ERR(clk)) { ret = PTR_ERR(clk); goto out_release; } nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); if (!nmk_chip) { ret = -ENOMEM; goto out_clk; } /* * The virt address in nmk_chip->addr is in the nomadik register space, * so we can simply convert the resource address, without remapping */ nmk_chip->bank = dev->id; nmk_chip->clk = clk; nmk_chip->addr = __io(IO_ADDRESS(res->start)); nmk_chip->chip = nmk_gpio_template; nmk_chip->parent_irq = irq; nmk_chip->secondary_parent_irq = secondary_irq; nmk_chip->get_secondary_status = pdata->get_secondary_status; nmk_chip->set_ioforce = pdata->set_ioforce; nmk_chip->sleepmode = pdata->supports_sleepmode; spin_lock_init(&nmk_chip->lock); chip = &nmk_chip->chip; chip->base = pdata->first_gpio; chip->ngpio = pdata->num_gpio; chip->label = pdata->name ?: dev_name(&dev->dev); chip->dev = &dev->dev; chip->owner = THIS_MODULE; clk_enable(nmk_chip->clk); nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); clk_disable(nmk_chip->clk); ret = gpiochip_add(&nmk_chip->chip); if (ret) goto out_free; BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); nmk_gpio_chips[nmk_chip->bank] = nmk_chip; platform_set_drvdata(dev, nmk_chip); nmk_gpio_init_irq(nmk_chip); dev_info(&dev->dev, "Bits %i-%i at address %p\n", nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); return 0; out_free: kfree(nmk_chip); out_clk: clk_disable(clk); clk_put(clk); out_release: release_mem_region(res->start, resource_size(res)); out: dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, pdata->first_gpio, pdata->first_gpio+31); return ret; }
/******************************************************************************* 函 数 名:omTimerGet 功能描述:获取系统timer的相对slice值 输入参数:无 输出参数:无 返 回 值:timer slice value *******************************************************************************/ unsigned int omTimerGet(void) { return (*(volatile unsigned int *)(SOC_AO_SCTRL_SC_ALWAYSON_SYS_STAT6_ADDR(IO_ADDRESS(SOC_SC_ON_BASE_ADDR)))); }
/** * usb_hcd_omap_probe - initialize OMAP-based HCDs * Context: !in_interrupt() * * Allocates basic resources for this USB host controller, and * then invokes the start() method for the HCD associated with it * through the hotplug entry's driver_data. */ static int usb_hcd_omap_probe (const struct hc_driver *driver, struct platform_device *pdev) { int retval, irq; struct usb_hcd *hcd = 0; struct ohci_hcd *ohci; if (pdev->num_resources != 2) { printk(KERN_ERR "hcd probe: invalid num_resources: %i\n", pdev->num_resources); return -ENODEV; } if (pdev->resource[0].flags != IORESOURCE_MEM || pdev->resource[1].flags != IORESOURCE_IRQ) { printk(KERN_ERR "hcd probe: invalid resource type\n"); return -ENODEV; } usb_host_ck = clk_get(0, "usb_hhc_ck"); if (IS_ERR(usb_host_ck)) return PTR_ERR(usb_host_ck); if (!cpu_is_omap15xx()) usb_dc_ck = clk_get(0, "usb_dc_ck"); else usb_dc_ck = clk_get(0, "lb_ck"); if (IS_ERR(usb_dc_ck)) { clk_put(usb_host_ck); return PTR_ERR(usb_dc_ck); } hcd = usb_create_hcd (driver, &pdev->dev, pdev->dev.bus_id); if (!hcd) { retval = -ENOMEM; goto err0; } hcd->rsrc_start = pdev->resource[0].start; hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { dev_dbg(&pdev->dev, "request_mem_region failed\n"); retval = -EBUSY; goto err1; } hcd->regs = (void __iomem *) (int) IO_ADDRESS(hcd->rsrc_start); ohci = hcd_to_ohci(hcd); ohci_hcd_init(ohci); host_initialized = 0; host_enabled = 1; irq = platform_get_irq(pdev, 0); if (irq < 0) { retval = -ENXIO; goto err2; } retval = usb_add_hcd(hcd, irq, IRQF_DISABLED); if (retval) goto err2; host_initialized = 1; if (!host_enabled) omap_ohci_clock_power(0); return 0; err2: release_mem_region(hcd->rsrc_start, hcd->rsrc_len); err1: usb_put_hcd(hcd); err0: clk_put(usb_dc_ck); clk_put(usb_host_ck); return retval; }
int utmi_phy_set_snps_trking_data(void) { void __iomem *base = IO_ADDRESS(TEGRA_USB_BASE); u32 val; struct clk *utmi_pad_clk; utmi_pad_clk = clk_get_sys("utmip-pad", NULL); if (IS_ERR(utmi_pad_clk)) { pr_err("%s: can't get utmip pad clock\n", __func__); return PTR_ERR(utmi_pad_clk); } if (!pmc_base) pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); clk_enable(utmi_pad_clk); spin_lock_irqsave(&pmc_lock, flags); /* Bias pad MASTER_ENABLE=1 */ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL); val |= BIAS_MASTER_PROG_VAL; writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL); /* Setting the tracking length time */ val = readl(base + UTMIP_BIAS_CFG1); val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); val |= UTMIP_BIAS_PDTRK_COUNT(5); writel(val, base + UTMIP_BIAS_CFG1); /* Bias PDTRK is Shared and MUST be done from USB1 ONLY, PD_TRK=0 */ val = readl(base + UTMIP_BIAS_CFG1); val &= ~UTMIP_BIAS_PDTRK_POWERDOWN; writel(val, base + UTMIP_BIAS_CFG1); val = readl(base + UTMIP_BIAS_CFG1); val |= UTMIP_BIAS_PDTRK_POWERUP; writel(val, base + UTMIP_BIAS_CFG1); /* Wait for 25usec */ udelay(25); /* Bias pad MASTER_ENABLE=0 */ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL); val &= ~BIAS_MASTER_PROG_VAL; writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL); /* Wait for 1usec */ udelay(1); /* Bias pad MASTER_ENABLE=1 */ val = readl(pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL); val |= BIAS_MASTER_PROG_VAL; writel(val, pmc_base + PMC_UTMIP_BIAS_MASTER_CNTRL); /* Read RCTRL and TCTRL from UTMIP space */ val = readl(base + UTMIP_BIAS_STS0); utmip_rctrl_val = 0xf + ffz(UTMIP_RCTRL_VAL(val)); utmip_tctrl_val = 0xf + ffz(UTMIP_TCTRL_VAL(val)); /* PD_TRK=1 */ val = readl(base + UTMIP_BIAS_CFG1); val |= UTMIP_BIAS_PDTRK_POWERDOWN; writel(val, base + UTMIP_BIAS_CFG1); /* Program thermally encoded RCTRL_VAL, TCTRL_VAL into PMC space */ val = readl(pmc_base + PMC_UTMIP_TERM_PAD_CFG); val = PMC_TCTRL_VAL(utmip_tctrl_val) | PMC_RCTRL_VAL(utmip_rctrl_val); writel(val, pmc_base + PMC_UTMIP_TERM_PAD_CFG); spin_unlock_irqrestore(&pmc_lock, flags); clk_disable(utmi_pad_clk); clk_put(utmi_pad_clk); return 0; }
.enable_ms = pl010_enable_ms, .break_ctl = pl010_break_ctl, .startup = pl010_startup, .shutdown = pl010_shutdown, .set_termios = pl010_set_termios, .type = pl010_type, .release_port = pl010_release_port, .request_port = pl010_request_port, .config_port = pl010_config_port, .verify_port = pl010_verify_port, }; static struct uart_amba_port amba_ports[UART_NR] = { { .port = { .membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE), .mapbase = INTEGRATOR_UART0_BASE, .iotype = SERIAL_IO_MEM, .irq = IRQ_UARTINT0, .uartclk = 14745600, .fifosize = 16, .ops = &amba_pl010_pops, .flags = ASYNC_BOOT_AUTOCONF, .line = 0, }, .dtr_mask = 1 << 5, .rts_mask = 1 << 4, }, { .port = { .membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
static int tegra_uart_probe(struct platform_device *pdev) { struct tegra_uart_port *t; struct uart_port *u; struct tegra_uart_platform_data *pdata; struct resource *resource; int ret; char name[64]; if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr) { pr_err("Invalid Uart instance (%d)\n", pdev->id); return -ENODEV; } t = kzalloc(sizeof(struct tegra_uart_port), GFP_KERNEL); if (!t) { pr_err("%s: Failed to allocate memory\n", __func__); return -ENOMEM; } u = &t->uport; u->dev = &pdev->dev; platform_set_drvdata(pdev, u); u->line = pdev->id; u->ops = &tegra_uart_ops; u->type = PORT_TEGRA; u->fifosize = 32; pdata = u->dev->platform_data; if (pdata && pdata->is_irda) { dev_info(&pdev->dev, "Initialized UART %d as SIR PHY\n", u->line); t->is_irda = pdata->is_irda; t->irda_init = pdata->irda_init; t->irda_start = pdata->irda_start; t->irda_mode_switch = pdata->irda_mode_switch; t->irda_shutdown = pdata->irda_shutdown; t->irda_remove = pdata->irda_remove; if (t->irda_init) t->irda_init(); } resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (unlikely(!resource)) { ret = -ENXIO; goto fail; } u->mapbase = resource->start; u->membase = IO_ADDRESS(u->mapbase); if (unlikely(!u->membase)) { ret = -ENOMEM; goto fail; } u->iotype = UPIO_MEM32; u->irq = platform_get_irq(pdev, 0); if (unlikely(u->irq < 0)) { ret = -ENXIO; goto fail; } u->regshift = 2; t->clk = clk_get(&pdev->dev, NULL); if (IS_ERR_OR_NULL(t->clk)) { dev_err(&pdev->dev, "Couldn't get the clock\n"); ret = -ENODEV; goto fail; } ret = uart_add_one_port(&tegra_uart_driver, u); if (ret) { pr_err("%s: Failed(%d) to add uart port %s%d\n", __func__, ret, tegra_uart_driver.dev_name, u->line); goto fail; } snprintf(name, sizeof(name), "tegra_hsuart_%d", u->line); pr_info("Registered UART port %s%d\n", tegra_uart_driver.dev_name, u->line); t->uart_state = TEGRA_UART_CLOSED; if (!RX_FORCE_PIO) { ret = tegra_uart_init_rx_dma_buffer(t); if (ret < 0) { pr_err("%s: Failed(%d) to allocate rx dma buffer " "%s%d\n", __func__, ret, tegra_uart_driver.dev_name, u->line); goto rx_dma_buff_fail; } } return ret; rx_dma_buff_fail: uart_remove_one_port(&tegra_uart_driver, u); fail: if (t->clk) clk_put(t->clk); platform_set_drvdata(pdev, NULL); kfree(t); return ret; }
#define PADS_PLL_CTL 0x000000B8 #define PADS_PLL_CTL_RST_B4SM (1 << 1) #define PADS_PLL_CTL_LOCKDET (1 << 8) #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16) #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16) #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16) #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16) #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) /* PMC access is required for PCIE xclk (un)clamping */ #define PMC_SCRATCH42 0x144 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0) static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); #define pmc_writel(value, reg) \ __raw_writel(value, reg_pmc_base + (reg)) #define pmc_readl(reg) \ __raw_readl(reg_pmc_base + (reg)) /* * Tegra2 defines 1GB in the AXI address map for PCIe. * * That address space is split into different regions, with sizes and * offsets as follows: * * 0x80000000 - 0x80003fff - PCI controller registers * 0x80004000 - 0x80103fff - PCI configuration space * 0x80104000 - 0x80203fff - PCI extended configuration space
int __init x3_regulator_init(void) { void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); u32 pmc_ctrl; /* configure the power management controller to trigger PMU * interrupts when low */ pmc_ctrl = readl(pmc + PMC_CTRL); writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); #if defined(CONFIG_MFD_TPS80031) /* Disable battery charging if power adapter is connected. */ if (get_power_supply_type() == POWER_SUPPLY_TYPE_MAINS) { bcharger_pdata.num_consumer_supplies = 0; bcharger_pdata.consumer_supplies = NULL; battery_gauge_data.battery_present = 0; } #endif i2c_register_board_info(4, x3_regulators, ARRAY_SIZE(x3_regulators)); #if defined(CONFIG_REGULATOR_AAT2870) i2c_register_board_info(2, x3_aat2870_i2c_board_info, ARRAY_SIZE(x3_aat2870_i2c_board_info)); #endif #if defined(CONFIG_REGULATOR_GPIO_SWITCH) #if defined(MACH_X3_REV_B) || defined(MACH_X3_REV_C) || defined(MACH_X3_REV_D) || defined(MACH_X3_REV_E) || defined(MACH_X3_REV_1_0) x3_gpio_switch_regulator_init(); #else // #if defined(CONFIG_MACH_VU10) gpio_switch_regulator_init(); #else switch(x3_get_hw_rev_pcb_version()) { case hw_rev_pcb_type_A : case hw_rev_pcb_type_B : case hw_rev_pcb_type_C : x3_gpio_switch_regulator_init_rev_C(); break; case hw_rev_pcb_type_D : x3_gpio_switch_regulator_init_rev_D(); break; case hw_rev_pcb_type_E : default : x3_gpio_switch_regulator_init_rev_E(); break; } #endif // #endif #endif pm_power_off = x3_power_off; return 0; }
int __init musb_platform_init(struct musb *musb) { void *__iomem tibase = musb->ctrl_base; u32 revision, phystatus; u8 id; struct platform_device *pdev = to_platform_device(musb->controller); struct musb_hdrc_platform_data *plat; struct clk *clkp; if (pdev->id == -1) id = 0; else id = pdev->id; switch (id) { case 0 : clkp = clk_get (NULL, "USBCLK"); break; default : return -ENODEV; } if (IS_ERR(clkp)) return -ENODEV; musb->clock = clkp; clk_use (clkp); if (clk_enable (clkp) != 0) return -ENODEV; plat = musb->controller->platform_data; /* overwrite the USB mode */ #ifdef CONFIG_USB_MUSB_HDRC_HCD plat->mode = MUSB_HOST; #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) plat->mode = MUSB_PERIPHERAL; #elif defined(CONFIG_USB_MUSB_OTG) plat->mode = MUSB_OTG; #else dev_dbg(musb->controller, "incompatible Kconfig role setting"); return -EINVAL; #endif musb->board_mode = plat->mode; musb->pRegs += DAVINCI_BASE_OFFSET; /* returns zero if e.g. not clocked */ revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); if (revision == 0) return -ENODEV; /* note that transceiver issues make us want to charge * VBUS only when the PHY PLL is not active. */ #if defined(CONFIG_MACH_DAVINCI_EVM) || defined (CONFIG_MACH_DAVINCI_HD_EVM) #ifdef CONFIG_USB_MUSB_OTG /* clear EMACEN to enble OTG GPIO 16 for VBus power control */ /* Set GPIO Direction */ REG_DVEVM_GPIO45_DIR &= ~(DVEVM_GPIO45_DIR_OUT); davinci_cfg_reg(DM644X_GPIO3V); #endif evm_vbus_work.data = musb; #endif #ifdef CONFIG_ARCH_DAVINCI_DM355 #ifdef CONFIG_USB_MUSB_HDRC_HCD gpio_direction_output(2, 1); #else gpio_direction_output(2, 0); #endif __raw_writel( __raw_readl (IO_ADDRESS(DM355_DEEPSLEEP_REG)) & 0xfffffff0, IO_ADDRESS (DM355_DEEPSLEEP_REG)); #endif /* reset the controller */ musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); /* start the on-chip PHY and its PLL */ phy_on(); msleep(5); phystatus = __raw_readl(IO_ADDRESS(USBPHY_CTL_PADDR)); #ifdef CONFIG_ARCH_DAVINCI_DM646x #ifdef CONFIG_USB_MUSB_HDRC_HCD __raw_writel(phystatus | DM646X_USBPHY_SESSION_VBUS | DM646X_USBPHY_NDATAPOL, IO_ADDRESS(USBPHY_CTL_PADDR)); #else __raw_writel (phystatus | DM646X_USBPHY_SESSION_VBUS | DM646X_USBPHY_NDATAPOL | DM646X_USBPHY_PERI_USBID, IO_ADDRESS(USBPHY_CTL_PADDR)); #endif #endif /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", revision, musb_readl((void *__iomem)IO_ADDRESS(USBPHY_CTL_PADDR), 0x00), musb_readb(tibase, DAVINCI_USB_CTRL_REG)); musb->isr = davinci_interrupt; return 0; }
#define TIMER_PERIODIC (1 << 30) #define TIMER_PCR 0x4 #define TIMER_PCR_INTR (1 << 30) #define WDT_CFG (0) #define WDT_CFG_TMR_SRC (7 << 0) /* for TMR7. */ #define WDT_CFG_PERIOD (1 << 4) #define WDT_CFG_INT_EN (1 << 12) #define WDT_CFG_SYS_RST_EN (1 << 14) #define WDT_CFG_PMC2CAR_RST_EN (1 << 15) #define WDT_CMD (8) #define WDT_CMD_START_COUNTER (1 << 0) #define WDT_CMD_DISABLE_COUNTER (1 << 1) #define WDT_UNLOCK (0xC) #define WDT_UNLOCK_PATTERN (0xC45A << 0) static void __iomem *wdt_timer = IO_ADDRESS(TEGRA_TMR7_BASE); static void __iomem *wdt_source = IO_ADDRESS(TEGRA_WDT0_BASE); static void tegra_wdt_reset_enable(void) { u32 val; writel(TIMER_PCR_INTR, wdt_timer + TIMER_PCR); val = (wdt_heartbeat * 1000000ul) / 4; val |= (TIMER_EN | TIMER_PERIODIC); writel(val, wdt_timer + TIMER_PTV); val = WDT_CFG_TMR_SRC | WDT_CFG_PERIOD | /*WDT_CFG_INT_EN |*/ /*WDT_CFG_SYS_RST_EN |*/ WDT_CFG_PMC2CAR_RST_EN; writel(val, wdt_source + WDT_CFG); writel(WDT_CMD_START_COUNTER, wdt_source + WDT_CMD);
void tegra_fiq_ack(unsigned int fiq) { void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x2000); readl_relaxed(base + GIC_CPU_INTACK); }
mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); mask |= (1 << irq); __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); } static struct irq_chip gemini_irq_chip = { .name = "INTC", .ack = gemini_ack_irq, .mask = gemini_mask_irq, .unmask = gemini_unmask_irq, }; static struct resource irq_resource = { .name = "irq_handler", .start = IO_ADDRESS(GEMINI_INTERRUPT_BASE), .end = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4, }; void __init gemini_init_irq(void) { unsigned int i, mode = 0, level = 0; /* * Disable arch_idle() by default since it is buggy * For more info see arch/arm/mach-gemini/include/mach/system.h */ disable_hlt(); request_resource(&iomem_resource, &irq_resource);
.flags = IORESOURCE_IRQ, }, }; struct platform_device imx_usb_device = { .name = "imx_udc", .id = 0, .num_resources = ARRAY_SIZE(imx_usb_resources), .resource = imx_usb_resources, }; /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { [0] = { .chip.label = "gpio-0", .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR), .irq = GPIO_INT_PORTA, .virtual_irq_start = MXC_GPIO_IRQ_START }, [1] = { .chip.label = "gpio-1", .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100), .irq = GPIO_INT_PORTB, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 }, [2] = { .chip.label = "gpio-2", .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200), .irq = GPIO_INT_PORTC, .virtual_irq_start = MXC_GPIO_IRQ_START + 64 },
static void gemini_ack_irq(unsigned int irq) { __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
static void __iomem *scu_base_addr(void) { return IO_ADDRESS(SCU_BASE_ADDR); }
void tegra_init_cache(bool init) { void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; u32 aux_ctrl; u32 speedo; u32 tmp; #ifdef CONFIG_TRUSTED_FOUNDATIONS /* issue the SMC to enable the L2 */ aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); tegra_cache_smc(true, aux_ctrl); /* after init, reread aux_ctrl and register handlers */ aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); l2x0_init(p, aux_ctrl, 0xFFFFFFFF); /* override outer_disable() with our disable */ outer_cache.disable = tegra_l2x0_disable; #else #if defined(CONFIG_ARCH_TEGRA_2x_SOC) writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); #elif defined(CONFIG_ARCH_TEGRA_3x_SOC) #ifdef CONFIG_TEGRA_SILICON_PLATFORM /* PL310 RAM latency is CPU dependent. NOTE: Changes here must also be reflected in __cortex_a9_l2x0_restart */ if (is_lp_cluster()) { writel(0x221, p + L2X0_TAG_LATENCY_CTRL); writel(0x221, p + L2X0_DATA_LATENCY_CTRL); } else { /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */ speedo = tegra_cpu_speedo_id(); if (speedo == 4 || speedo == 5 || speedo == 6 || speedo == 12 || speedo == 13) { writel(0x442, p + L2X0_TAG_LATENCY_CTRL); writel(0x552, p + L2X0_DATA_LATENCY_CTRL); } else { writel(0x441, p + L2X0_TAG_LATENCY_CTRL); writel(0x551, p + L2X0_DATA_LATENCY_CTRL); } } #else writel(0x770, p + L2X0_TAG_LATENCY_CTRL); writel(0x770, p + L2X0_DATA_LATENCY_CTRL); #endif #endif aux_ctrl = readl(p + L2X0_CACHE_TYPE); aux_ctrl = (aux_ctrl & 0x700) << (17-8); aux_ctrl |= 0x7C000001; if (init) { l2x0_init(p, aux_ctrl, 0x8200c3fe); } else { tmp = aux_ctrl; aux_ctrl = readl(p + L2X0_AUX_CTRL); aux_ctrl &= 0x8200c3fe; aux_ctrl |= tmp; writel(aux_ctrl, p + L2X0_AUX_CTRL); } l2x0_enable(); #endif }
#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/localtimer.h> #include <asm/tlbflush.h> #include <asm/smp_scu.h> #include <asm/cpu.h> #include <asm/mmu_context.h> #include <mach/iomap.h> #include "power.h" extern void tegra_secondary_startup(void); static DEFINE_SPINLOCK(boot_lock); static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); #ifdef CONFIG_HOTPLUG_CPU static DEFINE_PER_CPU(struct completion, cpu_killed); extern void tegra_hotplug_startup(void); #endif static DECLARE_BITMAP(cpu_init_bits, CONFIG_NR_CPUS) __read_mostly; const struct cpumask *const cpu_init_mask = to_cpumask(cpu_init_bits); #define cpu_init_map (*(cpumask_t *)cpu_init_mask) #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
void bcm476x_reset_system(void) { printk(KERN_INFO "Resetting the board...\n"); asm("cpsid aif"); /* disable FAULT/IRQ/FIQ */ /* * Unlock CMU so we can use BLOCK_RESETn registers. This is safer * as we're putting pretty much all hardware blocks into reset * state prior to watchdog reset getting fired after which we'll * re-enter Boot ROM. */ writel(0xbcbc4760, IO_ADDRESS(CMU_R_TRIGGER_UNLOCK_MEMADDR)); writel(readl(IO_ADDRESS(CMU_R_GLOBAL_RESET_CTL_MEMADDR)) & ~(CMU_F_SELECT_TRIGGER_RESETS_MASK | CMU_F_TRIGGER_RESETS_MASK), IO_ADDRESS(CMU_R_GLOBAL_RESET_CTL_MEMADDR)); /* * Most things in BLOCK_RESET2 are safe except for GPIO * blocks. Resetting those is not ok for A0 because it * resets the drive strength settings to the defaults which * are too weak. */ writel(readl(IO_ADDRESS(CMU_R_BLOCK_RESET2_MEMADDR)) & ~(CMU_BLK_SAFE_RESET2_MASK), IO_ADDRESS(CMU_R_BLOCK_RESET2_MEMADDR)); udelay(5); writel(readl(IO_ADDRESS(CMU_R_BLOCK_RESET2_MEMADDR)) | (CMU_BLK_SAFE_RESET2_MASK), IO_ADDRESS(CMU_R_BLOCK_RESET2_MEMADDR)); /* * This method uses the watchdog timer to generate the * reset. It still uses the BLOCK_RESETn registers to * reset most peripheral devices to a known state. */ /* * Need to be careful what we reset in BLOCK_RESET0. Some of the * peripheral resets in here will cause the system to fail. */ writel(readl(IO_ADDRESS(CMU_R_BLOCK_RESET0_MEMADDR)) & ~(CMU_BLK_SAFE_RESET0_MASK), IO_ADDRESS(CMU_R_BLOCK_RESET0_MEMADDR)); udelay(5); writel(readl(IO_ADDRESS(CMU_R_BLOCK_RESET0_MEMADDR)) | (CMU_BLK_SAFE_RESET0_MASK), IO_ADDRESS(CMU_R_BLOCK_RESET0_MEMADDR)); /* * Generally everything in BLOCK_RESET1 is safe. */ writel(readl(IO_ADDRESS(CMU_R_BLOCK_RESET1_MEMADDR)) & ~(CMU_BLK_SAFE_RESET1_MASK), IO_ADDRESS(CMU_R_BLOCK_RESET1_MEMADDR)); udelay(5); writel(readl(IO_ADDRESS(CMU_R_BLOCK_RESET1_MEMADDR)) | (CMU_BLK_SAFE_RESET1_MASK), IO_ADDRESS(CMU_R_BLOCK_RESET1_MEMADDR)); udelay(100); /* * Program watchdog timer to reset us in six 32Khz clocks. */ writel(0x1ACCE551, IO_ADDRESS(WDT_R_WDOGLOCK_MEMADDR)); udelay(1000); writel(readl(IO_ADDRESS(WDT_R_WDOGCONTROL_MEMADDR)) & ~(WDT_F_RESEN_MASK | WDT_F_PREEN_MASK | WDT_F_INTEN_MASK), IO_ADDRESS(WDT_R_WDOGCONTROL_MEMADDR)); udelay(1000); writel(3, IO_ADDRESS(WDT_R_WDOGLOAD_MEMADDR)); udelay(1000); writel(WDT_F_RESEN_MASK | WDT_F_INTEN_MASK, IO_ADDRESS(WDT_R_WDOGCONTROL_MEMADDR)); /* Loop here forever, until watchdog reset occurs. */ __asm("1: nop; b 1b"); /* We'll never get here because the reset will occur but... */ writel(0, IO_ADDRESS(CMU_R_TRIGGER_UNLOCK_MEMADDR)); }
void __init mx31_init_irq(void) { mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); }
static int __devinit cci_probe(struct platform_device *pdev) { struct cci_dev *cci = NULL; struct resource *res = NULL; struct cci_platform_data *pdata = NULL; int ret, irq = 0; pdata = pdev->dev.platform_data; if (pdata == NULL) { return -ENODEV; } vfe_print("cci probe start cci_sel = %d!\n",pdata->cci_sel); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (res == NULL || irq < 0) { return -ENODEV; } if (!request_mem_region(res->start, resource_size(res), res->name)) { return -ENOMEM; } cci = kzalloc(sizeof(struct cci_dev), GFP_KERNEL); if (!cci) { ret = -ENOMEM; goto ekzalloc; } cci->irq = irq; cci->cci_sel = pdata->cci_sel; spin_lock_init(&cci->slock); init_waitqueue_head(&cci->wait); #ifdef SUNXI_MEM cci->base = sunxi_map_kernel(res->start, resource_size(res)); #else cci->base = IO_ADDRESS(res->start); #endif if (!cci->base) { ret = -EIO; goto eremap; } ret = request_irq(irq, cci_irq_handler, IRQF_DISABLED, CCI_MODULE_NAME, cci); if (ret) { vfe_err("[cci_%d] requeset irq failed!\n", cci->cci_sel); goto ereqirq; } #if defined (CONFIG_ARCH_SUN9IW1P1) ret = bsp_csi_cci_set_base_addr(cci->cci_sel, (unsigned int)cci->base); if(ret < 0) goto ehwinit; #else ret = bsp_csi_cci_set_base_addr(0, (unsigned int)cci->base); if(ret < 0) goto ehwinit; ret = bsp_csi_cci_set_base_addr(1, (unsigned int)cci->base); if(ret < 0) goto ehwinit; #endif platform_set_drvdata(pdev, cci); vfe_print("cci probe end cci_sel = %d!\n",pdata->cci_sel); return 0; ehwinit: free_irq(irq, cci); ereqirq: iounmap(cci->base); eremap: kfree(cci); ekzalloc: vfe_print("cci probe err!\n"); return ret; }
for (i = 0; i < ARRAY_SIZE(mxci2c_devices); i++) { if (platform_device_register(&mxci2c_devices[i]) < 0) dev_err(&mxci2c_devices[i].dev, "Unable to register I2C device\n"); } } #else static inline void mxc_init_i2c(void) { } #endif struct mxc_gpio_port mxc_gpio_ports[] = { [0] = { .chip.label = "gpio-0", .base = IO_ADDRESS(GPIO1_BASE_ADDR), .irq = MXC_INT_GPIO1, .irq_high = 0, .virtual_irq_start = MXC_GPIO_IRQ_START, }, [1] = { .chip.label = "gpio-1", .base = IO_ADDRESS(GPIO2_BASE_ADDR), .irq = MXC_INT_GPIO2, .irq_high = 0, .virtual_irq_start = MXC_GPIO_IRQ_START + 32, }, [2] = { .chip.label = "gpio-2", .base = IO_ADDRESS(GPIO3_BASE_ADDR), .irq = MXC_INT_GPIO3,
#include "tegra2_emc.h" #define TEGRA_MRR_DIVLD (1<<20) #define TEGRA_EMC_STATUS 0x02b4 #define TEGRA_EMC_MRR 0x00ec static DEFINE_MUTEX(tegra_emc_mrr_lock); #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE static bool emc_enable = true; #else static bool emc_enable; #endif module_param(emc_enable, bool, 0644); static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE); static const struct tegra_emc_table *tegra_emc_table; static int tegra_emc_table_size; static unsigned long tegra_emc_max_bus_rate; /* 2 * 1000 * maximum emc_clock rate */ static unsigned long tegra_emc_min_bus_rate; /* 2 * 1000 * minimum emc_clock rate */ static inline void emc_writel(u32 val, unsigned long addr) { writel(val, emc + addr); } static inline u32 emc_readl(unsigned long addr) { return readl(emc + addr); }