int main()
{
printf("\nNOT 1: %d\n", NOT(1));
printf("NOT 0: %d\n", NOT(0));
printf("\n1 AND 1: %d\n", AND(1, 1));
printf("1 AND 0: %d\n", AND(1, 0));
printf("0 AND 1: %d\n", AND(0, 1));
printf("0 AND 0: %d\n", AND(0, 0));
printf("\n1 OR 1: %d\n", OR(1, 1));
printf("1 OR 0: %d\n", OR(1, 0));
printf("0 OR 1: %d\n", OR(0, 1));
printf("0 OR 0: %d\n", OR(0, 0));
printf("\n1 NOR 1: %d\n", NOR(1, 1));
printf("1 NOR 0: %d\n", NOR(1, 0));
printf("0 NOR 1: %d\n", NOR(0, 1));
printf("0 NOR 0: %d\n", NOR(0, 0));
printf("\n1 NAND 1: %d\n", NAND(1, 1));
printf("1 NAND 0: %d\n", NAND(1, 0));
printf("0 NAND 1: %d\n", NAND(0, 1));
printf("0 NAND 0: %d\n", NAND(0, 0));
printf("\n1 XOR 1: %d\n", XOR(1, 1));
printf("1 XOR 0: %d\n", XOR(1, 0));
printf("0 XOR 1: %d\n", XOR(0, 1));
printf("0 XOR 0: %d\n", XOR(0, 0));
printf("\n1 HALFSUM 1: %d\n", HALFSUM(1, 1));
printf("1 HALFSUM 0: %d\n", HALFSUM(1, 0));
printf("0 HALFSUM 1: %d\n", HALFSUM(0, 1));
printf("0 HALFSUM 0: %d\n", HALFSUM(0, 0));
printf("\n1 HALFCARRY 1: %d\n", HALFCARRY(1, 1));
printf("1 HALFCARRY 0: %d\n", HALFCARRY(1, 0));
printf("0 HALFCARRY 1: %d\n", HALFCARRY(0, 1));
printf("0 HALFCARRY 0: %d\n", HALFCARRY(0, 0));
printf("\n1 FULLSUM 1 CARRY 1: %d\n", FULLSUM(1, 1, 1));
printf("1 FULLSUM 1 CARRY 0: %d\n", FULLSUM(1, 1, 0));
printf("1 FULLSUM 0 CARRY 1: %d\n", FULLSUM(1, 0, 1));
printf("1 FULLSUM 0 CARRY 0: %d\n", FULLSUM(1, 0, 0));
printf("0 FULLSUM 1 CARRY 1: %d\n", FULLSUM(0, 1, 1));
printf("0 FULLSUM 1 CARRY 0: %d\n", FULLSUM(0, 1, 0));
printf("0 FULLSUM 0 CARRY 1: %d\n", FULLSUM(0, 0, 1));
printf("0 FULLSUM 0 CARRY 0: %d\n", FULLSUM(0, 0, 0));
printf("\n1 FULLCARRY 1 CARRY 1: %d\n", FULLCARRY(1, 1, 1));
printf("1 FULLCARRY 1 CARRY 0: %d\n", FULLCARRY(1, 1, 0));
printf("1 FULLCARRY 0 CARRY 1: %d\n", FULLCARRY(1, 0, 1));
printf("1 FULLCARRY 0 CARRY 0: %d\n", FULLCARRY(1, 0, 0));
printf("0 FULLCARRY 1 CARRY 1: %d\n", FULLCARRY(0, 1, 1));
printf("0 FULLCARRY 1 CARRY 0: %d\n", FULLCARRY(0, 1, 0));
printf("0 FULLCARRY 0 CARRY 1: %d\n", FULLCARRY(0, 0, 1));
printf("0 FULLCARRY 0 CARRY 0: %d\n", FULLCARRY(0, 0, 0));
}
int sc_main(int, char **)
{
sc_signal<bool> a, b, f;
sc_clock clk("Clk", 20, SC_NS); // 时钟周期为 20ns
// 分别定义模块 NAND 和 TB 的实例，并通过局部变量（如 a、b）将这两个实例连接起来
nand NAND("NAND");
NAND.A(a);
NAND.B(b);
NAND.F(f);
tb TB("TB");
TB.clk(clk);
TB.a(a);
TB.b(b);
TB.f(f);
// 生成仿真结果波形文件
sc_trace_file *tf = sc_create_vcd_trace_file("NAND");
sc_trace(tf, NAND.A, "A");
sc_trace(tf, NAND.B, "B");
sc_trace(tf, NAND.F, "F");
sc_trace(tf, TB.clk, "CLK");
sc_start(200, SC_NS); // 仿真时长 200ns
sc_close_vcd_trace_file(tf);
return 0;
}
static int nand_post_load(void *opaque, int version_id)
{
NANDFlashState *s = NAND(opaque);
if (s->ioaddr_vmstate > sizeof(s->io)) {
return -EINVAL;
}
s->ioaddr = s->io + s->ioaddr_vmstate;
return 0;
}
static void nand_reset(DeviceState *dev)
{
NANDFlashState *s = NAND(dev);
s->cmd = NAND_CMD_READ0;
s->addr = 0;
s->addrlen = 0;
s->iolen = 0;
s->offset = 0;
s->status &= NAND_IOSTATUS_UNPROTCT;
s->status |= NAND_IOSTATUS_READY;
}
static void nand_realize(DeviceState *dev, Error **errp)
{
int pagesize;
NANDFlashState *s = NAND(dev);
s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
s->size = nand_flash_ids[s->chip_id].size << 20;
if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
s->page_shift = 11;
s->erase_shift = 6;
} else {
s->page_shift = nand_flash_ids[s->chip_id].page_shift;
s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
}
switch (1 << s->page_shift) {
case 256:
nand_init_256(s);
break;
case 512:
nand_init_512(s);
break;
case 2048:
nand_init_2048(s);
break;
default:
error_setg(errp, "Unsupported NAND block size %#x\n",
1 << s->page_shift);
return;
}
pagesize = 1 << s->oob_shift;
s->mem_oob = 1;
if (s->bdrv) {
if (bdrv_is_read_only(s->bdrv)) {
error_setg(errp, "Can't use a read-only drive");
return;
}
if (bdrv_getlength(s->bdrv) >=
(s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
pagesize = 0;
s->mem_oob = 0;
}
} else {
pagesize += 1 << s->page_shift;
}
if (pagesize) {
s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
0xff, s->pages * pagesize);
}
/* Give s->ioaddr a sane value in case we save state before it is used. */
s->ioaddr = s->io;
}
int main(){
int i,j;
for(i=0;i<2;i++){
for(j=0;j<2;j++){
printf("%d AND %d = %d\n",i,j,AND(i,j));
}
}
printf("\n");
for(i=0;i<2;i++){
for(j=0;j<2;j++){
printf("%d OR %d = %d\n",i,j,OR(i,j));
}
}
printf("\n");
for(i=0;i<2;i++){
printf("%d NOT = %d\n",i,NOT(i));
}
printf("\n");
for(i=0;i<2;i++){
for(j=0;j<2;j++){
printf("%d NAND %d = %d\n",i,j,NAND(i,j));
}
}
printf("\n");
for(i=0;i<2;i++){
for(j=0;j<2;j++){
printf("%d NOR %d = %d\n",i,j,NOR(i,j));
}
}
printf("\n");
for(i=0;i<2;i++){
for(j=0;j<2;j++){
printf("%d XOR %d = %d\n",i,j,XOR(i,j));
}
}
printf("\n");
for(i=0;i<2;i++){
for(j=0;j<2;j++){
printf("%d XNOR %d = %d\n",i,j,XNOR(i,j));
}
}
printf("\n");
return 0;
}
/*
* Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins. Chip
* outputs are R/B and eight I/O pins.
*
* CE, WP and R/B are active low.
*/
void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
uint8_t ce, uint8_t wp, uint8_t gnd)
{
NANDFlashState *s = NAND(dev);
s->cle = cle;
s->ale = ale;
s->ce = ce;
s->wp = wp;
s->gnd = gnd;
if (wp) {
s->status |= NAND_IOSTATUS_UNPROTCT;
} else {
s->status &= ~NAND_IOSTATUS_UNPROTCT;
}
}
/* Process 3OP Integer instructions */
bool eval_3OP_Int(struct lilith* vm, struct Instruction* c)
{
#ifdef DEBUG
char Name[20] = "ILLEGAL_3OP";
#endif
switch(c->raw_XOP)
{
case 0x000: /* ADD */
{
#ifdef DEBUG
strncpy(Name, "ADD", 19);
#elif TRACE
record_trace("ADD");
#endif
ADD(vm, c);
break;
}
case 0x001: /* ADDU */
{
#ifdef DEBUG
strncpy(Name, "ADDU", 19);
#elif TRACE
record_trace("ADDU");
#endif
ADDU(vm, c);
break;
}
case 0x002: /* SUB */
{
#ifdef DEBUG
strncpy(Name, "SUB", 19);
#elif TRACE
record_trace("SUB");
#endif
SUB(vm, c);
break;
}
case 0x003: /* SUBU */
{
#ifdef DEBUG
strncpy(Name, "SUBU", 19);
#elif TRACE
record_trace("SUBU");
#endif
SUBU(vm, c);
break;
}
case 0x004: /* CMP */
{
#ifdef DEBUG
strncpy(Name, "CMP", 19);
#elif TRACE
record_trace("CMP");
#endif
CMP(vm, c);
break;
}
case 0x005: /* CMPU */
{
#ifdef DEBUG
strncpy(Name, "CMPU", 19);
#elif TRACE
record_trace("CMPU");
#endif
CMPU(vm, c);
break;
}
case 0x006: /* MUL */
{
#ifdef DEBUG
strncpy(Name, "MUL", 19);
#elif TRACE
record_trace("MUL");
#endif
MUL(vm, c);
break;
}
case 0x007: /* MULH */
{
#ifdef DEBUG
strncpy(Name, "MULH", 19);
#elif TRACE
record_trace("MULH");
#endif
MULH(vm, c);
break;
}
case 0x008: /* MULU */
{
#ifdef DEBUG
strncpy(Name, "MULU", 19);
#elif TRACE
record_trace("MULU");
#endif
MULU(vm, c);
break;
}
case 0x009: /* MULUH */
{
#ifdef DEBUG
strncpy(Name, "MULUH", 19);
#elif TRACE
record_trace("MULUH");
#endif
MULUH(vm, c);
break;
}
case 0x00A: /* DIV */
{
#ifdef DEBUG
strncpy(Name, "DIV", 19);
#elif TRACE
record_trace("DIV");
#endif
DIV(vm, c);
break;
}
case 0x00B: /* MOD */
{
#ifdef DEBUG
strncpy(Name, "MOD", 19);
#elif TRACE
record_trace("MOD");
#endif
MOD(vm, c);
break;
}
case 0x00C: /* DIVU */
{
#ifdef DEBUG
strncpy(Name, "DIVU", 19);
#elif TRACE
record_trace("DIVU");
#endif
DIVU(vm, c);
break;
}
case 0x00D: /* MODU */
{
#ifdef DEBUG
strncpy(Name, "MODU", 19);
#elif TRACE
record_trace("MODU");
#endif
MODU(vm, c);
break;
}
case 0x010: /* MAX */
{
#ifdef DEBUG
strncpy(Name, "MAX", 19);
#elif TRACE
record_trace("MAX");
#endif
MAX(vm, c);
break;
}
case 0x011: /* MAXU */
{
#ifdef DEBUG
strncpy(Name, "MAXU", 19);
#elif TRACE
record_trace("MAXU");
#endif
MAXU(vm, c);
break;
}
case 0x012: /* MIN */
{
#ifdef DEBUG
strncpy(Name, "MIN", 19);
#elif TRACE
record_trace("MIN");
#endif
MIN(vm, c);
break;
}
case 0x013: /* MINU */
{
#ifdef DEBUG
strncpy(Name, "MINU", 19);
#elif TRACE
record_trace("MINU");
#endif
MINU(vm, c);
break;
}
case 0x014: /* PACK */
case 0x015: /* UNPACK */
case 0x016: /* PACK8.CO */
case 0x017: /* PACK8U.CO */
case 0x018: /* PACK16.CO */
case 0x019: /* PACK16U.CO */
case 0x01A: /* PACK32.CO */
case 0x01B: /* PACK32U.CO */
{
illegal_instruction(vm, c);
break;
}
case 0x020: /* AND */
{
#ifdef DEBUG
strncpy(Name, "AND", 19);
#elif TRACE
record_trace("AND");
#endif
AND(vm, c);
break;
}
case 0x021: /* OR */
{
#ifdef DEBUG
strncpy(Name, "OR", 19);
#elif TRACE
record_trace("OR");
#endif
OR(vm, c);
break;
}
case 0x022: /* XOR */
{
#ifdef DEBUG
strncpy(Name, "XOR", 19);
#elif TRACE
record_trace("XOR");
#endif
XOR(vm, c);
break;
}
case 0x023: /* NAND */
{
#ifdef DEBUG
strncpy(Name, "NAND", 19);
#elif TRACE
record_trace("NAND");
#endif
NAND(vm, c);
break;
}
case 0x024: /* NOR */
{
#ifdef DEBUG
strncpy(Name, "NOR", 19);
#elif TRACE
record_trace("NOR");
#endif
NOR(vm, c);
break;
}
case 0x025: /* XNOR */
{
#ifdef DEBUG
strncpy(Name, "XNOR", 19);
#elif TRACE
record_trace("XNOR");
#endif
XNOR(vm, c);
break;
}
case 0x026: /* MPQ */
{
#ifdef DEBUG
strncpy(Name, "MPQ", 19);
#elif TRACE
record_trace("MPQ");
#endif
MPQ(vm, c);
break;
}
case 0x027: /* LPQ */
{
#ifdef DEBUG
strncpy(Name, "LPQ", 19);
#elif TRACE
record_trace("LPQ");
#endif
LPQ(vm, c);
break;
}
case 0x028: /* CPQ */
{
#ifdef DEBUG
strncpy(Name, "CPQ", 19);
#elif TRACE
record_trace("CPQ");
#endif
CPQ(vm, c);
break;
}
case 0x029: /* BPQ */
{
#ifdef DEBUG
strncpy(Name, "BPQ", 19);
#elif TRACE
record_trace("BPQ");
#endif
BPQ(vm, c);
break;
}
case 0x030: /* SAL */
{
#ifdef DEBUG
strncpy(Name, "SAL", 19);
#elif TRACE
record_trace("SAL");
#endif
SAL(vm, c);
break;
}
case 0x031: /* SAR */
{
#ifdef DEBUG
strncpy(Name, "SAR", 19);
#elif TRACE
record_trace("SAR");
#endif
SAR(vm, c);
break;
}
case 0x032: /* SL0 */
{
#ifdef DEBUG
strncpy(Name, "SL0", 19);
#elif TRACE
record_trace("SL0");
#endif
SL0(vm, c);
break;
}
case 0x033: /* SR0 */
{
#ifdef DEBUG
strncpy(Name, "SR0", 19);
#elif TRACE
record_trace("SR0");
#endif
SR0(vm, c);
break;
}
case 0x034: /* SL1 */
{
#ifdef DEBUG
strncpy(Name, "SL1", 19);
#elif TRACE
record_trace("SL1");
#endif
SL1(vm, c);
break;
}
case 0x035: /* SR1 */
{
#ifdef DEBUG
strncpy(Name, "SR1", 19);
#elif TRACE
record_trace("SR1");
#endif
SR1(vm, c);
break;
}
case 0x036: /* ROL */
{
#ifdef DEBUG
strncpy(Name, "ROL", 19);
#elif TRACE
record_trace("ROL");
#endif
ROL(vm, c);
break;
}
case 0x037: /* ROR */
{
#ifdef DEBUG
strncpy(Name, "ROR", 19);
#elif TRACE
record_trace("ROR");
#endif
ROR(vm, c);
break;
}
case 0x038: /* LOADX */
{
#ifdef DEBUG
strncpy(Name, "LOADX", 19);
#elif TRACE
record_trace("LOADX");
#endif
LOADX(vm, c);
break;
}
case 0x039: /* LOADX8 */
{
#ifdef DEBUG
strncpy(Name, "LOADX8", 19);
#elif TRACE
record_trace("LOADX8");
#endif
LOADX8(vm, c);
break;
}
case 0x03A: /* LOADXU8 */
{
#ifdef DEBUG
strncpy(Name, "LOADXU8", 19);
#elif TRACE
record_trace("LOADXU8");
#endif
LOADXU8(vm, c);
break;
}
case 0x03B: /* LOADX16 */
{
#ifdef DEBUG
strncpy(Name, "LOADX16", 19);
#elif TRACE
record_trace("LOADX16");
#endif
LOADX16(vm, c);
break;
}
case 0x03C: /* LOADXU16 */
{
#ifdef DEBUG
strncpy(Name, "LOADXU16", 19);
#elif TRACE
record_trace("LOADXU16");
#endif
LOADXU16(vm, c);
break;
}
case 0x03D: /* LOADX32 */
{
#ifdef DEBUG
strncpy(Name, "LOADX32", 19);
#elif TRACE
record_trace("LOADX32");
#endif
LOADX32(vm, c);
break;
}
case 0x03E: /* LOADXU32 */
{
#ifdef DEBUG
strncpy(Name, "LOADXU32", 19);
#elif TRACE
record_trace("LOADXU32");
#endif
LOADXU32(vm, c);
break;
}
case 0x048: /* STOREX */
{
#ifdef DEBUG
strncpy(Name, "STOREX", 19);
#elif TRACE
record_trace("STOREX");
#endif
STOREX(vm, c);
break;
}
case 0x049: /* STOREX8 */
{
#ifdef DEBUG
strncpy(Name, "STOREX8", 19);
#elif TRACE
record_trace("STOREX8");
#endif
STOREX8(vm, c);
break;
}
case 0x04A: /* STOREX16 */
{
#ifdef DEBUG
strncpy(Name, "STOREX16", 19);
#elif TRACE
record_trace("STOREX16");
#endif
STOREX16(vm, c);
break;
}
case 0x04B: /* STOREX32 */
{
#ifdef DEBUG
strncpy(Name, "STOREX32", 19);
#elif TRACE
record_trace("STOREX32");
#endif
STOREX32(vm, c);
break;
}
case 0x050: /* CMPJUMP.G */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMP.G", 19);
#elif TRACE
record_trace("CMPJUMP.G");
#endif
CMPJUMP_G(vm, c);
break;
}
case 0x051: /* CMPJUMP.GE */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMP.GE", 19);
#elif TRACE
record_trace("CMPJUMP.GE");
#endif
CMPJUMP_GE(vm, c);
break;
}
case 0x052: /* CMPJUMP.E */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMP.E", 19);
#elif TRACE
record_trace("CMPJUMP.E");
#endif
CMPJUMP_E(vm, c);
break;
}
case 0x053: /* CMPJUMP.NE */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMP.NE", 19);
#elif TRACE
record_trace("CMPJUMP.NE");
#endif
CMPJUMP_NE(vm, c);
break;
}
case 0x054: /* CMPJUMP.LE */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMP.LE", 19);
#elif TRACE
record_trace("CMPJUMP.LE");
#endif
CMPJUMP_LE(vm, c);
break;
}
case 0x055: /* CMPJUMP.L */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMP.L", 19);
#elif TRACE
record_trace("CMPJUMP.L");
#endif
CMPJUMP_L(vm, c);
break;
}
case 0x060: /* CMPJUMPU.G */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMPU.G", 19);
#elif TRACE
record_trace("CMPJUMPU.G");
#endif
CMPJUMPU_G(vm, c);
break;
}
case 0x061: /* CMPJUMPU.GE */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMPU.GE", 19);
#elif TRACE
record_trace("CMPJUMPU.GE");
#endif
CMPJUMPU_GE(vm, c);
break;
}
case 0x064: /* CMPJUMPU.LE */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMPU.LE", 19);
#elif TRACE
record_trace("CMPJUMPU.LE");
#endif
CMPJUMPU_LE(vm, c);
break;
}
case 0x065: /* CMPJUMPU.L */
{
#ifdef DEBUG
strncpy(Name, "CMPJUMPU.L", 19);
#elif TRACE
record_trace("CMPJUMPU.L");
#endif
CMPJUMPU_L(vm, c);
break;
}
default:
{
illegal_instruction(vm, c);
break;
}
}
#ifdef DEBUG
fprintf(stdout, "# %s reg%u reg%u reg%u\n", Name, c->reg0, c->reg1, c->reg2);
#endif
return false;
}
void nand_setio(DeviceState *dev, uint32_t value)
{
int i;
NANDFlashState *s = NAND(dev);
if (!s->ce && s->cle) {
if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
if (s->cmd == NAND_CMD_READ0
&& (value == NAND_CMD_LPREAD2
|| value == NAND_CMD_READCACHESTART
|| value == NAND_CMD_READCACHELAST))
return;
if (value == NAND_CMD_RANDOMREAD1) {
s->addr &= ~((1 << s->addr_shift) - 1);
s->addrlen = 0;
return;
}
}
if (value == NAND_CMD_READ0) {
s->offset = 0;
} else if (value == NAND_CMD_READ1) {
s->offset = 0x100;
value = NAND_CMD_READ0;
} else if (value == NAND_CMD_READ2) {
s->offset = 1 << s->page_shift;
value = NAND_CMD_READ0;
}
s->cmd = value;
if (s->cmd == NAND_CMD_READSTATUS ||
s->cmd == NAND_CMD_PAGEPROGRAM2 ||
s->cmd == NAND_CMD_BLOCKERASE1 ||
s->cmd == NAND_CMD_BLOCKERASE2 ||
s->cmd == NAND_CMD_NOSERIALREAD2 ||
s->cmd == NAND_CMD_RANDOMREAD2 ||
s->cmd == NAND_CMD_RESET ||
s->cmd == NAND_CMD_READCACHEEXIT) {
nand_command(s);
}
if (s->cmd != NAND_CMD_RANDOMREAD2) {
s->addrlen = 0;
}
}
if (s->ale) {
unsigned int shift = s->addrlen * 8;
unsigned int mask = ~(0xff << shift);
unsigned int v = value << shift;
s->addr = (s->addr & mask) | v;
s->addrlen ++;
switch (s->addrlen) {
case 1:
if (s->cmd == NAND_CMD_READID) {
nand_command(s);
}
break;
case 2: /* fix cache address as a byte address */
s->addr <<= (s->buswidth - 1);
break;
case 3:
if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
(s->cmd == NAND_CMD_READ0 ||
s->cmd == NAND_CMD_PAGEPROGRAM1)) {
nand_command(s);
}
break;
case 4:
if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
(s->cmd == NAND_CMD_READ0 ||
s->cmd == NAND_CMD_PAGEPROGRAM1)) {
nand_command(s);
}
break;
case 5:
if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
(s->cmd == NAND_CMD_READ0 ||
s->cmd == NAND_CMD_PAGEPROGRAM1)) {
nand_command(s);
}
break;
default:
break;
}
}
if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
for (i = s->buswidth; i--; value >>= 8) {
s->io[s->iolen ++] = (uint8_t) (value & 0xff);
}
}
} else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
static void nand_pre_save(void *opaque)
{
NANDFlashState *s = NAND(opaque);
s->ioaddr_vmstate = s->ioaddr - s->io;
}