NTSTATUS NTAPI HwReset(PCONTROLLER_INFO ControllerInfo) /* * FUNCTION: Reset the controller * ARGUMENTS: * ControllerInfo: controller to reset * RETURNS: * STATUS_SUCCESS in all cases * NOTES: * - Generates an interrupt that must be serviced four times (one per drive) */ { TRACE_(FLOPPY, "HwReset called\n"); /* Write the reset bit in the DRSR */ WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DATA_RATE_SELECT_REGISTER, DRSR_SW_RESET); /* Check for the reset bit in the DOR and set it if necessary (see Intel doc) */ if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET)) { HwDumpRegisters(ControllerInfo); INFO_(FLOPPY, "HwReset: Setting Enable bit\n"); WRITE_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER, DOR_DMA_IO_INTERFACE_ENABLE|DOR_RESET); HwDumpRegisters(ControllerInfo); if(!(READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER) & DOR_RESET)) { WARN_(FLOPPY, "HwReset: failed to set the DOR enable bit!\n"); HwDumpRegisters(ControllerInfo); return STATUS_UNSUCCESSFUL; } } return STATUS_SUCCESS; }
VOID ClearKbdFifo( ) /*++ Routine Description: This routine empties the Keyboard controller Fifo. Arguments: None. Return Value: None. --*/ { UCHAR Trash, Stat; volatile Timeout; // // wait until the previous command is processed. // while ((READ_PORT_UCHAR((PUCHAR)&KEYBOARD_READ->Status) & KBD_IBF_MASK) != 0) { } while ((READ_PORT_UCHAR((PUCHAR)&KEYBOARD_READ->Status) & KBD_OBF_MASK) != 0) { Trash= READ_PORT_UCHAR((PUCHAR)&KEYBOARD_READ->Data); for (Timeout=0;Timeout<10000;Timeout++) { } } }
void dc_dbg_init() { #ifdef DBG_COM u32 divisor; u8 lcr; /* set baud rate and data format (8N1) */ /* turn on DTR and RTS */ WRITE_PORT_UCHAR(pv(SER_MCR(COM_BASE)), SR_MCR_DTR | SR_MCR_RTS); /* set DLAB */ lcr = READ_PORT_UCHAR(pv(SER_LCR(COM_BASE))) | SR_LCR_DLAB; WRITE_PORT_UCHAR(pv(SER_LCR(COM_BASE)), lcr); /* set baud rate */ divisor = 115200 / DEFAULT_BAUD_RATE; WRITE_PORT_UCHAR(pv(SER_DLL(COM_BASE)), divisor & 0xff); WRITE_PORT_UCHAR(pv(SER_DLM(COM_BASE)), (divisor >> 8) & 0xff); /* reset DLAB and set 8N1 format */ WRITE_PORT_UCHAR(pv(SER_LCR(COM_BASE)), SR_LCR_CS8 | SR_LCR_ST1 | SR_LCR_PNO); /* read junk out of the RBR */ READ_PORT_UCHAR(pv(SER_RBR(COM_BASE))); #endif /* DBG_COM */ #ifdef DBG_HAL_DISPLAY InbvAcquireDisplayOwnership(); InbvEnableDisplayString(TRUE); #endif /* DBG_HAL_DISPLAY */ }
NTSTATUS W98Ports_ParallelSetChipMode (IN PDEVICE_OBJECT DeviceObject, IN PPARALLEL_CHIP_MODE ChipMode) { #define CONTROL_FORWARD 0x04 #define CONTROL_REVERSE 0x24 PDEVICE_EXTENSION DeviceExtension; PUCHAR ECR; PUCHAR DCR; PUCHAR DR; UCHAR Data; PAGED_CODE (); /* First check that we know the mode requested. Anything else is an error */ if (!( (ChipMode->ModeFlags==ECR_SPP_MODE) || (ChipMode->ModeFlags==ECR_BYTE_PIO_MODE) )) return STATUS_INVALID_DEVICE_STATE; /* Get a pointer to device data */ DeviceExtension= (PDEVICE_EXTENSION) DeviceObject->DeviceExtension; if (DeviceExtension->BaseAddress!=0x3BC) { ECR= (PUCHAR) DeviceExtension->BaseAddress+ECR_OFFSET; PPJOY_DBGPRINT (FILE_IOCTL|PPJOY_FENTRY, ("W98Ports_ParallelSetChipMode: Set ECR register 0x%x to 0x%x)",ECR,ChipMode->ModeFlags) ); WRITE_PORT_UCHAR (ECR,ChipMode->ModeFlags); } /* Set reverse mode if ChipMode is bidirectional, else set forward mode */ DCR= (PUCHAR) DeviceExtension->BaseAddress+DCR_OFFSET; if (ChipMode->ModeFlags) { WRITE_PORT_UCHAR (DCR,CONTROL_REVERSE); DR= (PUCHAR) DeviceExtension->BaseAddress; /* Now test that reverse mode works. */ WRITE_PORT_UCHAR (DR,0xA5); Data= READ_PORT_UCHAR (DR); if (Data==0xA5) { /* Hmm, first time we got same data, try again with new value */ WRITE_PORT_UCHAR (DR,0x5A); Data= READ_PORT_UCHAR (DR); if (Data==0x5A) { /* Same data again. This is too much... assume port is not bidirectional */ return STATUS_INVALID_DEVICE_STATE; } } } else { WRITE_PORT_UCHAR (DCR,CONTROL_FORWARD); } return STATUS_SUCCESS; }
/*! \brief Determine the type of cable (XA1541/XM1541) on the IEC bus This function tries to determine the type of cable with which the IEC bus is connected to the PC's parallel port. Afterwards, some variables in the device extension are initialized to reflect the type. \param Pdx Pointer to the device extension. \return If the routine succeeds, it returns STATUS_SUCCESS. Otherwise, it returns one of the error status values. \todo Do a more sophisticated test */ static NTSTATUS cbmiec_testcable(PDEVICE_EXTENSION Pdx) { const wchar_t *msgAuto = L""; const wchar_t *msgCable; UCHAR in, out; FUNC_ENTER(); /*! \todo Do a more sophisticated test for the cable */ switch (Pdx->IecCable) { case IEC_CABLETYPE_XM: /* FALL THROUGH */ case IEC_CABLETYPE_XA: break; default: in = CBMIEC_GET(PP_ATN_IN); out = (READ_PORT_UCHAR(OUT_PORT) & PP_ATN_OUT) ? 1 : 0; Pdx->IecCable = (in != out) ? IEC_CABLETYPE_XA : IEC_CABLETYPE_XM; msgAuto = L" (auto)"; break; } switch (Pdx->IecCable) { case IEC_CABLETYPE_XM: msgCable = L"passive (XM1541)"; break; case IEC_CABLETYPE_XA: msgCable = L"active (XA1541)"; break; } Pdx->IecOutEor = Pdx->IecCable ? 0xcb : 0xc4; DBG_SUCCESS((DBG_PREFIX "using %ws cable%ws", Pdx->IecCable ? L"active (XA1541)" : L"passive (XM1541)", msgAuto)); LogErrorString(Pdx->Fdo, CBM_IEC_INIT, msgCable, msgAuto); Pdx->IecOutBits = (READ_PORT_UCHAR(OUT_PORT) ^ Pdx->IecOutEor) & (PP_DATA_OUT|PP_CLK_OUT|PP_ATN_OUT|PP_RESET_OUT); /* if (Pdx->IecOutBits & PP_RESET_OUT) { cbmiec_reset(Pdx); } */ FUNC_LEAVE_NTSTATUS_CONST(STATUS_SUCCESS); }
static BOOL KbdpResetIndicator(void) { UCHAR status; do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 ); WRITE_PORT_UCHAR((PUCHAR)0x60, 0xed); do { status = READ_PORT_UCHAR((PUCHAR)0x64); } while( status & 0x02 ); WRITE_PORT_UCHAR((PUCHAR)0x60, m_KbdData.indicator_status); return 0; }
static BOOL FddpReadFdcData(BYTE *pData) { UCHAR status; do { status = READ_PORT_UCHAR((PUCHAR)FDD_STATUS_PORT); } while( !(status & 0x80) ); *pData = READ_PORT_UCHAR((PUCHAR)FDD_DATA_PORT); return TRUE; }
VOID SerialInterruptRequest ( PUCHAR PortAddress ) /*++ Routine Description: This routine generates an interrupt on the interrupt line for com port. Arguments: PortAddress - the port address of the desired com port. Return Value: None. --*/ { USHORT i; UCHAR Temp; WRITE_PORT_UCHAR( PortAddress + MODEM_CONTROL_REGISTER, 8 ); WRITE_PORT_UCHAR( PortAddress + INTERRUPT_ENABLE_REGISTER, 0 ); WRITE_PORT_UCHAR( PortAddress + INTERRUPT_ENABLE_REGISTER, 0xf ); // // Add some delay // for (i = 0; i < 5 ; i++ ) { Temp = READ_PORT_UCHAR((PUCHAR) PIC1_PORT1); Temp = READ_PORT_UCHAR((PUCHAR) PIC2_PORT1); } }
/* NSC/Cyrix CPU indexed register access macros */ static __inline UCHAR getCx86(UCHAR reg) { WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22, reg); return READ_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23); }
/***************************************************************************** * TryMPU() ***************************************************************************** * See if the MPU401 is free. */ BOOLEAN TryMPU ( IN PUCHAR PortBase ) { BOOLEAN success; USHORT numPolls; UCHAR status; _DbgPrintF(DEBUGLVL_BLAB, ("TryMPU")); numPolls = 0; while (numPolls < kMPUPollTimeout) { status = READ_PORT_UCHAR(PortBase + MPU401_REG_STATUS); if (UartFifoOkForWrite(status)) // Is this a good time to write data? { break; } numPolls++; } if (numPolls >= kMPUPollTimeout) { success = FALSE; _DbgPrintF(DEBUGLVL_BLAB, ("TryMPU failed")); } else { success = TRUE; } return success; }
UCHAR NTAPI VideoPortReadPortUchar( PUCHAR Port) { return READ_PORT_UCHAR(Port); }
BOOLEAN SendKbdCommand( IN UCHAR Command ) /*++ Routine Description: This routine polls the Status Register until the controller is ready to accept a command or timeout, then it send the Command. Arguments: None. Return Value: TRUE if timeout, FALSE if OK; --*/ { ULONG i; for (i=0; i <KBD_TIMEOUT; i++) { if ((READ_PORT_UCHAR((PUCHAR)&KEYBOARD_READ->Status) & KBD_IBF_MASK) == 0) { WRITE_PORT_UCHAR((PUCHAR)&KEYBOARD_WRITE->Command,Command); return FALSE; } } return TRUE; }
NTSTATUS DumpInitialize( VOID ) { UCHAR Version; NTSTATUS status; Version = READ_PORT_UCHAR(PortEB); if (Version != DUMP_VERSION) goto done; KeInitializeCallbackRecord(&DumpBugCheckReasonCallbackRecord); status = STATUS_UNSUCCESSFUL; if (!KeRegisterBugCheckReasonCallback(&DumpBugCheckReasonCallbackRecord, DumpBugCheckReasonCallback, KbCallbackDumpIo, (PUCHAR)__MODULE__)) goto fail1; Info("callback registered\n"); done: return STATUS_SUCCESS; fail1: Error("fail1 (%08x)\n", status); return status; }
ACPI_STATUS AcpiOsReadPort ( ACPI_IO_ADDRESS Address, UINT32 *Value, UINT32 Width) { DPRINT("AcpiOsReadPort %p, width %d\n",Address,Width); switch (Width) { case 8: *Value = READ_PORT_UCHAR((PUCHAR)Address); break; case 16: *Value = READ_PORT_USHORT((PUSHORT)Address); break; case 32: *Value = READ_PORT_ULONG((PULONG)Address); break; default: DPRINT1("AcpiOsReadPort got bad width: %d\n",Width); return (AE_BAD_PARAMETER); break; } return (AE_OK); }
static inline UCHAR ReadData(PUCHAR ReadDataPort) { return READ_PORT_UCHAR(ReadDataPort); }
/* * @implemented */ VOID NTAPI HalHandleNMI(IN PVOID NmiInfo) { UCHAR ucStatus; /* Get the NMI Flag */ ucStatus = READ_PORT_UCHAR((PUCHAR)0x61); /* Display NMI failure string */ HalDisplayString ("\n*** Hardware Malfunction\n\n"); HalDisplayString ("Call your hardware vendor for support\n\n"); /* Check for parity error */ if (ucStatus & 0x80) { /* Display message */ HalDisplayString ("NMI: Parity Check / Memory Parity Error\n"); } /* Check for I/O failure */ if (ucStatus & 0x40) { /* Display message */ HalDisplayString ("NMI: Channel Check / IOCHK\n"); } /* Halt the system */ HalDisplayString("\n*** The system has halted ***\n"); //KeEnterKernelDebugger(); }
void sound(int freq) { int scale; if (freq == 0) { WRITE_PORT_UCHAR((PUCHAR)0x61, READ_PORT_UCHAR((PUCHAR)0x61) & ~3); return; } scale = 1193046 / freq; WRITE_PORT_UCHAR((PUCHAR)0x43, 0xb6); WRITE_PORT_UCHAR((PUCHAR)0x42, scale & 0xff); WRITE_PORT_UCHAR((PUCHAR)0x42, scale >> 8); WRITE_PORT_UCHAR((PUCHAR)0x61, READ_PORT_UCHAR((PUCHAR)0x61) | 3); }
VOID PutLedDisplay( IN UCHAR Value ) /*++ Routine Description: This displays a 0--F in the single hexadecimal digit display in Jensen. Arguments: Value The lower four bits of this will be displayed in the Jensen LED. Return Value: None. --*/ { WRITE_PORT_UCHAR ((PUCHAR)SYSCTL, (READ_PORT_UCHAR((PUCHAR)SYSCTL) & 0xf0) | (Value & 0x0f) ); }
VOID HalpInitializeNMI( VOID ) /*++ Routine Description: This function is called to intialize SIO NMI interrupts. Arguments: None. Return Value: None. --*/ { UCHAR DataByte; // // Initialize the SIO NMI interrupt. // KeInitializeInterrupt( &HalpEisaNmiInterrupt, HalHandleNMI, NULL, NULL, EISA_NMI_VECTOR, EISA_NMI_LEVEL, EISA_NMI_LEVEL, LevelSensitive, FALSE, 0, FALSE ); // // Don't fail if the interrupt cannot be connected. // KeConnectInterrupt( &HalpEisaNmiInterrupt ); // // Clear the Eisa NMI disable bit. This bit is the high order of the // NMI enable register. Note that the other bits should be left as // they are, according to the chip's documentation. // //[wem] ?? Avanti simply writes zero to NmiEnable -- OK DataByte = READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable); ((PNMI_ENABLE)(&DataByte))->NmiDisable = 0; WRITE_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable, DataByte); #ifdef DBG DbgPrint("HalpIntializeNMI: wrote 0x%x to NmiEnable\n", DataByte); #endif }
UCHAR NTAPI ScsiPortReadPortUchar( IN PUCHAR Port) { return READ_PORT_UCHAR(Port); }
static NTSTATUS read_port(PDEVICE_OBJECT devobj, PIRP irp, PUCHAR port) { NTSTATUS status = STATUS_SUCCESS; PIO_STACK_LOCATION irpsp; PFILE_OBJECT fileobj; struct eppflex *s = devobj->DeviceExtension; struct eppflexfile *fs; struct eppflex_rwdata *rw = (struct eppflex_rwdata *)irp->AssociatedIrp.SystemBuffer; irpsp = IoGetCurrentIrpStackLocation(irp); fileobj = irpsp->FileObject; fs = fileobj->FsContext; irp->IoStatus.Information = 0; if (irpsp->Parameters.DeviceIoControl.OutputBufferLength < sizeof(struct eppflex_rwdata)) status = STATUS_INVALID_PARAMETER; else if ((port < fs->info.Controller || port >= fs->info.Controller+fs->info.SpanOfController) && (port < fs->pnpinfo.EcpController || port >= fs->pnpinfo.EcpController+fs->pnpinfo.SpanOfEcpController)) status = STATUS_ACCESS_VIOLATION; else { rw->data = READ_PORT_UCHAR(port); irp->IoStatus.Information = sizeof(struct eppflex_rwdata); } irp->IoStatus.Status = status; IoCompleteRequest(irp, IO_NO_INCREMENT); return status; }
UCHAR ScsiPortReadPortUchar( IN PUCHAR Port ) /*++ Routine Description: Read from the specified port address. Arguments: Port - Supplies a pointer to the port address. Return Value: Returns the value read from the specified port address. --*/ { return(READ_PORT_UCHAR(Port)); }
UCHAR HalpAcknowledgeEisaInterrupt( PVOID ServiceContext ) /*++ Routine Description: Acknowledge the EISA interrupt from the programmable interrupt controller. Return the vector number of the highest priority pending interrupt. Arguments: ServiceContext - Service context of the interrupt service supplies a pointer to the EISA interrupt acknowledge register. Return Value: Return the value of the highest priority pending interrupt. --*/ { UCHAR InterruptVector; // // Read the interrupt vector from the PIC. // InterruptVector = READ_PORT_UCHAR(ServiceContext); return( InterruptVector ); }
/* * FUNCTION: Read data from port 0x60 */ NTSTATUS i8042ReadData( IN PPORT_DEVICE_EXTENSION DeviceExtension, IN UCHAR StatusFlags, OUT PUCHAR Data) { UCHAR PortStatus; NTSTATUS Status; Status = i8042ReadStatus(DeviceExtension, &PortStatus); if (!NT_SUCCESS(Status)) return Status; // If data is available if (PortStatus & StatusFlags) { *Data = READ_PORT_UCHAR(DeviceExtension->DataPort); INFO_(I8042PRT, "Read: 0x%02x (status: 0x%x)\n", Data[0], PortStatus); // If the data is valid (not timeout, not parity error) if ((PortStatus & KBD_PERR) == 0) return STATUS_SUCCESS; } return STATUS_UNSUCCESSFUL; }
/* * FUNCTION: Write data to a port, waiting first for it to become ready */ BOOLEAN i8042Write( IN PPORT_DEVICE_EXTENSION DeviceExtension, IN PUCHAR addr, IN UCHAR data) { ULONG Counter; ASSERT(addr); ASSERT(DeviceExtension->ControlPort != NULL); Counter = DeviceExtension->Settings.PollingIterations; while ((KBD_IBF & READ_PORT_UCHAR(DeviceExtension->ControlPort)) && (Counter--)) { KeStallExecutionProcessor(50); } if (Counter) { WRITE_PORT_UCHAR(addr, data); INFO_(I8042PRT, "Sent 0x%x to port %p\n", data, addr); return TRUE; } return FALSE; }
static FORCEINLINE NTSTATUS __UnplugPreamble( IN PXENFILT_UNPLUG_CONTEXT Context, IN BOOLEAN Locked ) { KIRQL Irql = PASSIVE_LEVEL; USHORT Magic; UCHAR Version; NTSTATUS status; if (!Locked) AcquireHighLock(&Context->Lock, &Irql); // See docs/misc/hvm-emulated-unplug.markdown for details of the // protocol in use here Magic = READ_PORT_USHORT((PUSHORT)0x10); if (Magic == 0xd249) { Context->BlackListed = TRUE; goto done; } status = STATUS_NOT_SUPPORTED; if (Magic != 0x49d2) goto fail1; Version = READ_PORT_UCHAR((PUCHAR)0x12); if (Version != 0) { WRITE_PORT_USHORT((PUSHORT)0x12, 0xFFFF); // FIXME WRITE_PORT_ULONG((PULONG)0x10, (MAJOR_VERSION << 16) | (MINOR_VERSION << 8) | MICRO_VERSION); Magic = READ_PORT_USHORT((PUSHORT)0x10); if (Magic == 0xd249) Context->BlackListed = TRUE; } done: LogPrintf(LOG_LEVEL_WARNING, "UNPLUG: PRE-AMBLE (DRIVERS %s)\n", (Context->BlackListed) ? "BLACKLISTED" : "NOT BLACKLISTED"); if (!Locked) ReleaseHighLock(&Context->Lock, Irql); return STATUS_SUCCESS; fail1: Error("fail1 (%08x)\n", status); if (!Locked) ReleaseHighLock(&Context->Lock, Irql); return status; }
void cPcSpeakerServer::soundOff() { traceMedium("PcSpeakerServer: soundOff" << endl); // Turn off the PcSpekaer gate UCHAR speaker = READ_PORT_UCHAR(SPEAKER_PORT); WRITE_PORT_UCHAR(SPEAKER_PORT, speaker & (~SPEAKER_SIGNAL_BIT)); }
void cPcSpeakerServer::soundOn() { traceMedium("PcSpeakerServer: soundOn" << endl); // Activate PcSpekaer gate UCHAR speaker = READ_PORT_UCHAR(SPEAKER_PORT); WRITE_PORT_UCHAR(SPEAKER_PORT, speaker | SPEAKER_SIGNAL_BIT); }
VOID NTAPI HwDumpRegisters(PCONTROLLER_INFO ControllerInfo) /* * FUNCTION: Dump all readable registers from the floppy controller * ARGUMENTS: * ControllerInfo: Controller to dump registers from */ { UNREFERENCED_PARAMETER(ControllerInfo); INFO_(FLOPPY, "STATUS:\n"); INFO_(FLOPPY, "STATUS_REGISTER_A = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + STATUS_REGISTER_A)); INFO_(FLOPPY, "STATUS_REGISTER_B = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + STATUS_REGISTER_B)); INFO_(FLOPPY, "DIGITAL_OUTPUT_REGISTER = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_OUTPUT_REGISTER)); INFO_(FLOPPY, "MAIN_STATUS_REGISTER =0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + MAIN_STATUS_REGISTER)); INFO_(FLOPPY, "DIGITAL_INPUT_REGISTER = 0x%x\n", READ_PORT_UCHAR(ControllerInfo->BaseAddress + DIGITAL_INPUT_REGISTER)); }
// // fetch a byte // ULONG CpGetByte(__in PCPPORT Port,__out PUCHAR Byte,__in BOOLEAN WaitForByte,__in BOOLEAN CheckOnly) { // // check to make sure the CPPORT we were passed has been initialized. // if(!Port->Address) return CP_GET_NODATA; ULONG LimitCount = WaitForByte ? 204800 : 1; while(LimitCount) { LimitCount -= 1; // // check data ready // UCHAR lsr = CpReadLsr(Port,COM_DATRDY); if((lsr & COM_DATRDY) == COM_DATRDY) { // // check for errors // if(lsr & (COM_FE | COM_PE | COM_OE)) { *Byte = 0; return CP_GET_ERROR; } // // check data ready only // if(CheckOnly) return CP_GET_SUCCESS; // // fetch the byte // UCHAR value = READ_PORT_UCHAR(Port->Address + COM_DAT); if(Port->Flags & PORT_MODEMCONTROL) { // // using modem control. if no CD, then skip this byte. // if((READ_UCHAR(Port->Address + COM_MSR) & MS_CD) == 0) continue; } *Byte = value & 0xff; return CP_GET_SUCCESS; } } CpReadLsr(Port,0); return CP_GET_NODATA; }