{ BRDATA (CS1, rpcs1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DA, rpda, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DS, rpds, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER1, rper1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (HR, rmhr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (OF, rpof, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DC, rpdc, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER2, rper2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER3, rper3, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC1, rpec1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC2, rpec2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR, rpmr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR2, rmmr2, DEV_RDX, 16, RP_NUMDR) },
{ DRDATA (STIME, rp_swait, 24), REG_NZ + PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), REG_NZ + PV_LEFT },
{ URDATA (CAPAC, rp_unit[0].capac, 10, T_ADDR_W, 0,
RP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ GRDATA (CTRLTYPE, rp_dib.lnt, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB rp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rp_set_bad },
{ (UNIT_DTYPE+UNIT_ATT), (RM03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM03", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RP04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RP04", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RM80_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
MTAB dcsl_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcs_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
&tmxr_set_log, &tmxr_show_log, &dcs_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
&tmxr_set_nolog, NULL, &dcs_desc },
{ 0 }
};
REG dcsl_reg[] = {
{ URDATA (TIME, dcsl_unit[0].wait, 10, 24, 0,
DCS_LINES, REG_NZ + PV_LEFT) },
{ NULL }
};
DEVICE dcsl_dev = {
"DCSL", dcsl_unit, dcsl_reg, dcsl_mod,
DCS_LINES, 10, 31, 1, 8, 8,
NULL, NULL, &dcs_reset,
NULL, NULL, NULL,
NULL, DEV_DIS | DEV_MUX
};
/* DCS IOT routine */
int32 dcs (int32 inst, int32 dev, int32 dat)
{
{ HRDATA (STA, dp_sta, 8) },
{ HRDATA (BUF, dp_db, 8) },
{ HRDATA (PLAT, dp_plat, 1) },
{ HRDATA (HDSC, dp_hdsc, 6) },
{ HRDATA (CYL, dp_cyl, 9) },
{ HRDATA (SVUN, dp_svun, 8), REG_HIDDEN },
{ BRDATA (DBUF, dpxb, 16, 8, DP_NUMBY) },
{ HRDATA (DBPTR, dp_bptr, 9), REG_RO },
{ FLDATA (FIRST, dp_1st, 0) },
{ GRDATA (IREQ, int_req[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
{ GRDATA (IENB, int_enb[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
{ BRDATA (IARM, dpd_arm, 16, 1, DP_NUMDR) },
{ DRDATA (RTIME, dp_rtime, 0), PV_LEFT | REG_NZ },
{ DRDATA (STIME, dp_stime, 0), PV_LEFT | REG_NZ },
{ DRDATA (WTIME, dp_wtime, 0), PV_LEFT | REG_NZ },
{ URDATA (UCYL, dp_unit[0].CYL, 16, 9, 0,
DP_NUMDR, REG_RO) },
{ URDATA (UST, dp_unit[0].STD, 16, 8, 0,
DP_NUMDR, REG_RO) },
{ URDATA (CAPAC, dp_unit[0].capac, 10, T_ADDR_W, 0,
DP_NUMDR, PV_LEFT | REG_HRO) },
{ HRDATA (DEVNO, dp_dib.dno, 8), REG_HRO },
{ HRDATA (SELCH, dp_dib.sch, 2), REG_HRO },
{ NULL }
};
MTAB dp_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ (UNIT_DTYPE+UNIT_ATT), (TYPE_2315 << UNIT_V_DTYPE) + UNIT_ATT,
"2315", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (TYPE_5440 << UNIT_V_DTYPE) + UNIT_ATT,
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT},
{UDATA(&dco_svc, TT_MODE_7P + DCX_EPAR + DCX_MDM, 0), SERIAL_OUT_WAIT}
};
REG dco_reg[] = {
{BRDATA(BUF, dco_buf, DEV_RDX, 8, DCX_LINES)},
{BRDATA(CSR, dco_csr, DEV_RDX, 16, DCX_LINES)},
{GRDATA(IREQ, dco_ireq, DEV_RDX, DCX_LINES, 0)},
{URDATA(TIME, dco_unit[0].wait, 10, 31, 0,
DCX_LINES, PV_LEFT)},
{NULL}
};
MTAB dco_mod[] = {
{TT_MODE, TT_MODE_UC, "UC", "UC", NULL},
{TT_MODE, TT_MODE_7B, "7b", "7B", NULL},
{TT_MODE, TT_MODE_8B, "8b", "8B", NULL},
{TT_MODE, TT_MODE_7P, "7p", "7P", NULL},
{DCX_OPAR + DCX_EPAR, 0, "no parity", "NOPARITY", NULL},
{DCX_OPAR + DCX_EPAR, DCX_OPAR, "odd parity", "ODDPARITY", NULL},
{DCX_OPAR + DCX_EPAR, DCX_EPAR, "even parity", "EVENPARITY", NULL},
{DCX_MDM, 0, "no dataset", "NODATASET", NULL},
{DCX_MDM, DCX_MDM, "dataset", "DATASET", NULL},
{MTAB_XTD | MTAB_VUN, 0, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc},
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT },
{ UDATA (&ttox_svc, TT_MODE_KSR+UNIT_DIS, 0), SERIAL_OUT_WAIT }
};
REG ttox_reg[] = {
{ BRDATA (BUF, ttox_buf, 8, 8, TTX_MAXL) },
{ ORDATA (DONE, ttox_done, TTX_MAXL) },
{ FLDATA (INT, int_hwre[API_TTO1], INT_V_TTO1) },
{ URDATA (TIME, ttox_unit[0].wait, 10, 24, 0,
TTX_MAXL, PV_LEFT) },
{ NULL }
};
MTAB ttox_mod[] = {
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &ttx_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
&tmxr_set_log, &tmxr_show_log, &ttx_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
&tmxr_set_nolog, NULL, &ttx_desc },
{ 0 }
{ FLDATA (BUSY, dp_sta, 15) },
{ FLDATA (RDY, dp_sta, 14) },
{ FLDATA (EOR, dp_eor, 0) },
{ FLDATA (DEFINT, dp_defint, 0) },
{ FLDATA (INTREQ, dev_int, INT_V_DP) },
{ FLDATA (ENABLE, dev_enb, INT_V_DP) },
{ BRDATA (TBUF, dpxb, 8, 16, DP_TRKLEN) },
{ ORDATA (RPTR, dp_rptr, 11), REG_RO },
{ ORDATA (WPTR, dp_wptr, 11), REG_RO },
{ ORDATA (BCTR, dp_bctr, 15), REG_RO },
{ ORDATA (GAP, dp_gap, 16), REG_RO },
{ DRDATA (STIME, dp_stime, 24), REG_NZ + PV_LEFT },
{ DRDATA (XTIME, dp_xtime, 24), REG_NZ + PV_LEFT },
{ DRDATA (BTIME, dp_btime, 24), REG_NZ + PV_LEFT },
{ FLDATA (CTYPE, dp_ctype, 0), REG_HRO },
{ URDATA (UCYL, dp_unit[0].CYL, 10, 8, 0,
DP_NUMDRV, PV_LEFT | REG_HRO) },
{ URDATA (UFNC, dp_unit[0].FNC, 8, 7, 0,
DP_NUMDRV, REG_HRO) },
{ URDATA (CAPAC, dp_unit[0].capac, 10, T_ADDR_W, 0,
DP_NUMDRV, PV_LEFT | REG_HRO) },
{ ORDATA (OTAS, dp_otas, 2), REG_HRO },
{ ORDATA (XIP, dp_xip, 6), REG_HRO },
{ ORDATA (CHAN, dp_dib.chan, 5), REG_HRO },
{ FLDATA (STOP_IOE, dp_stopioe, 0) },
{ NULL }
};
MTAB dp_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD | MTAB_VDV, TYPE_4623, NULL, "4623",
MTAB muxl_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", NULL },
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &mux_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
&tmxr_set_log, &tmxr_show_log, &mux_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
&tmxr_set_nolog, NULL, &mux_desc },
{ 0 }
};
REG muxl_reg[] = {
{ URDATA (TIME, muxl_unit[0].wait, 10, 24, 0,
MUX_LINES, REG_NZ + PV_LEFT) },
{ NULL }
};
DEVICE muxl_dev = {
"MUXL", muxl_unit, muxl_reg, muxl_mod,
MUX_LINES, 10, 31, 1, 8, 8,
NULL, NULL, &mux_reset,
NULL, NULL, NULL,
NULL, 0
};
/* MUX: IO routine */
/* Mux routine - EOM 30001 or EOM 77777,2 */
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) },
{ UDATA (&mtr_svc, UNIT_DIS, 0) }
};
REG mt_reg[] = {
{ BRDATA (BUF, mt_xb, 16, 8, MT_MAXFR) },
{ DRDATA (BPTR, mt_bptr, 17) },
{ DRDATA (BLNT, mt_blim, 17) },
{ HRDATA (RWINT, mt_rwi, MT_NUMDR) },
{ DRDATA (TIME, mt_time, 24), PV_LEFT+REG_NZ },
{ DRDATA (CTIME, mt_ctime, 24), PV_LEFT+REG_NZ },
{ DRDATA (RWTIME, mt_rwtime, 24), PV_LEFT+REG_NZ },
{ URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
{ URDATA (UCMD, mt_unit[0].UCMD, 16, 8, 0, 2 * MT_NUMDR, 0) },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ HRDATA (DEVNO, mt_dib.dva, 12), REG_HRO },
{ NULL }
};
MTAB mt_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ ORDATA (CNT, dqc_cnt, 9) },
{ FLDATA (CMD, dqc.command, 0) },
{ FLDATA (CTL, dqc.control, 0) },
{ FLDATA (FLG, dqc.flag, 0) },
{ FLDATA (FBF, dqc.flagbuf, 0) },
{ DRDATA (RARC, dqc_rarc, 8), PV_RZRO | REG_FIT },
{ DRDATA (RARH, dqc_rarh, 5), PV_RZRO | REG_FIT },
{ DRDATA (RARS, dqc_rars, 5), PV_RZRO | REG_FIT },
{ BRDATA (CYL, dqc_ucyl, 10, 8, DQ_NUMDRV), PV_RZRO },
{ BRDATA (HED, dqc_uhed, 10, 5, DQ_NUMDRV), PV_RZRO },
{ BRDATA (STA, dqc_sta, 8, 16, DQ_NUMDRV) },
{ DRDATA (CTIME, dqc_ctime, 24), PV_LEFT },
{ DRDATA (DTIME, dqc_dtime, 24), PV_LEFT },
{ DRDATA (STIME, dqc_stime, 24), PV_LEFT },
{ DRDATA (XTIME, dqc_xtime, 24), REG_NZ + PV_LEFT },
{ URDATA (UFNC, dqc_unit[0].FNC, 8, 8, 0,
DQ_NUMDRV, REG_HRO) },
{ ORDATA (SC, dqc_dib.select_code, 6), REG_HRO },
{ ORDATA (DEVNO, dqc_dib.select_code, 6), REG_HRO },
{ NULL }
};
MTAB dqc_mod[] = {
{ UNIT_UNLOAD, UNIT_UNLOAD, "heads unloaded", "UNLOADED", dqc_load_unload },
{ UNIT_UNLOAD, 0, "heads loaded", "LOADED", dqc_load_unload },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD | MTAB_VDV, 1, "SC", "SC", &hp_setsc, &hp_showsc, &dqd_dev },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "DEVNO", "DEVNO", &hp_setdev, &hp_showdev, &dqd_dev },
{ 0 }
};
{ GRDATA (RYES, ry_esr, DEV_RDX, 12, 0) },
{ GRDATA (RYERR, ry_ecode, DEV_RDX, 8, 0) },
{ GRDATA (RYTA, ry_track, DEV_RDX, 8, 0) },
{ GRDATA (RYSA, ry_sector, DEV_RDX, 8, 0) },
{ DRDATA (STAPTR, ry_state, 4), REG_RO },
{ FLDATA (INT, IREQ (RY), INT_V_RY) },
{ FLDATA (ERR, ry_csr, RYCS_V_ERR) },
{ FLDATA (TR, ry_csr, RYCS_V_TR) },
{ FLDATA (IE, ry_csr, RYCS_V_IE) },
{ FLDATA (DONE, ry_csr, RYCS_V_DONE) },
{ DRDATA (CTIME, ry_cwait, 24), PV_LEFT },
{ DRDATA (STIME, ry_swait, 24), PV_LEFT },
{ DRDATA (XTIME, ry_xwait, 24), PV_LEFT },
{ BRDATA (SBUF, rx2xb, 8, 8, RY_NUMBY) },
{ FLDATA (STOP_IOE, ry_stopioe, 0) },
{ URDATA (CAPAC, ry_unit[0].capac, 10, T_ADDR_W, 0,
RX_NUMDR, REG_HRO | PV_LEFT) },
{ GRDATA (DEVADDR, ry_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ry_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ry_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ (UNIT_DEN+UNIT_ATT), UNIT_ATT, "single density", NULL, NULL },
{ (UNIT_DEN+UNIT_ATT), (UNIT_DEN+UNIT_ATT), "double density", NULL, NULL },
{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), 0, "single density", NULL, NULL },
{ (UNIT_AUTO+UNIT_DEN+UNIT_ATT), UNIT_DEN, "double density", NULL, NULL },
{ (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },
{ UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },
{ (UNIT_AUTO+UNIT_DEN), 0, NULL, "SINGLE", &ry_set_size },
},
{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ATTABLE +
UNIT_BUFABLE + UNIT_MUSTBUF + UNIT_BCD, DP_SIZE)
},
{ UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ATTABLE +
UNIT_BUFABLE + UNIT_MUSTBUF + UNIT_BCD, DP_SIZE)
}
};
REG dp_reg[] = {
{ FLDATA (ADCHK, ind[IN_DACH], 0) },
{ FLDATA (WLRC, ind[IN_DWLR], 0) },
{ FLDATA (CYLO, ind[IN_DCYO], 0) },
{ FLDATA (ERR, ind[IN_DERR], 0) },
{ FLDATA (DPSTOP, dp_stop, 0) },
{ URDATA (CYL, dp_unit[0].CYL, 10, 8, 0,
DP_NUMDR, PV_LEFT + REG_RO)
},
{ NULL }
};
MTAB dp_mod[] = {
{ UNIT_WAE, 0, "write address disabled", "ADDROFF", NULL },
{ UNIT_WAE, UNIT_WAE, "write address enabled", "ADDRON", NULL },
{ 0 }
};
DEVICE dp_dev = {
"DP", dp_unit, dp_reg, dp_mod,
DP_NUMDR, 10, 21, 1, 16, 5,
NULL, NULL, &dp_reset,
NULL, NULL, NULL
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
{ UNIT_MDM, 0, "no dataset", "NODATASET", NULL },
{ UNIT_MDM, UNIT_MDM, "dataset", "DATASET", NULL },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &pas_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
&tmxr_set_log, &tmxr_show_log, &pas_desc },
{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
&tmxr_set_nolog, NULL, &pas_desc },
{ 0 }
};
REG pasl_reg[] = {
{ URDATA (TIME, pasl_unit[0].wait, 16, 24, 0,
PAS_LINES, REG_NZ + PV_LEFT) },
{ NULL }
};
DEVICE pasl_dev = {
"PASL", pasl_unit, pasl_reg, pasl_mod,
PAS_LINES, 10, 31, 1, 16, 8,
NULL, NULL, &pas_reset,
NULL, NULL, NULL,
NULL, 0
};
/* PAS: IO routine */
uint32 pas (uint32 dev, uint32 op, uint32 dat)
{
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }
};
REG mt_reg[] = {
{ BRDATA (BUF, mtxb, 8, 8, MT_MAXFR) },
{ DRDATA (BPTR, mt_bptr, 18), PV_LEFT },
{ DRDATA (BLNT, mt_blnt, 18), PV_LEFT },
{ FLDATA (XFR, xfr_req, XFR_V_MT0) },
{ ORDATA (INST, mt_inst, 24) },
{ FLDATA (EOF, mt_eof, 0) },
{ FLDATA (GAP, mt_gap, 0) },
{ FLDATA (SKIP, mt_skip, 0) },
{ DRDATA (CTIME, mt_ctime, 24), REG_NZ + PV_LEFT },
{ DRDATA (GTIME, mt_gtime, 24), REG_NZ + PV_LEFT },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ URDATA (BOT, mt_unit[0].botf, 10, 1, 0, MT_NUMDR, REG_RO) },
{ URDATA (EOT, mt_unit[0].eotf, 10, 1, 0, MT_NUMDR, REG_RO) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ NULL }
};
MTAB mt_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "CHANNEL", "CHANNEL",
&set_chan, &show_chan, NULL },