}; static bool vsx_needed(void *opaque) { PowerPCCPU *cpu = opaque; return (cpu->env.insns_flags2 & PPC2_VSX); } static const VMStateDescription vmstate_vsx = { .name = "cpu/vsx", .version_id = 1, .minimum_version_id = 1, .needed = vsx_needed, .fields = (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32), VMSTATE_END_OF_LIST() }, }; #ifdef TARGET_PPC64 /* Transactional memory state */ static bool tm_needed(void *opaque) { PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; return msr_ts; } static const VMStateDescription vmstate_tm = { .name = "cpu/tm",
static bool spapr_vlan_rx_buffer_pools_needed(void *opaque) { VIOsPAPRVLANDevice *dev = opaque; return (dev->compat_flags & SPAPRVLAN_FLAG_RX_BUF_POOLS) != 0; } static const VMStateDescription vmstate_rx_buffer_pool = { .name = "spapr_llan/rx_buffer_pool", .version_id = 1, .minimum_version_id = 1, .needed = spapr_vlan_rx_buffer_pools_needed, .fields = (VMStateField[]) { VMSTATE_INT32(bufsize, RxBufPool), VMSTATE_INT32(count, RxBufPool), VMSTATE_UINT64_ARRAY(bds, RxBufPool, RX_POOL_MAX_BDS), VMSTATE_END_OF_LIST() } }; static const VMStateDescription vmstate_rx_pools = { .name = "spapr_llan/rx_pools", .version_id = 1, .minimum_version_id = 1, .needed = spapr_vlan_rx_buffer_pools_needed, .fields = (VMStateField[]) { VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(rx_pool, VIOsPAPRVLANDevice, RX_MAX_POOLS, 1, vmstate_rx_buffer_pool, RxBufPool), VMSTATE_END_OF_LIST() }
}; static bool iwmmxt_needed(void *opaque) { ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; return arm_feature(env, ARM_FEATURE_IWMMXT); } static const VMStateDescription vmstate_iwmmxt = { .name = "cpu/iwmmxt", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), VMSTATE_END_OF_LIST() } }; static bool m_needed(void *opaque) { ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; return arm_feature(env, ARM_FEATURE_M); } static const VMStateDescription vmstate_m = { .name = "cpu/m",
VMSTATE_END_OF_LIST() } }; static bool gscb_needed(void *opaque) { return s390_has_feat(S390_FEAT_GUARDED_STORAGE); } const VMStateDescription vmstate_gscb = { .name = "cpu/gscb", .version_id = 1, .minimum_version_id = 1, .needed = gscb_needed, .fields = (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.gscb, S390CPU, 4), VMSTATE_END_OF_LIST() } }; const VMStateDescription vmstate_s390_cpu = { .name = "cpu", .post_load = cpu_post_load, .pre_save = cpu_pre_save, .version_id = 4, .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.regs, S390CPU, 16), VMSTATE_UINT64(env.psw.mask, S390CPU), VMSTATE_UINT64(env.psw.addr, S390CPU), VMSTATE_UINT64(env.psa, S390CPU),
} return 0; } static const VMStateDescription vmstate_its = { .name = "arm_gicv3_its", .pre_save = gicv3_its_pre_save, .post_load = gicv3_its_post_load, .priority = MIG_PRI_GICV3_ITS, .fields = (VMStateField[]) { VMSTATE_UINT32(ctlr, GICv3ITSState), VMSTATE_UINT32(iidr, GICv3ITSState), VMSTATE_UINT64(cbaser, GICv3ITSState), VMSTATE_UINT64(cwriter, GICv3ITSState), VMSTATE_UINT64(creadr, GICv3ITSState), VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8), VMSTATE_END_OF_LIST() }, }; static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, uint64_t *data, unsigned size, MemTxAttrs attrs) { qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset); *data = 0; return MEMTX_OK; } static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, uint64_t value, unsigned size,
LM32PicState *s = LM32_PIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); qdev_init_gpio_in(dev, irq_handler, 32); sysbus_init_irq(sbd, &s->parent_irq); } static const VMStateDescription vmstate_lm32_pic = { .name = "lm32-pic", .version_id = 2, .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(im, LM32PicState), VMSTATE_UINT32(ip, LM32PicState), VMSTATE_UINT32(irq_state, LM32PicState), VMSTATE_UINT64_ARRAY(stats_irq_count, LM32PicState, 32), VMSTATE_END_OF_LIST() } }; static void lm32_pic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass); dc->reset = pic_reset; dc->vmsd = &vmstate_lm32_pic; ic->get_statistics = lm32_get_statistics; ic->print_info = lm32_print_info; }
return 0; } static const VMStateDescription vmstate_ioapic_common = { .name = "ioapic", .version_id = 3, .minimum_version_id = 1, .minimum_version_id_old = 1, .pre_save = ioapic_dispatch_pre_save, .post_load = ioapic_dispatch_post_load, .fields = (VMStateField[]) { VMSTATE_UINT8(id, IOAPICCommonState), VMSTATE_UINT8(ioregsel, IOAPICCommonState), VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */ VMSTATE_UINT32_V(irr, IOAPICCommonState, 2), VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS), VMSTATE_END_OF_LIST() } }; static void ioapic_common_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); sc->init = ioapic_init_common; dc->vmsd = &vmstate_ioapic_common; dc->no_user = 1; } static TypeInfo ioapic_common_type = {
VMSTATE_INT32(env.CP0_Compare, MIPSCPU), VMSTATE_INT32(env.CP0_Status, MIPSCPU), VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU), VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU), VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU), VMSTATE_INT32(env.CP0_Cause, MIPSCPU), VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), VMSTATE_INT32(env.CP0_PRid, MIPSCPU), VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU), VMSTATE_INT32(env.CP0_Config0, MIPSCPU), VMSTATE_INT32(env.CP0_Config1, MIPSCPU), VMSTATE_INT32(env.CP0_Config2, MIPSCPU), VMSTATE_INT32(env.CP0_Config3, MIPSCPU), VMSTATE_INT32(env.CP0_Config6, MIPSCPU), VMSTATE_INT32(env.CP0_Config7, MIPSCPU), VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX), VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), VMSTATE_UINT64(env.lladdr, MIPSCPU), VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), VMSTATE_INT32(env.CP0_Debug, MIPSCPU), VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),