static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode) { struct drm_device *dev = crtc->dev; struct cirrus_device *cdev = dev->dev_private; u8 sr01, gr0e; switch (mode) { case DRM_MODE_DPMS_ON: sr01 = 0x00; gr0e = 0x00; break; case DRM_MODE_DPMS_STANDBY: sr01 = 0x20; gr0e = 0x02; break; case DRM_MODE_DPMS_SUSPEND: sr01 = 0x20; gr0e = 0x04; break; case DRM_MODE_DPMS_OFF: sr01 = 0x20; gr0e = 0x06; break; default: return; } WREG8(SEQ_INDEX, 0x1); sr01 |= RREG8(SEQ_DATA) & ~0x20; WREG_SEQ(0x1, sr01); WREG8(GFX_INDEX, 0xe); gr0e |= RREG8(GFX_DATA) & ~0x06; WREG_GFX(0xe, gr0e); }
static void avivo_crtc_load_lut(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_device *dev = crtc->dev; struct radeon_device *rdev = dev->dev_private; int i; DRM_DEBUG("%d\n", radeon_crtc->crtc_id); WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); WREG32(AVIVO_DC_LUT_RW_MODE, 0); WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); WREG8(AVIVO_DC_LUT_RW_INDEX, 0); for (i = 0; i < 256; i++) { WREG32(AVIVO_DC_LUT_30_COLOR, (radeon_crtc->lut_r[i] << 20) | (radeon_crtc->lut_g[i] << 10) | (radeon_crtc->lut_b[i] << 0)); } WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); }
static void cirrus_crtc_load_lut(struct drm_crtc *crtc) { struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc); struct drm_device *dev = crtc->dev; struct cirrus_device *cdev = dev->dev_private; int i; if (!crtc->enabled) return; for (i = 0; i < CIRRUS_LUT_SIZE; i++) { /* VGA registers */ WREG8(PALETTE_INDEX, i); WREG8(PALETTE_DATA, cirrus_crtc->lut_r[i]); WREG8(PALETTE_DATA, cirrus_crtc->lut_g[i]); WREG8(PALETTE_DATA, cirrus_crtc->lut_b[i]); } }
static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset) { struct cirrus_device *cdev = crtc->dev->dev_private; u32 addr; u8 tmp; addr = offset >> 2; WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff)); WREG_CRT(0x0d, (u8)(addr & 0xff)); WREG8(CRT_INDEX, 0x1b); tmp = RREG8(CRT_DATA); tmp &= 0xf2; tmp |= (addr >> 16) & 0x01; tmp |= (addr >> 15) & 0x0c; WREG_CRT(0x1b, tmp); WREG8(CRT_INDEX, 0x1d); tmp = RREG8(CRT_DATA); tmp &= 0x7f; tmp |= (addr >> 12) & 0x80; WREG_CRT(0x1d, tmp); }
static void cirrus_crtc_load_lut(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct cirrus_device *cdev = dev->dev_private; u16 *r, *g, *b; int i; if (!crtc->enabled) return; r = crtc->gamma_store; g = r + crtc->gamma_size; b = g + crtc->gamma_size; for (i = 0; i < CIRRUS_LUT_SIZE; i++) { /* VGA registers */ WREG8(PALETTE_INDEX, i); WREG8(PALETTE_DATA, *r++ >> 8); WREG8(PALETTE_DATA, *g++ >> 8); WREG8(PALETTE_DATA, *b++ >> 8); } }
static void legacy_crtc_load_lut(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); struct drm_device *dev = crtc->dev; struct radeon_device *rdev = dev->dev_private; int i; uint32_t dac2_cntl; dac2_cntl = RREG32(RADEON_DAC_CNTL2); if (radeon_crtc->crtc_id == 0) dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; else dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; WREG32(RADEON_DAC_CNTL2, dac2_cntl); WREG8(RADEON_PALETTE_INDEX, 0); for (i = 0; i < 256; i++) { WREG32(RADEON_PALETTE_30_DATA, (radeon_crtc->lut_r[i] << 20) | (radeon_crtc->lut_g[i] << 10) | (radeon_crtc->lut_b[i] << 0)); } }
/* * The meat of this driver. The core passes us a mode and we have to program * it. The modesetting here is the bare minimum required to satisfy the qemu * emulation of this hardware, and running this against a real device is * likely to result in an inadequately programmed mode. We've already had * the opportunity to modify the mode, so whatever we receive here should * be something that can be correctly programmed and displayed */ static int cirrus_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, int x, int y, struct drm_framebuffer *old_fb) { struct drm_device *dev = crtc->dev; struct cirrus_device *cdev = dev->dev_private; int hsyncstart, hsyncend, htotal, hdispend; int vtotal, vdispend; int tmp; int sr07 = 0, hdr = 0; htotal = mode->htotal / 8; hsyncend = mode->hsync_end / 8; hsyncstart = mode->hsync_start / 8; hdispend = mode->hdisplay / 8; vtotal = mode->vtotal; vdispend = mode->vdisplay; vdispend -= 1; vtotal -= 2; htotal -= 5; hdispend -= 1; hsyncstart += 1; hsyncend += 1; WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20); WREG_CRT(VGA_CRTC_H_TOTAL, htotal); WREG_CRT(VGA_CRTC_H_DISP, hdispend); WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart); WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend); WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff); WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff); tmp = 0x40; if ((vdispend + 1) & 512) tmp |= 0x20; WREG_CRT(VGA_CRTC_MAX_SCAN, tmp); /* * Overflow bits for values that don't fit in the standard registers */ tmp = 16; if (vtotal & 256) tmp |= 1; if (vdispend & 256) tmp |= 2; if ((vdispend + 1) & 256) tmp |= 8; if (vtotal & 512) tmp |= 32; if (vdispend & 512) tmp |= 64; WREG_CRT(VGA_CRTC_OVERFLOW, tmp); tmp = 0; /* More overflow bits */ if ((htotal + 5) & 64) tmp |= 16; if ((htotal + 5) & 128) tmp |= 32; if (vtotal & 256) tmp |= 64; if (vtotal & 512) tmp |= 128; WREG_CRT(CL_CRT1A, tmp); /* Disable Hercules/CGA compatibility */ WREG_CRT(VGA_CRTC_MODE, 0x03); WREG8(SEQ_INDEX, 0x7); sr07 = RREG8(SEQ_DATA); sr07 &= 0xe0; hdr = 0; switch (crtc->primary->fb->bits_per_pixel) { case 8: sr07 |= 0x11; break; case 16: sr07 |= 0x17; hdr = 0xc1; break; case 24: sr07 |= 0x15; hdr = 0xc5; break; case 32: sr07 |= 0x19; hdr = 0xc5; break; default: return -1; } WREG_SEQ(0x7, sr07); /* Program the pitch */ tmp = crtc->primary->fb->pitches[0] / 8; WREG_CRT(VGA_CRTC_OFFSET, tmp); /* Enable extended blanking and pitch bits, and enable full memory */ tmp = 0x22; tmp |= (crtc->primary->fb->pitches[0] >> 7) & 0x10; tmp |= (crtc->primary->fb->pitches[0] >> 6) & 0x40; WREG_CRT(0x1b, tmp); /* Enable high-colour modes */ WREG_GFX(VGA_GFX_MODE, 0x40); /* And set graphics mode */ WREG_GFX(VGA_GFX_MISC, 0x01); WREG_HDR(hdr); cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0); /* Unblank (needed on S3 resume, vgabios doesn't do it then) */ outb(0x20, 0x3c0); return 0; }
static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) { WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0); }
static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) { WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2); }