#include <plat/mux.h> #include <plat/tc.h> #include "clock.h" extern void omap_check_revision(void); extern void omap_sram_init(void); /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ static struct map_desc omap_io_desc[] __initdata = { { .virtual = OMAP1_IO_VIRT, .pfn = __phys_to_pfn(OMAP1_IO_PHYS), .length = OMAP1_IO_SIZE, .type = MT_DEVICE } }; #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) static struct map_desc omap7xx_io_desc[] __initdata = { { .virtual = OMAP7XX_DSP_BASE, .pfn = __phys_to_pfn(OMAP7XX_DSP_START), .length = OMAP7XX_DSP_SIZE, .type = MT_DEVICE }, { .virtual = OMAP7XX_DSPREG_BASE, .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START),
#include <plat/iic.h> #include <plat/s3c2410.h> #include <plat/s3c2440.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/common-smdk.h> static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ { .virtual = (u32)S3C24XX_VA_ISA_WORD, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, .type = MT_DEVICE, }, { .virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000, .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)), .length = SZ_4M, .type = MT_DEVICE, }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(S3C2410_CS2), .length = 0x10000, .type = MT_DEVICE, }, { .virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000, .pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
*(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; } void clear_cs3_bit(int value) { cs3_shadow &= ~value; *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow; } EXPORT_SYMBOL(set_cs3_bit); EXPORT_SYMBOL(clear_cs3_bit); static struct map_desc simpad_io_desc[] __initdata = { { /* MQ200 */ .virtual = 0xf2800000, .pfn = __phys_to_pfn(0x4b800000), .length = 0x00800000, .type = MT_DEVICE }, { /* Paules CS3, write only */ .virtual = 0xf1000000, .pfn = __phys_to_pfn(0x18000000), .length = 0x00100000, .type = MT_DEVICE }, }; static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate) { if (port->mapbase == (u_int)&Ser1UTCR0) { if (state)
static struct resource cerf_flash_resource = { .start = SA1100_CS0_PHYS, .end = SA1100_CS0_PHYS + SZ_32M - 1, .flags = IORESOURCE_MEM, }; static void __init cerf_init_irq(void) { sa1100_init_irq(); set_irq_type(CERF_ETH_IRQ, IRQT_RISING); } static struct map_desc cerf_io_desc[] __initdata = { { /* Crystal Ethernet Chip */ .virtual = 0xf0000000, .pfn = __phys_to_pfn(0x08000000), .length = 0x00100000, .type = MT_DEVICE } }; static void __init cerf_map_io(void) { sa1100_map_io(); iotable_init(cerf_io_desc, ARRAY_SIZE(cerf_io_desc)); sa1100_register_uart(0, 3); sa1100_register_uart(1, 2); /* disable this and the uart2 device for sa1100_fir */ sa1100_register_uart(2, 1); /* set some GPDR bits here while it's safe */
&Mstar_alsa_device, #ifdef CONFIG_MSTAR_IIC_MODULE &Mstar_iic_device, #endif #ifdef CONFIG_MSTAR_GPIO_MODULE &Mstar_gpio_device, #endif }; /* IO tables for Registers, ITCM and DTCM */ static struct map_desc chip_io_desc[] __initdata = { /* Define Registers' physcial and virtual addresses */ { .virtual = IO_VIRT, .pfn = __phys_to_pfn(IO_PHYS), .length = IO_SIZE, .type = MT_DEVICE }, /* Define periphral physcial and virtual addresses */ { .virtual = PERI_VIRT, .pfn = __phys_to_pfn(PERI_PHYS), .length = PERI_SIZE, .type = MT_DEVICE }, { .virtual = L2_CACHE_VIRT, .pfn = __phys_to_pfn(L2_CACHE_PHYS),
static void __init palmtx_nand_init(void) { platform_device_register(&palmtx_nand); } #else static inline void palmtx_nand_init(void) {} #endif /****************************************************************************** * Machine init ******************************************************************************/ static struct map_desc palmtx_io_desc[] __initdata = { { .virtual = (unsigned long)PALMTX_PCMCIA_VIRT, .pfn = __phys_to_pfn(PALMTX_PCMCIA_PHYS), .length = PALMTX_PCMCIA_SIZE, .type = MT_DEVICE, }, { .virtual = (unsigned long)PALMTX_NAND_ALE_VIRT, .pfn = __phys_to_pfn(PALMTX_NAND_ALE_PHYS), .length = SZ_1M, .type = MT_DEVICE, }, { .virtual = (unsigned long)PALMTX_NAND_CLE_VIRT, .pfn = __phys_to_pfn(PALMTX_NAND_CLE_PHYS), .length = SZ_1M, .type = MT_DEVICE, } };
#include <mach/hardware.h> #include <mach/syscon.h> #include "clock.h" #include "mmc.h" /* * Static I/O mappings that are needed for booting the U300 platforms. The * only things we need are the areas where we find the timer, syscon and * intcon, since the remaining device drivers will map their own memory * physical to virtual as the need arise. */ static struct map_desc u300_io_desc[] __initdata = { { .virtual = U300_SLOW_PER_VIRT_BASE, .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE), .length = SZ_64K, .type = MT_DEVICE, }, { .virtual = U300_AHB_PER_VIRT_BASE, .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE), .length = SZ_32K, .type = MT_DEVICE, }, { .virtual = U300_FAST_PER_VIRT_BASE, .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE), .length = SZ_32K, .type = MT_DEVICE, },
#include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/mm.h> #include <linux/io.h> #include <mach/iomap.h> #include <asm/page.h> #include <asm/mach/map.h> #include "board.h" static struct map_desc tegra_io_desc[] __initdata = { { .virtual = IO_PPSB_VIRT, .pfn = __phys_to_pfn(IO_PPSB_PHYS), .length = IO_PPSB_SIZE, .type = MT_DEVICE, }, { .virtual = IO_APB_VIRT, .pfn = __phys_to_pfn(IO_APB_PHYS), .length = IO_APB_SIZE, .type = MT_DEVICE, }, { .virtual = IO_CPU_VIRT, .pfn = __phys_to_pfn(IO_CPU_PHYS), .length = IO_CPU_SIZE, .type = MT_DEVICE, },
static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, MSM7X30), MSM_DEVICE(DMOV), MSM_CHIP_DEVICE(GPIO1, MSM7X30), MSM_CHIP_DEVICE(GPIO2, MSM7X30), MSM_DEVICE(CLK_CTL), MSM_DEVICE(CLK_CTL_SH2), MSM_DEVICE(AD5), MSM_DEVICE(MDC), MSM_DEVICE(ACC), MSM_DEVICE(SAW), MSM_DEVICE(GCC), MSM_DEVICE(TCSR), #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ defined(CONFIG_DEBUG_MSM_UART3) MSM_DEVICE(DEBUG_UART), #endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), .length = MSM_SHARED_RAM_SIZE, .type = MT_DEVICE, }, };
extern void mt_power_off(void); extern void mt_fixup(struct tag *tags, char **cmdline, struct meminfo *mi); extern void mt_reserve(void); static void __init mt_init(void) { pm_power_off = mt_power_off; panic_on_oops = 1; } static struct map_desc mt_io_desc[] __initdata = { /* MM Subsys */ { .virtual = MMSYS_CONFIG_BASE, .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(MMSYS_CONFIG_BASE)), .length = SZ_128K, .type = MT_DEVICE }, /* G3D Sys */ { .virtual = G3D_CONFIG_BASE, .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(G3D_CONFIG_BASE)), .length = SZ_128K, .type = MT_DEVICE }, /* Perisys */ { .virtual = AP_DMA_BASE,
#include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> #include <plat/audio-simtec.h> #include "common.h" #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics" static struct map_desc anubis_iodesc[] __initdata = { /* ISA IO areas */ { .virtual = (u32)S3C24XX_VA_ISA_BYTE, .pfn = __phys_to_pfn(0x0), .length = SZ_4M, .type = MT_DEVICE, }, { .virtual = (u32)S3C24XX_VA_ISA_WORD, .pfn = __phys_to_pfn(0x0), .length = SZ_4M, .type = MT_DEVICE, }, /* we could possibly compress the next set down into a set of smaller tables * pagetables, but that would mean using an L2 section, and it still means * we cannot actually feed the same register to an LDR due to 16K spacing */ /* CPLD control registers */
#include <asm/mach/time.h> #include <mach/kirkwood.h> #include <plat/cache-feroceon-l2.h> #include <plat/ehci-orion.h> #include <plat/mv_xor.h> #include <plat/orion_nand.h> #include <plat/time.h> #include "common.h" /***************************************************************************** * I/O Address Mapping ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), .length = KIRKWOOD_PCIE_IO_SIZE, .type = MT_DEVICE, }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, .type = MT_DEVICE, }, }; void __init kirkwood_map_io(void) { iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc)); }
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/sched.h> #include <linux/mm.h> #include <linux/init.h> #include <mach/hardware.h> #include <asm/io.h> #include <asm/pgtable.h> #include <asm/page.h> #include <asm/mach/map.h> static struct map_desc pnx67xx_io_desc[] __initdata = { { .virtual = IO_BASE_VIRT, /* only peripherals */ .pfn = __phys_to_pfn(IO_BASE_PHYS), .length = IO_SIZE, .type = MT_DEVICE, } }; void __init pnx67xx_map_io(void) { iotable_init(pnx67xx_io_desc, ARRAY_SIZE(pnx67xx_io_desc) ); }
#include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <mach/board-pb1176.h> #include <mach/irqs.h> #include "core.h" static struct map_desc realview_pb1176_io_desc[] __initdata = { { .virtual = IO_ADDRESS(REALVIEW_SYS_BASE), .pfn = __phys_to_pfn(REALVIEW_SYS_BASE), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE), .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE), .pfn = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE), .pfn = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
.idcode = EXYNOS5250_CPU_ID, .idmask = EXYNOS_CPU_MASK, .map_io = exynos5_map_io, .init_clocks = exynos5_init_clocks, .init_uarts = exynos5_init_uarts, .init = exynos5_init, .name = name_exynos5250, }, }; /* minimal IO mapping */ static struct map_desc s5p_iodesc[] __initdata = { { .virtual = (unsigned long)S5P_VA_CHIPID, .pfn = __phys_to_pfn(S5P_PA_CHIPID), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C_VA_SYS, .pfn = __phys_to_pfn(S5P_PA_SYSCON), .length = SZ_64K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C_VA_TIMER, .pfn = __phys_to_pfn(S5P_PA_TIMER), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S3C_VA_WATCHDOG, .pfn = __phys_to_pfn(S3C_PA_WDT),
#include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/at91sam9263.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> #include "generic.h" #include "clock.h" static struct map_desc at91sam9263_io_desc[] __initdata = { { .virtual = AT91_VA_BASE_SYS, .pfn = __phys_to_pfn(AT91_BASE_SYS), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE, .pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE), .length = AT91SAM9263_SRAM0_SIZE, .type = MT_DEVICE, }, { .virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE, .pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE), .length = AT91SAM9263_SRAM1_SIZE, .type = MT_DEVICE, }, };
#include <plat/fb-core.h> #include <plat/s5pv210.h> #include <plat/adc-core.h> #include <plat/ata-core.h> #include <plat/fimc-core.h> #include <plat/iic-core.h> #include <plat/keypad-core.h> #include <plat/sdhci.h> #include <plat/reset.h> /* Initial IO mappings */ static struct map_desc s5pv210_iodesc[] __initdata = { { .virtual = (unsigned long)S5P_VA_SYSTIMER, .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_GPIO, .pfn = __phys_to_pfn(S5PV210_PA_GPIO), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = (unsigned long)VA_VIC0, .pfn = __phys_to_pfn(S5PV210_PA_VIC0), .length = SZ_16K, .type = MT_DEVICE, }, { .virtual = (unsigned long)VA_VIC1, .pfn = __phys_to_pfn(S5PV210_PA_VIC1),
#ifdef CONFIG_USB_DWC_OTG_HCD set_usb_phy_clk(USB_PHY_CLOCK_SEL_XTAL_DIV2); lm_device_register(&usb_ld_a); lm_device_register(&usb_ld_b); #endif #ifdef CONFIG_SATA_DWC_AHCI set_sata_phy_clk(SATA_PHY_CLOCK_SEL_DEMOD_PLL); lm_device_register(&sata_ld); #endif } /*VIDEO MEMORY MAPING*/ static __initdata struct map_desc meson_video_mem_desc[] = { { .virtual = PAGE_ALIGN(__phys_to_virt(RESERVED_MEM_START)), .pfn = __phys_to_pfn(RESERVED_MEM_START), .length = RESERVED_MEM_END-RESERVED_MEM_START+1, .type = MT_DEVICE, }, }; static __init void m1_map_io(void) { meson_map_io(); iotable_init(meson_video_mem_desc, ARRAY_SIZE(meson_video_mem_desc)); } static __init void m1_irq_init(void) { meson_init_irq(); }
&fsi_device, &mmc_device, &irda_device, &lcdc0_device, &mipidsi0_device, &sdhi0_device, &sdhi1_device, }; static struct map_desc ag5evm_io_desc[] __initdata = { /* create a 1:1 entity map for 0xe6xxxxxx * used by CPGA, INTC and PFC. */ { .virtual = 0xe6000000, .pfn = __phys_to_pfn(0xe6000000), .length = 256 << 20, .type = MT_DEVICE_NONSHARED }, }; static void __init ag5evm_map_io(void) { iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc)); /* DMA memory at 0xf6000000 - 0xffdfffff */ init_consistent_dma_size(158 << 20); /* setup early devices and console here as well */ sh73a0_add_early_devices(); shmobile_setup_console(); }
#include <mach/irqs.h> #include <mach/r8a7779.h> #include <mach/common.h> #include <mach/hpb-dmae.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/map.h> #include <asm/hardware/cache-l2x0.h> #include <asm/pmu.h> static struct map_desc r8a7779_io_desc[] __initdata = { /* 2M entity map for 0xf0000000 (MPCORE) */ { .virtual = 0xf0000000, .pfn = __phys_to_pfn(0xf0000000), .length = SZ_2M, .type = MT_DEVICE_NONSHARED }, /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ { .virtual = 0xfe000000, .pfn = __phys_to_pfn(0xfe000000), .length = SZ_16M, .type = MT_DEVICE_NONSHARED }, /* 16M entity map for 0xffxxxxxx */ { .virtual = 0xf8000000, .pfn = __phys_to_pfn(0xff000000), .length = SZ_16M,
long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr, dma_addr_t dma_addr) { return __phys_to_pfn(dma_to_phys(dev, dma_addr)); }
/* * omap_clk_init: points to a function that does the SoC-specific * clock initializations */ int (*omap_clk_init)(void); /* * The machine specific code may provide the extra mapping besides the * default mapping provided here. */ #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) static struct map_desc omap24xx_io_desc[] __initdata = { { .virtual = L3_24XX_VIRT, .pfn = __phys_to_pfn(L3_24XX_PHYS), .length = L3_24XX_SIZE, .type = MT_DEVICE }, { .virtual = L4_24XX_VIRT, .pfn = __phys_to_pfn(L4_24XX_PHYS), .length = L4_24XX_SIZE, .type = MT_DEVICE }, }; #ifdef CONFIG_SOC_OMAP2420 static struct map_desc omap242x_io_desc[] __initdata = { { .virtual = DSP_MEM_2420_VIRT,
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); pxa_set_ac97_info(NULL); if (lpd270_lcd_to_use != NULL) pxa_set_fb_info(NULL, lpd270_lcd_to_use); pxa_set_ohci_info(&lpd270_ohci_platform_data); } static struct map_desc lpd270_io_desc[] __initdata = { { .virtual = (unsigned long)LPD270_CPLD_VIRT, .pfn = __phys_to_pfn(LPD270_CPLD_PHYS), .length = LPD270_CPLD_SIZE, .type = MT_DEVICE, }, }; static void __init lpd270_map_io(void) { pxa27x_map_io(); iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); /* for use I SRAM as framebuffer. */ PSLR |= 0x00000F04; PCFR = 0x00000066; }
.name = "smsc911x", .id = -1, .num_resources = ARRAY_SIZE(smsc911x_resources), .resource = smsc911x_resources, .dev = { .platform_data = &smsc911x_config, }, }; /* * This structure defines the MX31 memory map. */ static struct map_desc mx31lite_io_desc[] __initdata = { { .virtual = SPBA0_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), .length = SPBA0_SIZE, .type = MT_DEVICE_NONSHARED }, { .virtual = CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(CS4_BASE_ADDR), .length = CS4_SIZE, .type = MT_DEVICE } }; /* * Set up static virtual mappings. */ void __init mx31lite_map_io(void) {
.dma_mask = &dm644x_video_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, }; void dm644x_set_vpbe_display_config(struct vpbe_display_config *cfg) { dm644x_vpbe_dev.dev.platform_data = cfg; } /*----------------------------------------------------------------------*/ static struct map_desc dm644x_io_desc[] = { { .virtual = IO_VIRT, .pfn = __phys_to_pfn(IO_PHYS), .length = IO_SIZE, .type = MT_DEVICE }, { .virtual = SRAM_VIRT, .pfn = __phys_to_pfn(0x00008000), .length = SZ_16K, .type = MT_MEMORY_NONCACHED, }, }; /* Contents of JTAG ID register used to identify exact cpu type */ static struct davinci_id dm644x_ids[] = { { .variant = 0x0,
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } /* Hook into PCI interrupt */ irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); } /************************************************************************* * IXDP2x00 memory map *************************************************************************/ static struct map_desc ixdp2x00_io_desc __initdata = { .virtual = IXDP2X00_VIRT_CPLD_BASE, .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE), .length = IXDP2X00_CPLD_SIZE, .type = MT_DEVICE }; void __init ixdp2x00_map_io(void) { ixp2000_map_io(); iotable_init(&ixdp2x00_io_desc, 1); } /************************************************************************* * IXDP2x00-common PCI init * * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board
/** * xilinx_irq_init() - Interrupt controller initialization for the GIC. */ static void __init xilinx_irq_init(void) { gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE); } /* The minimum devices needed to be mapped before the VM system is up and * running include the GIC, UART and Timer Counter. */ static struct map_desc io_desc[] __initdata = { { .virtual = TTC0_VIRT, .pfn = __phys_to_pfn(TTC0_PHYS), .length = SZ_4K, .type = MT_DEVICE, }, { .virtual = SCU_PERIPH_VIRT, .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), .length = SZ_8K, .type = MT_DEVICE, }, { .virtual = PL310_L2CC_VIRT, .pfn = __phys_to_pfn(PL310_L2CC_PHYS), .length = SZ_4K, .type = MT_DEVICE, }, #ifdef CONFIG_DEBUG_LL
yf255_init_ac97(); yf255_init_touchscreen(); yf255_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; /* Compensate for the nROMBT switch which swaps the flash banks */ printk(KERN_NOTICE "YF255 configured to boot from %s (bank %d)\n", flashboot?"Flash":"ROM", flashboot); yf255_flash_data[flashboot].name = "boot-rom"; (void) platform_add_devices(devices, ARRAY_SIZE(devices)); } static struct map_desc yf255_io_desc[] __initdata = { { /* CPLD */ .virtual = YF255_FPGA_VIRT, .pfn = __phys_to_pfn(YF255_FPGA_PHYS), .length = 0x00100000, .type = MT_DEVICE } }; static void __init yf255_map_io(void) { pxa_map_io(); iotable_init(yf255_io_desc, ARRAY_SIZE(yf255_io_desc)); #if 1 //zkj add start -------------------------------------- /* low power mode setting */ /* if you can make the power consumption less, change the setting below */ PGSR0 = 0xC3E39FFC; PGSR1 = 0xFCFFAB8C;
irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START); /* * Interrupts on secondary controller from 0 to 8 are routed to * source 31 on PIC. * Interrupts from 21 to 31 are routed directly to the VIC on * the corresponding number on primary controller. This is controlled * by setting PIC_ENABLEx. */ writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); } static struct map_desc versatile_io_desc[] __initdata = { { .virtual = IO_ADDRESS(VERSATILE_SYS_BASE), .pfn = __phys_to_pfn(VERSATILE_SYS_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = IO_ADDRESS(VERSATILE_SIC_BASE), .pfn = __phys_to_pfn(VERSATILE_SIC_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = IO_ADDRESS(VERSATILE_VIC_BASE), .pfn = __phys_to_pfn(VERSATILE_VIC_BASE), .length = SZ_4K, .type = MT_DEVICE }, { .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE), .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
#include <asm/page.h> #include <asm/setup.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include "common.h" /* * Map the CS89712 Ethernet port. That should be moved to the * ethernet driver, perhaps. */ static struct map_desc cdb89712_io_desc[] __initdata = { { .virtual = ETHER_BASE, .pfn =__phys_to_pfn(ETHER_START), .length = ETHER_SIZE, .type = MT_DEVICE } }; static void __init cdb89712_map_io(void) { clps711x_map_io(); iotable_init(cdb89712_io_desc, ARRAY_SIZE(cdb89712_io_desc)); } MACHINE_START(CDB89712, "Cirrus-CDB89712") /* Maintainer: Ray Lehtiniemi */ .phys_io = 0x80000000, .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,