static void psxRcntReset( u32 index ) { u32 count; if( rcnts[index].counterState == CountToTarget ) { if( rcnts[index].mode & RcCountToTarget ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; count /= rcnts[index].rate; count -= rcnts[index].target; } else { count = _psxRcntRcount( index ); } _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnTarget ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcCountEqTarget; } else if( rcnts[index].counterState == CountToOverflow ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; count /= rcnts[index].rate; count -= 0xffff; _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnOverflow ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcOverflow; } rcnts[index].mode |= RcUnknown10; psxRcntSet(); }
void psxRcntInit() { s32 i; // rcnt 0. rcnts[0].rate = 1; rcnts[0].irq = 0x10; // rcnt 1. rcnts[1].rate = 1; rcnts[1].irq = 0x20; // rcnt 2. rcnts[2].rate = 1; rcnts[2].irq = 0x40; // rcnt base. rcnts[3].rate = 1; rcnts[3].mode = RcCountToTarget; rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); for( i = 0; i < CounterQuantity; ++i ) { _psxRcntWcount( i, 0 ); } hSyncCount = 0; spuSyncCount = 0; psxRcntSet(); }
void psxRcntInit(void) { s32 i; // rcnt 0. rcnts[0].rate = 1; rcnts[0].irq = 0x10; // rcnt 1. rcnts[1].rate = 1; rcnts[1].irq = 0x20; // rcnt 2. rcnts[2].rate = 1; rcnts[2].irq = 0x40; // rcnt base. rcnts[3].rate = 1; rcnts[3].mode = RcCountToTarget; psxRcntUVtarget(); rcnts[3].target = rcnt_target; for( i = 0; i < CounterQuantity; ++i ) { _psxRcntWcount( i, 0 ); } psxRcntSet(); }
void psxRcntWcount( u32 index, u32 value ) { verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); psxRcntUpdate(); _psxRcntWcount( index, value ); psxRcntSet(); }
void psxRcntWtarget( u32 index, u32 value ) { verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); psxRcntUpdate(); rcnts[index].target = value; _psxRcntWcount( index, _psxRcntRcount( index ) ); psxRcntSet(); }
void psxRcntWmode( u32 index, u32 value ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] wmode: %x\n", index, value ); #endif psxRcntUpdate(); rcnts[index].mode = value; rcnts[index].irqState = 0; switch( index ) { case 0: if( value & Rc0PixelClock ) { rcnts[index].rate = 5; } else { rcnts[index].rate = 1; } break; case 1: if( value & Rc1HSyncClock ) { rcnts[index].rate = rcnt_target; } else { rcnts[index].rate = 1; } break; case 2: if( value & Rc2OneEighthClock ) { rcnts[index].rate = 8; } else { rcnts[index].rate = 1; } // TODO: wcount must work. if( value & Rc2Disable ) { rcnts[index].rate = 0xffffffff; } break; } _psxRcntWcount( index, 0 ); psxRcntSet(); }
void psxRcntWcount( u32 index, u32 value ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] wcount: %x\n", index, value ); #endif psxRcntUpdate(); _psxRcntWcount( index, value ); psxRcntSet(); }
void psxRcntWmode( u32 index, u32 value ) { verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); psxRcntUpdate(); rcnts[index].mode = value; rcnts[index].irqState = 0; switch( index ) { case 0: if( value & Rc0PixelClock ) { rcnts[index].rate = 5; } else { rcnts[index].rate = 1; } break; case 1: if( value & Rc1HSyncClock ) { rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); } else { rcnts[index].rate = 1; } break; case 2: if( value & Rc2OneEighthClock ) { rcnts[index].rate = 8; } else { rcnts[index].rate = 1; } // TODO: wcount must work. if( value & Rc2Disable ) { rcnts[index].rate = 0xffffffff; } break; } _psxRcntWcount( index, 0 ); psxRcntSet(); }
void psxRcntWtarget( u32 index, u32 value ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] wtarget: %x\n", index, value ); #endif psxRcntUpdate(); rcnts[index].target = value; _psxRcntWcount( index, _psxRcntRcount( index ) ); psxRcntSet(); }
static void psxRcntReset( u32 index ) { u32 count; if( rcnts[index].counterState == CountToTarget ) { if( rcnts[index].mode & RcCountToTarget ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; if (rcnts[index].rate > 1) count = UDIV(count,rcnts[index].rate); count -= rcnts[index].target; } else { count = _psxRcntRcount( index ); } _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnTarget ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] irq: %x\n", index, count ); #endif setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcCountEqTarget; } else if( rcnts[index].counterState == CountToOverflow ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; if (rcnts[index].rate > 1) count = UDIV(count,rcnts[index].rate); count -= 0xffff; _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnOverflow ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] irq: %x\n", index, count ); #endif setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcOverflow; } rcnts[index].mode |= RcUnknown10; psxRcntSet(); }