示例#1
0
文件: board.c 项目: cpdesign/barebox
static int smd_mem_init(void)
{
	arm_add_mem_device("ram0", 0x70000000, SZ_512M);
	arm_add_mem_device("ram1", 0xb0000000, SZ_512M);

	return 0;
}
示例#2
0
文件: board.c 项目: cpdesign/barebox
static int tx25_mem_init(void)
{
	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 32 * 1024 * 1024);
	arm_add_mem_device("ram0", IMX_SDRAM_CS1, 32 * 1024 * 1024);
	add_mem_device("ram0", 0x78000000, 128 * 1024,
				   IORESOURCE_MEM_WRITEABLE);

	return 0;
}
示例#3
0
文件: board.c 项目: Jokymon/barebox
static int tqma53_mem_init(void)
{
	arm_add_mem_device("ram0", 0x70000000, SZ_512M);
#ifdef CONFIG_MACH_TQMA53_1GB_RAM
	arm_add_mem_device("ram1", 0xb0000000, SZ_512M);
#endif

	return 0;
}
示例#4
0
文件: board.c 项目: Jokymon/barebox
static int tx25_mem_init(void)
{
	arm_add_mem_device("ram0", MX25_CSD0_BASE_ADDR, 32 * 1024 * 1024);
	arm_add_mem_device("ram0", MX25_CSD1_BASE_ADDR, 32 * 1024 * 1024);
	add_mem_device("ram0", 0x78000000, 128 * 1024,
				   IORESOURCE_MEM_WRITEABLE);

	return 0;
}
示例#5
0
static int a9m2440_mem_init(void)
{
	/*
	 * The special SDRAM setup code for this machine will always enable
	 * both SDRAM banks. But the second SDRAM device may not exists!
	 * So we must check here, if the second bank is populated to get the
	 * correct RAM size.
	 */
	switch (readl(S3C_BANKSIZE) & 0x7) {
	case 0:
		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024))
			s3c24xx_disable_second_sdram_bank();
		break;
	case 1:
		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024))
			s3c24xx_disable_second_sdram_bank();
		break;
	case 2:
		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024))
			s3c24xx_disable_second_sdram_bank();
		break;
	case 4:
	case 5:
	case 6:		/* not supported on this machine */
		break;
	default:
		if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024))
			s3c24xx_disable_second_sdram_bank();
		break;
	}

	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());

	return 0;
}
示例#6
0
void bcm2835_add_device_sdram(u32 size)
{
	if (!size)
		size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);

	arm_add_mem_device("ram0", BCM2835_SDRAM_BASE, size);
}
示例#7
0
文件: pcm038.c 项目: cpdesign/barebox
static int pcm038_mem_init(void)
{
	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);

	add_mem_device("ram0", 0xc8000000, 512 * 1024, /* Can be up to 2MiB */
				   IORESOURCE_MEM_WRITEABLE);
	return 0;
}
示例#8
0
void at91_add_device_sdram(u32 size)
{
	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
	add_mem_device("sram0", AT91SAM9263_SRAM0_BASE,
			AT91SAM9263_SRAM0_SIZE, IORESOURCE_MEM_WRITEABLE);
	add_mem_device("sram1", AT91SAM9263_SRAM1_BASE,
			AT91SAM9263_SRAM1_SIZE, IORESOURCE_MEM_WRITEABLE);
}
示例#9
0
static int pcaaxl2_mem_init(void)
{
	arm_add_mem_device("ram0", 0x80000000, SZ_512M);

	add_mem_device("sram0", 0x40300000, 48 * 1024,
				   IORESOURCE_MEM_WRITEABLE);
	return 0;
}
示例#10
0
文件: board.c 项目: frantony/barebox
static int pfc200_mem_init(void)
{
	if (!of_machine_is_compatible("ti,pfc200"))
		return 0;

	arm_add_mem_device("ram0", 0x80000000, SZ_256M);
	return 0;
}
示例#11
0
void at91_add_device_sdram(u32 size)
{
	if (!size)
		size = at91sam9x5_get_ddram_size();

	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
	add_mem_device("sram0", AT91SAM9X5_SRAM_BASE,
			AT91SAM9X5_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
}
示例#12
0
void at91_add_device_sdram(u32 size)
{
	if (!size)
		size = at91sama5_get_ddram_size();

	arm_add_mem_device("ram0", SAMA5_DDRCS, size);
	add_mem_device("sram0", SAMA5D3_SRAM_BASE,
			SAMA5D3_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
}
示例#13
0
static int tegra30_mem_init(void)
{
	if (!of_machine_is_compatible("nvidia,tegra30"))
		return 0;

	arm_add_mem_device("ram0", SZ_2G, tegra30_get_ramsize());

	return 0;
}
示例#14
0
static int sabrelite_mem_init(void)
{
	if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
	    !of_machine_is_compatible("fsl,imx6dl-sabrelite"))
		return 0;

	arm_add_mem_device("ram0", 0x10000000, SZ_1G);

	return 0;
}
示例#15
0
static int ep93xx_mem_init(void)
{
	arm_add_mem_device("ram0", CONFIG_EP93XX_SDRAM_BANK0_BASE,
				   CONFIG_EP93XX_SDRAM_BANK0_SIZE);
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
	arm_add_mem_device("ram1", CONFIG_EP93XX_SDRAM_BANK1_BASE,
				   CONFIG_EP93XX_SDRAM_BANK1_SIZE);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
	arm_add_mem_device("ram2", CONFIG_EP93XX_SDRAM_BANK2_BASE,
				   CONFIG_EP93XX_SDRAM_BANK2_SIZE);
#endif
#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
	arm_add_mem_device("ram3", CONFIG_EP93XX_SDRAM_BANK3_BASE,
				   CONFIG_EP93XX_SDRAM_BANK3_SIZE);
#endif

	return 0;
}
void at91_add_device_sdram(u32 size)
{
	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
	if (cpu_is_at91sam9g10())
		add_mem_device("sram0", AT91SAM9G10_SRAM_BASE,
			AT91SAM9G10_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
	else
		add_mem_device("sram0", AT91SAM9261_SRAM_BASE,
			AT91SAM9261_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
}
示例#17
0
void at91_add_device_sdram(u32 size)
{
	if (!size)
		size = at91_get_sdram_size();

	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
	if (cpu_is_at91sam9g20()) {
		add_mem_device("sram0", AT91SAM9G20_SRAM_BASE,
			AT91SAM9G20_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
	} else {
		add_mem_device("sram0", AT91SAM9260_SRAM_BASE,
			AT91SAM9260_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
	}
}
示例#18
0
static int imx25_mem_init(void)
{
#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
#define SDRAM_SIZE	64 * 1024 * 1024
#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
#define SDRAM_SIZE	128 * 1024 * 1024
#else
#error "Unsupported SDRAM type"
#endif
	arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM_SIZE);
	add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE);

	return 0;
}
示例#19
0
文件: dove.c 项目: SayCV/barebox-at91
static int dove_init_soc(void)
{
	unsigned long phys_base, phys_size;

	dove_remap_mc_regs();
	dove_init_clocks();
	add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
			   (unsigned int)DOVE_TIMER_BASE, 0x30,
			   IORESOURCE_MEM, NULL);
	dove_memory_find(&phys_base, &phys_size);
	arm_add_mem_device("ram0", phys_base, phys_size);
	dove_add_uart();

	return 0;
}
示例#20
0
static int beaglebone_mem_init(void)
{
	uint32_t sdram_size;

	if (!of_machine_is_compatible("ti,am335x-bone"))
		return 0;

	if (is_beaglebone_black())
		sdram_size = SZ_512M;
	else
		sdram_size = SZ_256M;

	arm_add_mem_device("ram0", 0x80000000, sdram_size);
	return 0;
}
示例#21
0
static int armada_370_xp_init_soc(void)
{
	unsigned long phys_base, phys_size;

	barebox_set_model("Marvell Armada 370/XP");
	barebox_set_hostname("armada");

	armada_370_xp_init_clocks();
	clkdev_add_physbase(tclk, (unsigned int)ARMADA_370_XP_TIMER_BASE, NULL);
	add_generic_device("mvebu-timer", DEVICE_ID_SINGLE, NULL,
			   (unsigned int)ARMADA_370_XP_TIMER_BASE, 0x30,
			   IORESOURCE_MEM, NULL);
	armada_370_xp_memory_find(&phys_base, &phys_size);
	arm_add_mem_device("ram0", phys_base, phys_size);
	armada_370_xp_add_uart();
	return 0;
}
示例#22
0
static int imx28_init(void)
{
	u32 reg;

	/*
	 * The default setting for the WDT is to do a POR. If the SoC is only
	 * powered via battery, then a WDT reset powers the chip down instead
	 * of resetting it. Use a software reset only.
	 */
	reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET) |
		HW_CLKCTRL_WDOG_POR_DISABLE;
	writel(reg, IMX_CCM_BASE + HW_CLKCTRL_RESET);

	restart_handler_register_fn(imx28_restart_soc);

	arm_add_mem_device("ram0", IMX_MEMORY_BASE, imx28_get_memsize());

	return 0;
}
示例#23
0
static int pcaal1_mem_init(void)
{

#ifdef CONFIG_OMAP_GPMC
    /*
     * WP is made high and WAIT1 active Low
     */
    gpmc_generic_init(0x10);
#endif
    omap3_add_sram0();


    omap_add_ram0(get_sdr_cs_size(SDRC_CS0_OSET));
    printf("found %s at SDCS0\n", size_human_readable(get_sdr_cs_size(SDRC_CS0_OSET)));

    if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0)) {
        arm_add_mem_device("ram1", get_sdr_cs1_base(), get_sdr_cs_size(SDRC_CS1_OSET));
        printf("found %s at SDCS1\n", size_human_readable(get_sdr_cs_size(SDRC_CS1_OSET)));
    }

    return 0;
}
示例#24
0
文件: board.c 项目: AubrCool/barebox
/*
 * This board can have 512MiB, 1GiB or 2GiB of SDRAM. The actual amount of SDRAM
 * is detected using mirror detection in lowlevel init and is stored in the first
 * SDRAM address from the lowlevel code.
 */
static int dfi_fs700_m60_mem_init(void)
{
	u32 memsize;

	if (!of_machine_is_compatible("dfi,fs700-m60"))
		return 0;

	memsize = *(u32 *)0x10000000;

	/* play safe if we find some corrupted amount of SDRAM */
	switch (memsize) {
	case SZ_512M:
	case SZ_1G:
	case SZ_2G:
		break;
	default:
		pr_err("unknown SDRAM size 0x%08x defaulting to 512MiB\n", memsize);
		memsize = SZ_512M;
	}

	arm_add_mem_device("ram0", 0x10000000, memsize);

	return 0;
}
示例#25
0
static int imx23_olinuxino_mem_init(void)
{
	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 64 * 1024 * 1024);

	return 0;
}
示例#26
0
static int arm2_mem_init(void)
{
	arm_add_mem_device("ram0", 0x10000000, SZ_2G);

	return 0;
}
示例#27
0
文件: tx28.c 项目: AubrCool/barebox
static int tx28_mem_init(void)
{
	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 128 * 1024 * 1024);

	return 0;
}
示例#28
0
static int mini2440_mem_init(void)
{
	arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size());

	return 0;
}
示例#29
0
static int mx23_evk_mem_init(void)
{
	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 32 * 1024 * 1024);

	return 0;
}
示例#30
0
static int sabresd_mem_init(void)
{
	arm_add_mem_device("ram0", 0x10000000, SZ_1G);

	return 0;
}