static int imx25_devices_init(void) { #ifdef CONFIG_USB /* USB does not work yet. Don't know why. Maybe * the CPLD has to be initialized. */ imx25_usb_init(); add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL); #endif imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); imx25_add_i2c0(NULL); armlinux_set_bootparams((void *)0x80000100); armlinux_set_architecture(MACH_TYPE_MX25_3DS); armlinux_set_serial(imx_uid()); return 0; }
void at91sam9m10ihd_devices_detect_hw(void) { at91sam9m10ihd_devices_detect_one("/dev/ds24310"); at91sam9m10ihd_devices_detect_one("/dev/ds24330"); pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); armlinux_set_revision(rev); armlinux_set_serial(sn); }
void at91sam9x5ek_devices_detect_hw(void) { at91sam9x5ek_devices_detect_one("/dev/ds24310"); at91sam9x5ek_devices_detect_one("/dev/ds24311"); at91sam9x5ek_devices_detect_one("/dev/ds24330"); pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); armlinux_set_revision(rev); armlinux_set_serial(sn); if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) of_register_fixup(cm_cogent_fixup); }
static int tx25_init(void) { if (!of_machine_is_compatible("karo,imx25-tx25")) return 0; gpio_fec_active(); barebox_set_hostname("tx25"); armlinux_set_architecture(MACH_TYPE_TX25); armlinux_set_serial(imx_uid()); imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot", BBU_HANDLER_FLAG_DEFAULT); return 0; }
static int tx25_devices_init(void) { gpio_fec_active(); imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); armlinux_set_bootparams((void *)0x80000100); armlinux_set_architecture(MACH_TYPE_TX25); armlinux_set_serial(imx_uid()); return 0; }
static int pcm038_devices_init(void) { int i; u64 uid = 0; char *envdev; long sram_size; unsigned int mode[] = { /* FEC */ PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, PD2_AIN_FEC_TXD2, PD3_AIN_FEC_TXD3, PD4_AOUT_FEC_RX_ER, PD5_AOUT_FEC_RXD1, PD6_AOUT_FEC_RXD2, PD7_AOUT_FEC_RXD3, PD8_AF_FEC_MDIO, PD9_AIN_FEC_MDC | GPIO_PUEN, PD10_AOUT_FEC_CRS, PD11_AOUT_FEC_TX_CLK, PD12_AOUT_FEC_RXD0, PD13_AOUT_FEC_RX_DV, PD14_AOUT_FEC_RX_CLK, PD15_AOUT_FEC_COL, PD16_AIN_FEC_TX_ER, PF23_AIN_FEC_TX_EN, PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT, /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, /* CSPI1 */ PD25_PF_CSPI1_RDY, PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT, #ifdef CONFIG_MACH_PCM970_BASEBOARD PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT, #endif /* Display */ PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD, /* USB OTG */ PC7_PF_USBOTG_DATA5, PC8_PF_USBOTG_DATA6, PC9_PF_USBOTG_DATA0, PC10_PF_USBOTG_DATA2, PC11_PF_USBOTG_DATA1, PC12_PF_USBOTG_DATA4, PC13_PF_USBOTG_DATA3, PE0_PF_USBOTG_NXT, PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT, PE2_PF_USBOTG_DIR, PE24_PF_USBOTG_CLK, PE25_PF_USBOTG_DATA7, /* I2C1 */ PD17_PF_I2C_DATA | GPIO_PUEN, PD18_PF_I2C_CLK, /* I2C2 */ PC5_PF_I2C2_SDA, PC6_PF_I2C2_SCL, }; /* configure 16 bit nor flash on cs0 */ imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900); /* configure SRAM on cs1 */ imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); /* SRAM can be up to 2MiB */ sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M); if (sram_size) add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size, IORESOURCE_MEM_WRITEABLE); /* initizalize gpios */ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); imx27_add_spi0(&pcm038_spi_0_data); pcm038_power_init(); add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); imx27_add_i2c0(NULL); imx27_add_i2c1(NULL); /* Register the fec device after the PLL re-initialisation * as the fec depends on the (now higher) ipg clock */ gpio_set_value(PCM038_GPIO_FEC_RST, 1); imx27_add_fec(&fec_info); /* Apply delay for STP line to stop ULPI */ gpio_direction_output(PCM038_GPIO_OTG_STP, 1); mdelay(1); imx_gpio_mode(PE1_PF_USBOTG_STP); imx27_add_usbotg(&pcm038_otg_pdata); switch (bootsource_get()) { case BOOTSOURCE_NAND: devfs_add_partition("nand0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); envdev = "NAND"; break; default: devfs_add_partition("nor0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); protect_file("/dev/env0", 1); envdev = "NOR"; } pr_notice("Using environment in %s Flash\n", envdev); if (imx_iim_read(1, 0, &uid, 6) == 6) armlinux_set_serial(uid); armlinux_set_bootparams((void *)0xa0000100); armlinux_set_architecture(MACH_TYPE_PCM038); return 0; }