/** * @brief Run the self calibration of one OPAMP * @note Trimming values (PMOS & NMOS) are updated and user trimming is * enabled is calibration is succesful. * @note Calibration is performed in the mode specified in OPAMP init * structure (mode normal or low-power). To perform calibration for * both modes, repeat this function twice after OPAMP init structure * accordingly updated. * @note Calibration runs about 10 ms (5 dichotmy steps, repeated for P * and N transistors: 10 steps with 1 ms for each step). * @param hopamp: handle * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled * @retval HAL status */ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp) { HAL_StatusTypeDef status = HAL_OK; uint32_t* opamp_trimmingvalue = 0; uint32_t opamp_trimmingvaluen = 0; uint32_t opamp_trimmingvaluep = 0; uint32_t trimming_diff_pair = 0; /* Selection of differential transistors pair high or low */ __IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */ uint32_t tmp_opamp_otr_otuser = 0; /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */ uint32_t tmp_Opaxcalout_DefaultSate = 0; /* Bit OPAMP_CSR_OPAXCALOUT default state when trimming value is 00000b. Used to detect the bit toggling */ uint32_t tmp_OpaxSwitchesContextBackup = 0; uint8_t trimming_diff_pair_iteration_count = 0; uint8_t delta = 0; /* Check the OPAMP handle allocation */ /* Check if OPAMP locked */ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)) { status = HAL_ERROR; } else { /* Check if OPAMP in calibration mode and calibration not yet enable */ if(hopamp->State == HAL_OPAMP_STATE_READY) { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); /* Update OPAMP state */ hopamp->State = HAL_OPAMP_STATE_CALIBBUSY; /* Backup of switches configuration to restore it at the end of the */ /* calibration. */ tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); /* Open all switches on non-inverting input, inverting input and output */ /* feedback. */ CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp)); /* Set calibration mode to user programmed trimming values */ SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); /* Select trimming settings depending on power mode */ if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) { tmp_opamp_otr_otuser = OPAMP_OTR_OT_USER; tmp_opamp_reg_trimming = &OPAMP->OTR; } else { tmp_opamp_otr_otuser = 0x00000000; tmp_opamp_reg_trimming = &OPAMP->LPOTR; } /* Enable the selected opamp */ CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); /* Perform trimming for both differential transistors pair high and low */ for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++) { if (trimming_diff_pair_iteration_count == 0) { /* Calibration of transistors differential pair high (NMOS) */ trimming_diff_pair = OPAMP_FACTORYTRIMMING_N; opamp_trimmingvalue = &opamp_trimmingvaluen; /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ /* is 00000b. Used to detect the bit toggling during trimming. */ tmp_Opaxcalout_DefaultSate = RESET; /* Enable calibration for N differential pair */ MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_L(hopamp), __OPAMP_CSR_OPAXCAL_H(hopamp) ); } else /* (trimming_diff_pair_iteration_count == 1) */ { /* Calibration of transistors differential pair low (PMOS) */ trimming_diff_pair = OPAMP_FACTORYTRIMMING_P; opamp_trimmingvalue = &opamp_trimmingvaluep; /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value */ /* is 00000b. Used to detect the bit toggling during trimming. */ tmp_Opaxcalout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp); /* Enable calibration for P differential pair */ MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_H(hopamp), __OPAMP_CSR_OPAXCAL_L(hopamp) ); } /* Perform calibration parameter search by dichotomy sweep */ /* - Delta initial value 16: for 5 dichotomy steps: 16 for the */ /* initial range, then successive delta sweeps (8, 4, 2, 1). */ /* can extend the search range to +/- 15 units. */ /* - Trimming initial value 15: search range will go from 0 to 30 */ /* (Trimming value 31 is forbidden). */ *opamp_trimmingvalue = 15; delta = 16; while (delta != 0) { /* Set candidate trimming */ MODIFY_REG(*tmp_opamp_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) , __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser); /* Offset trimming time: during calibration, minimum time needed */ /* between two steps to have 1 mV accuracy. */ HAL_Delay(OPAMP_TRIMMING_DELAY); /* Divide range by 2 to continue dichotomy sweep */ delta >>= 1; /* Set trimming values for next iteration in function of trimming */ /* result toggle (versus initial state). */ if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate) { /* If calibration output is has toggled, try lower trimming */ *opamp_trimmingvalue -= delta; } else { /* If calibration output is has not toggled, try higher trimming */ *opamp_trimmingvalue += delta; } } } /* Disable calibration for P and N differential pairs */ /* Disable the selected opamp */ CLEAR_BIT (OPAMP->CSR, (__OPAMP_CSR_OPAXCAL_H(hopamp) | __OPAMP_CSR_OPAXCAL_L(hopamp) | __OPAMP_CSR_OPAXPD(hopamp)) ); /* Backup of switches configuration to restore it at the end of the */ /* calibration. */ SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup); /* Self calibration is successful */ /* Store calibration (user trimming) results in init structure. */ /* Set user trimming mode */ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER; /* Affect calibration parameters depending on mode normal/low power */ if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) { /* Write calibration result N */ hopamp->Init.TrimmingValueN = opamp_trimmingvaluen; /* Write calibration result P */ hopamp->Init.TrimmingValueP = opamp_trimmingvaluep; } else { /* Write calibration result N */ hopamp->Init.TrimmingValueNLowPower = opamp_trimmingvaluen; /* Write calibration result P */ hopamp->Init.TrimmingValuePLowPower = opamp_trimmingvaluep; } /* Update OPAMP state */ hopamp->State = HAL_OPAMP_STATE_READY; } else {
/** * @brief Sets IWDG Prescaler value. * @param IWDG_Prescaler: specifies the IWDG Prescaler value. * This parameter can be one of the following values: * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 * @retval : None */ void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) { /* Check the parameters */ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); IWDG->PR = IWDG_Prescaler; }
/** * @brief Enables or disables write access to IWDG_PR and IWDG_RLR * registers. * @param IWDG_WriteAccess: new state of write access to IWDG_PR and * IWDG_RLR registers. * This parameter can be one of the following values: * @arg IWDG_WriteAccess_Enable: Enable write access to * IWDG_PR and IWDG_RLR registers * @arg IWDG_WriteAccess_Disable: Disable write access to * IWDG_PR and IWDG_RLR registers * @retval : None */ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) { /* Check the parameters */ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); IWDG->KR = IWDG_WriteAccess; }
/** * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. * This parameter can be one of the following values: * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers * @retval None */ void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess) { /* Check the parameters */ assert_param(IS_IWDG_WRITE_ACCESS_MODE(IWDG_WriteAccess)); IWDG->KR = IWDG_WriteAccess; /* Write Access */ }
/** * @brief Initializes the LPTIM according to the specified parameters in the * LPTIM_InitTypeDef and creates the associated handle. * @param hlptim: LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { uint32_t tmpcfgr = 0; /* Check the LPTIM handle allocation */ if(hlptim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); if(hlptim->State == HAL_LPTIM_STATE_RESET) { /* Allocate lock resource and initialize it */ hlptim->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_LPTIM_MspInit(hlptim); } /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE )); /* Set initialization parameters */ tmpcfgr |= (hlptim->Init.Clock.Source | hlptim->Init.Clock.Prescaler | hlptim->Init.OutputPolarity | hlptim->Init.UpdateMode | hlptim->Init.CounterSource); if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) { tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | hlptim->Init.UltraLowPowerClock.SampleTime); } if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ tmpcfgr |= (hlptim->Init.Trigger.Source | hlptim->Init.Trigger.ActiveEdge | hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ hlptim->Instance->CFGR = tmpcfgr; /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; }
/** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { __IO uint32_t counter = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); /* Process locked */ __HAL_LOCK(hadc); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ hadc->Instance->CR2 |= ADC_CR2_DMA; /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Enable the DMA Stream */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_REG; /* Process unlocked */ __HAL_UNLOCK(hadc); /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) { counter--; } } /* if no external trigger present enable software conversion of regular channels */ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= ADC_CR2_SWSTART; } /* Return function status */ return HAL_OK; }
/** * @brief Initializes the LCD peripheral according to the specified parameters * in the LCD_InitStruct. * @note This function can be used only when the LCD is disabled. * The LCD HighDrive can be enabled/disabled using related macros up to user. * @param hlcd: LCD handle * @retval None */ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) { uint32_t tickstart = 0x00; uint8_t counter = 0; /* Check the LCD handle allocation */ if(hlcd == NULL) { return HAL_ERROR; } /* Check function parameters */ assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler)); assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider)); assert_param(IS_LCD_DUTY(hlcd->Init.Duty)); assert_param(IS_LCD_BIAS(hlcd->Init.Bias)); assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource)); assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration)); assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive)); assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime)); assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment)); if(hlcd->State == HAL_LCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hlcd->Lock = HAL_UNLOCKED; /* Initialize the low level hardware (MSP) */ HAL_LCD_MspInit(hlcd); } hlcd->State = HAL_LCD_STATE_BUSY; /* Disable the peripheral */ __HAL_LCD_DISABLE(hlcd); /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit in the LCD_SR register */ for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) { hlcd->Instance->RAM[counter] = 0; } /* Enable the display request */ SET_BIT(hlcd->Instance->SR, LCD_SR_UDR); /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: Set PS[3:0] bits according to hlcd->Init.Prescaler value Set DIV[3:0] bits according to hlcd->Init.Divider value Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value Set DEAD[2:0] bits according to hlcd->Init.DeadTime value Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value Set CC[2:0] bits according to hlcd->Init.Contrast value Set HD[0] bit according to hlcd->Init.HighDrive value */ MODIFY_REG(hlcd->Instance->FCR, \ (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \ (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive)); /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.*/ LCD_WaitForSynchro(hlcd); /* Configure the LCD Duty, Bias, Voltage Source, Dead Time: Set DUTY[2:0] bits according to hlcd->Init.Duty value Set BIAS[1:0] bits according to hlcd->Init.Bias value Set VSEL bit according to hlcd->Init.VoltageSource value Set MUX_SEG bit according to hlcd->Init.MuxSegment value */ MODIFY_REG(hlcd->Instance->CR, \ (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \ (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment)); /* Enable the peripheral */ __HAL_LCD_ENABLE(hlcd); /* Get timeout */ tickstart = HAL_GetTick(); /* Wait Until the LCD is enabled */ while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) { if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_ENS; return HAL_TIMEOUT; } } /* Get timeout */ tickstart = HAL_GetTick(); /*!< Wait Until the LCD Booster is ready */ while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) { if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_RDY; return HAL_TIMEOUT; } } /* Initialize the LCD state */ hlcd->ErrorCode = HAL_LCD_ERROR_NONE; hlcd->State= HAL_LCD_STATE_READY; return HAL_OK; }
/******************************************************************************* * Function Name : CAN_Transmit * Description : Initiates the transmission of a message. * Input : TxMessage: pointer to a structure which contains CAN Id, CAN * DLC and CAN datas. * Output : None. * Return : The number of the mailbox that is used for transmission * or CAN_NO_MB if there is no empty mailbox. *******************************************************************************/ u8 CAN_Transmit(CanTxMsg* TxMessage) { u8 TransmitMailbox = 0; /* Check the parameters */ assert_param(IS_CAN_STDID(TxMessage->StdId)); assert_param(IS_CAN_EXTID(TxMessage->StdId)); assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); assert_param(IS_CAN_RTR(TxMessage->RTR)); assert_param(IS_CAN_DLC(TxMessage->DLC)); /* Select one empty transmit mailbox */ if ((CAN->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { TransmitMailbox = 0; } else if ((CAN->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) { TransmitMailbox = 1; } else if ((CAN->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) { TransmitMailbox = 2; } else { TransmitMailbox = CAN_NO_MB; } if (TransmitMailbox != CAN_NO_MB) { /* Set up the Id */ CAN->sTxMailBox[TransmitMailbox].TIR &= CAN_TMIDxR_TXRQ; if (TxMessage->IDE == CAN_ID_STD) { TxMessage->StdId &= (u32)0x000007FF; TxMessage->StdId = TxMessage->StdId << 21; CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->StdId | TxMessage->IDE | TxMessage->RTR); } else { TxMessage->ExtId &= (u32)0x1FFFFFFF; TxMessage->ExtId <<= 3; CAN->sTxMailBox[TransmitMailbox].TIR |= (TxMessage->ExtId | TxMessage->IDE | TxMessage->RTR); } /* Set up the DLC */ TxMessage->DLC &= (u8)0x0000000F; CAN->sTxMailBox[TransmitMailbox].TDTR &= (u32)0xFFFFFFF0; CAN->sTxMailBox[TransmitMailbox].TDTR |= TxMessage->DLC; /* Set up the data field */ CAN->sTxMailBox[TransmitMailbox].TDLR = (((u32)TxMessage->Data[3] << 24) | ((u32)TxMessage->Data[2] << 16) | ((u32)TxMessage->Data[1] << 8) | ((u32)TxMessage->Data[0])); CAN->sTxMailBox[TransmitMailbox].TDHR = (((u32)TxMessage->Data[7] << 24) | ((u32)TxMessage->Data[6] << 16) | ((u32)TxMessage->Data[5] << 8) | ((u32)TxMessage->Data[4])); /* Request transmission */ CAN->sTxMailBox[TransmitMailbox].TIR |= CAN_TMIDxR_TXRQ; } return TransmitMailbox; }
/** * @brief Enables or disables the Power Voltage Detector(PVD). * @param NewState: new state of the PVD. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_PVDCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; }
/******************************************************************************* * Function Name : CAN_Init * Description : Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains the configuration information for the CAN peripheral. * Output : None. * Return : Constant indicates initialization succeed which will be * CANINITFAILED or CANINITOK. *******************************************************************************/ u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct) { u8 InitStatus = 0; u16 WaitAck; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); /* Request initialisation */ CAN->MCR = CAN_MCR_INRQ; /* ...and check acknowledged */ if ((CAN->MSR & CAN_MSR_INAK) == 0) { InitStatus = CANINITFAILED; } else { /* Set the time triggered communication mode */ if (CAN_InitStruct->CAN_TTCM == ENABLE) { CAN->MCR |= CAN_MCR_TTCM; } else { CAN->MCR &= ~CAN_MCR_TTCM; } /* Set the automatic bus-off management */ if (CAN_InitStruct->CAN_ABOM == ENABLE) { CAN->MCR |= CAN_MCR_ABOM; } else { CAN->MCR &= ~CAN_MCR_ABOM; } /* Set the automatic wake-up mode */ if (CAN_InitStruct->CAN_AWUM == ENABLE) { CAN->MCR |= CAN_MCR_AWUM; } else { CAN->MCR &= ~CAN_MCR_AWUM; } /* Set the no automatic retransmission */ if (CAN_InitStruct->CAN_NART == ENABLE) { CAN->MCR |= CAN_MCR_NART; } else { CAN->MCR &= ~CAN_MCR_NART; } /* Set the receive FIFO locked mode */ if (CAN_InitStruct->CAN_RFLM == ENABLE) { CAN->MCR |= CAN_MCR_RFLM; } else { CAN->MCR &= ~CAN_MCR_RFLM; } /* Set the transmit FIFO priority */ if (CAN_InitStruct->CAN_TXFP == ENABLE) { CAN->MCR |= CAN_MCR_TXFP; } else { CAN->MCR &= ~CAN_MCR_TXFP; } /* Set the bit timing register */ CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) | ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) | ((u32)CAN_InitStruct->CAN_Prescaler - 1); InitStatus = CANINITOK; /* Request leave initialisation */ CAN->MCR &= ~CAN_MCR_INRQ; /* Wait the acknowledge */ for(WaitAck = 0x400; WaitAck > 0x0; WaitAck--) { } /* ...and check acknowledged */ if ((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { InitStatus = CANINITFAILED; } } /* At this step, return the status of initialization */ return InitStatus; }
/******************************************************************************* * Function Name : CAN_FilterInit * Description : Initializes the CAN peripheral according to the specified * parameters in the CAN_FilterInitStruct. * Input : CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef * structure that contains the configuration information. * Output : None. * Return : None. *******************************************************************************/ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) { u16 FilterNumber_BitPos = 0; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); FilterNumber_BitPos = (u16)((u16)0x0001 << ((u16)CAN_FilterInitStruct->CAN_FilterNumber)); /* Initialisation mode for the filter */ CAN->FMR |= CAN_FMR_FINIT; /* Filter Deactivation */ CAN->FA1R &= ~(u32)FilterNumber_BitPos; /* Filter Scale */ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) { /* 16-bit scale for the filter */ CAN->FS1R &= ~(u32)FilterNumber_BitPos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh); } if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) { /* 32-bit scale for the filter */ CAN->FS1R |= FilterNumber_BitPos; /* 32-bit identifier or First 32-bit identifier */ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((u32)((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | ((u32)0x0000FFFF & CAN_FilterInitStruct->CAN_FilterMaskIdLow); } /* Filter Mode */ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) { /*Id/Mask mode for the filter*/ CAN->FM1R &= ~(u32)FilterNumber_BitPos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ CAN->FM1R |= (u32)FilterNumber_BitPos; } /* Filter FIFO assignment */ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) { /* FIFO 0 assignation for the filter */ CAN->FFA1R &= ~(u32)FilterNumber_BitPos; } if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) { /* FIFO 1 assignation for the filter */ CAN->FFA1R |= (u32)FilterNumber_BitPos; } /* Filter activation */ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) { CAN->FA1R |= FilterNumber_BitPos; } /* Leave the initialisation mode for the filter */ CAN->FMR &= ~CAN_FMR_FINIT; }
/** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param sConfigInjected: ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { #ifdef USE_FULL_ASSERT uint32_t tmp = 0; #endif /* USE_FULL_ASSERT */ /* Check the parameters */ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); #ifdef USE_FULL_ASSERT tmp = ADC_GET_RESOLUTION(hadc); assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); #endif /* USE_FULL_ASSERT */ if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START) { assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } /* Process locked */ __HAL_LOCK(hadc); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) { /* Clear the old sample time */ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); /* Set the new sample time */ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Clear the old sample time */ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); /* Set the new sample time */ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } /*---------------------------- ADCx JSQR Configuration -----------------*/ hadc->Instance->JSQR &= ~(ADC_JSQR_JL); hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); /* Rank configuration */ /* Clear the old SQx bits for the selected rank */ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); /* Set the SQx bits for the selected rank */ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; /* Select external trigger polarity */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; } else { /* Reset the external trigger */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); } if (sConfigInjected->AutoInjectedConv != DISABLE) { /* Enable the selected ADC automatic injected group conversion */ hadc->Instance->CR1 |= ADC_CR1_JAUTO; } else { /* Disable the selected ADC automatic injected group conversion */ hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); } if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) { /* Enable the selected ADC injected discontinuous mode */ hadc->Instance->CR1 |= ADC_CR1_JDISCEN; } else { /* Disable the selected ADC injected discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); } switch(sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; break; case 2: /* Set injected channel 2 offset */ hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; break; case 3: /* Set injected channel 3 offset */ hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; break; default: /* Set injected channel 4 offset */ hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; break; } /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) { /* Enable the VBAT channel*/ ADC->CCR |= ADC_CCR_VBATE; } /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) { /* Enable the TSVREFE channel*/ ADC->CCR |= ADC_CCR_TSVREFE; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; }
/** * @brief Enables WWDG and load the counter value. * @param Counter: specifies the watchdog counter value. * This parameter must be a number between 0x40 and 0x7F (to prevent * generating an immediate reset). * @retval None */ void WWDG_Enable(uint8_t Counter) { /* Check the parameters */ assert_param(IS_WWDG_COUNTER(Counter)); WWDG->CR = WWDG_CR_WDGA | Counter; }
void CRG_SetMonitoringClock(uint32_t value) { assert_param(IS_CRG_MONCLK_SSR(value)); CRG->MONCLK_SSR = value; }
/** * @brief Enables the interrupt and starts ADC conversion of regular channels. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { __IO uint32_t counter = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); /* Process locked */ __HAL_LOCK(hadc); /* Check if an injected conversion is ongoing */ if(hadc->State == HAL_ADC_STATE_BUSY_INJ) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_REG; } /* Set ADC error code to none */ hadc->ErrorCode = HAL_ADC_ERROR_NONE; /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) { counter--; } } /* Enable the ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable the ADC end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Check if Multimode enabled */ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) { /* if no external trigger present enable software conversion of regular channels */ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } /* Return function status */ return HAL_OK; }
/** * @brief Enables or disables the WakeUp Pin functionality. * @param NewState: new state of the WakeUp Pin functionality. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_WakeUpPinCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; }
/** * @brief Handles ADC interrupt request * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); /* Check End of conversion flag for regular channels */ if(tmp1 && tmp2) { /* Check if an injected conversion is ready */ if(hadc->State == HAL_ADC_STATE_EOC_INJ) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_REG; } if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { /* DISABLE the ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* DISABLE the ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); } else { if (hadc->NbrOfCurrentConversionRank == 0) { hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion; } /* Decrement the number of conversion when an interrupt occurs */ hadc->NbrOfCurrentConversionRank--; /* Check if all conversions are finished */ if(hadc->NbrOfCurrentConversionRank == 0) { /* DISABLE the ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* DISABLE the ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); } } } /* Conversion complete callback */ HAL_ADC_ConvCpltCallback(hadc); /* Clear the ADCx flag for regular end of conversion */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); /* Check End of conversion flag for injected channels */ if(tmp1 && tmp2) { /* Check if a regular conversion is ready */ if(hadc->State == HAL_ADC_STATE_EOC_REG) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ; } tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2) { /* DISABLE the ADC end of conversion interrupt for injected group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); } /* Conversion complete callback */ HAL_ADCEx_InjectedConvCpltCallback(hadc); /* Clear the ADCx flag for injected end of conversion */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); /* Check Analog watchdog flag */ if(tmp1 && tmp2) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_AWD; /* Clear the ADCx's Analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); /* Level out of window callback */ HAL_ADC_LevelOutOfWindowCallback(hadc); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); /* Check Overrun flag */ if(tmp1 && tmp2) { /* Change ADC state to overrun state */ hadc->State = HAL_ADC_STATE_ERROR; /* Set ADC error code to overrun */ hadc->ErrorCode |= HAL_ADC_ERROR_OVR; /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR); /* Error callback */ HAL_ADC_ErrorCallback(hadc); } }
int uart_close(USART_TypeDef* USARTx) { assert_param(IS_USART_123_PERIPH(USARTx)); }
/** * @brief Initializes the TSC peripheral according to the specified parameters * in the TSC_InitTypeDef structure. * @param htsc: TSC handle * @retval HAL status */ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) { /* Check TSC handle allocation */ if (htsc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength)); assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength)); assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum)); assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation)); assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler)); assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler)); assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue)); assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode)); assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode)); assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_BUSY; /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_TSC_MspInit(htsc); /*--------------------------------------------------------------------------*/ /* Set TSC parameters */ /* Enable TSC */ htsc->Instance->CR = TSC_CR_TSCE; /* Set all functions */ htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | htsc->Init.CTPulseLowLength | (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) | htsc->Init.SpreadSpectrumPrescaler | htsc->Init.PulseGeneratorPrescaler | htsc->Init.MaxCountValue | htsc->Init.IODefaultMode | htsc->Init.SynchroPinPolarity | htsc->Init.AcquisitionMode); /* Spread spectrum */ if (htsc->Init.SpreadSpectrum == ENABLE) { htsc->Instance->CR |= TSC_CR_SSE; } /* Disable Schmitt trigger hysteresis on all used TSC IOs */ htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs)); /* Set channel and shield IOs */ htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs); /* Set sampling IOs */ htsc->Instance->IOSCR = htsc->Init.SamplingIOs; /* Set the groups to be acquired */ htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs); /* Clear interrupts */ htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE)); /* Clear flags */ htsc->Instance->ICR |= (TSC_FLAG_EOA | TSC_FLAG_MCE); /*--------------------------------------------------------------------------*/ /* Initialize the TSC state */ htsc->State = HAL_TSC_STATE_READY; /* Return function status */ return HAL_OK; }
int uart_open (USART_TypeDef* USARTx, uint32_t baud, uint32_t flags) { USART_InitTypeDef USART_InitStructure; GPIO_InitTypeDef GPIO_InitStructureTx; GPIO_InitTypeDef GPIO_InitStructureRx; assert_param(IS_USART_123_PERIPH(USARTx)); if (USARTx == USART1) { // Turn on clocks /*RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_AFIO, ENABLE); */ //manual RCC->APB2ENR |= ( RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN ); //RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); //manual RCC->APB2ENR |= RCC_APB2ENR_USART1EN; // Configure TX pin /* GPIO_InitStructureTx.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructureTx.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructureTx.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(GPIOA, &GPIO_InitStructureTx); */ //manual GPIOA->CRH |= ( GPIO_CRH_CNF9_1 | GPIO_CRH_MODE9 ); //GPIO_CRH_MODE9 does GPIO_CRH_MODE9_1 and 0. GPIOA->CRH &= ~GPIO_CRH_CNF9_0; //just make sure // Configure RX pin /* GPIO_InitStructureRx.GPIO_Pin = GPIO_Pin_10; GPIO_InitStructureRx.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOA, &GPIO_InitStructureRx); */ //manual GPIOA->CRH |= ( GPIO_CRH_CNF10_0 ); GPIOA->CRH &= ~( GPIO_CRH_MODE10 | GPIO_CRH_CNF10_1 ); //make sure disabled so it is an input and floating // Configure the UART /* USART_StructInit(&USART_InitStructure); USART_InitStructure.USART_BaudRate = baud; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_Init(USART1,&USART_InitStructure); USART_Cmd(USART1, ENABLE); */ USART1->BRR = SystemCoreClock/baud; USART1->CR1 |= ( USART_CR1_RE | USART_CR1_TE ); //enable rx and tx USART1->CR1 |= USART_CR1_UE; //enable uart return 0; } }
/** * @brief Initialize LPUART registers according to the specified * parameters in LPUART_InitStruct. * @note As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), * LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). * @param LPUARTx LPUART Instance * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure * that contains the configuration information for the specified LPUART peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content * - ERROR: Problem occurred during LPUART Registers initialization */ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; /* Check the parameters */ assert_param(IS_LPUART_INSTANCE(LPUARTx)); #if defined(USART_PRESC_PRESCALER) assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); #endif assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity)); assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); /* LPUART needs to be in disabled state, in order to be able to configure some bits in CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ if (LL_LPUART_IsEnabled(LPUARTx) == 0U) { /*---------------------------- LPUART CR1 Configuration ----------------------- * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters: * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value */ MODIFY_REG(LPUARTx->CR1, (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection)); /*---------------------------- LPUART CR2 Configuration ----------------------- * Configure LPUARTx CR2 (Stop bits) with parameters: * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value. */ LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits); /*---------------------------- LPUART CR3 Configuration ----------------------- * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value. */ LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); /*---------------------------- LPUART BRR Configuration ----------------------- * Retrieve Clock frequency used for LPUART Peripheral */ periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); /* Configure the LPUART Baud Rate : #if defined(USART_PRESC_PRESCALER) - prescaler value is required #endif - valid baud rate value (different from 0) is required - Peripheral clock as returned by RCC service, should be valid (different from 0). */ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) && (LPUART_InitStruct->BaudRate != 0U)) { status = SUCCESS; LL_LPUART_SetBaudRate(LPUARTx, periphclk, #if defined(USART_PRESC_PRESCALER) LPUART_InitStruct->PrescalerValue, #endif LPUART_InitStruct->BaudRate); /* Check BRR is greater than or equal to 0x300 */ assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR)); } #if defined(USART_PRESC_PRESCALER) /*---------------------------- LPUART PRESC Configuration ----------------------- * Configure LPUARTx PRESC (Prescaler) with parameters: * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. */ LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); #endif } return (status); }
void I2C_Enable(I2C0_Type* I2Cx, BOOL enable) { assert_param(IS_I2C_ALL_PERIPH(I2Cx)); I2Cx->ENABLE_b.EN = enable; }
/** * @brief Sets IWDG Prescaler value. * @param IWDG_Prescaler: specifies the IWDG Prescaler value. * This parameter can be one of the following values: * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 * @retval None */ void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler) { /* Check the parameters */ assert_param(IS_IWDG_PRESCALER_VALUE(IWDG_Prescaler)); IWDG->PR = IWDG_Prescaler; }
/** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param sConfig: ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { __IO uint32_t counter = 0; /* Check the parameters */ assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (sConfig->Channel > ADC_CHANNEL_9) { /* Clear the old sample time */ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); /* Set the new sample time */ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Clear the old sample time */ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); /* Set the new sample time */ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); } /* For Rank 1 to 6 */ if (sConfig->Rank < 7) { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); /* Set the SQx bits for the selected rank */ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); } /* For Rank 7 to 12 */ else if (sConfig->Rank < 13) { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); /* Set the SQx bits for the selected rank */ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); } /* For Rank 13 to 16 */ else { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); /* Set the SQx bits for the selected rank */ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); } /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) { /* Enable the VBAT channel*/ ADC->CCR |= ADC_CCR_VBATE; } /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) { /* Enable the TSVREFE channel*/ ADC->CCR |= ADC_CCR_TSVREFE; if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) { counter--; } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; }
/** * @brief Initializes the COMP according to the specified * parameters in the COMP_InitTypeDef and create the associated handle. * @note If the selected comparator is locked, initialization can't be performed. * To unlock the configuration, perform a system reset. * @param hcomp: COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET)) { status = HAL_ERROR; } else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput)); assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput)); assert_param(IS_COMP_NONINVERTINGINPUT_INSTANCE(hcomp->Instance, hcomp->Init.NonInvertingInput)); assert_param(IS_COMP_OUTPUT(hcomp->Init.Output)); assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_MODE(hcomp->Init.Mode)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_BLANKINGSRCE_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED) { assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance)); } if(hcomp->State == HAL_COMP_STATE_RESET) { /* Init SYSCFG and the low level hardware to access comparators */ __SYSCFG_CLK_ENABLE(); HAL_COMP_MspInit(hcomp); } /* Set COMP parameters */ /* Set COMPxINSEL bits according to hcomp->Init.InvertingInput value */ /* Set COMPxNONINSEL bits according to hcomp->Init.NonInvertingInput value */ /* Set COMPxBLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set COMPxOUTSEL bits according to hcomp->Init.Output value */ /* Set COMPxPOL bit according to hcomp->Init.OutputPol value */ /* Set COMPxHYST bits according to hcomp->Init.Hysteresis value */ /* Set COMPxMODE bits according to hcomp->Init.Mode value */ COMP_INIT(hcomp); /* Initialize the COMP state*/ if(hcomp->State == HAL_COMP_STATE_RESET) { hcomp->State = HAL_COMP_STATE_READY; } } return status; }
/** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct without initializing the ADC MSP. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ static void ADC_Init(ADC_HandleTypeDef* hadc) { /* Set ADC parameters */ /* Set the ADC clock prescaler */ ADC->CCR &= ~(ADC_CCR_ADCPRE); ADC->CCR |= hadc->Init.ClockPrescaler; /* Set ADC scan mode */ hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); /* Set ADC resolution */ hadc->Instance->CR1 &= ~(ADC_CR1_RES); hadc->Instance->CR1 |= hadc->Init.Resolution; /* Set ADC data alignment */ hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); hadc->Instance->CR2 |= hadc->Init.DataAlign; /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; /* Select external trigger polarity */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; } else { /* Reset the external trigger */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); } /* Enable or disable ADC continuous conversion mode */ hadc->Instance->CR2 &= ~(ADC_CR2_CONT); hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode); if(hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); /* Enable the selected ADC regular discontinuous mode */ hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; /* Set the number of channels to be converted in discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); } else { /* Disable the selected ADC regular discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); } /* Set ADC number of conversion */ hadc->Instance->SQR1 &= ~(ADC_SQR1_L); hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); /* Enable or disable ADC DMA continuous request */ hadc->Instance->CR2 &= ~(ADC_CR2_DDS); hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests); /* Enable or disable ADC end of conversion selection */ hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); }
/** * @brief Sets IWDG Reload value. * @param Reload: specifies the IWDG Reload value. * This parameter must be a number between 0 and 0x0FFF. * @retval : None */ void IWDG_SetReload(uint16_t Reload) { /* Check the parameters */ assert_param(IS_IWDG_RELOAD(Reload)); IWDG->RLR = Reload; }
/** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct and initializes the ADC MSP. * * @note This function is used to configure the global features of the ADC ( * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, * the rest of the configuration parameters are specific to the regular * channels group (scan mode activation, continuous mode activation, * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). * * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); } if(hadc->State == HAL_ADC_STATE_RESET) { /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_ADC_MspInit(hadc); } /* Initialize the ADC state */ hadc->State = HAL_ADC_STATE_BUSY; /* Set ADC parameters */ ADC_Init(hadc); /* Set ADC error code to none */ hadc->ErrorCode = HAL_ADC_ERROR_NONE; /* Initialize the ADC state */ hadc->State = HAL_ADC_STATE_READY; /* Release Lock */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; }
/** * @brief Enables DAC and starts conversion of channel. * Note: For STM32F100x devices with specific feature: DMA underrun. * On these devices, this function enables the interruption of DMA * underrun. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @param pData: The destination peripheral Buffer address. * @param Length: The length of data to be transferred from memory to DAC peripheral * @param Alignment: Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if(Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); /* Case of use of channel 1 */ switch(Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R1; break; case DAC_ALIGN_12B_L: /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; case DAC_ALIGN_8B_R: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; default: break; } } else { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Case of use of channel 2 */ switch(Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R2; break; case DAC_ALIGN_12B_L: /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; case DAC_ALIGN_8B_R: /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; default: break; } } /* Enable the DMA channel */ if(Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA channel */ HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Enable the Peripharal */ __HAL_DAC_ENABLE(hdac, Channel); /* Process Unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Initializes the OPAMP according to the specified * parameters in the OPAMP_InitTypeDef and create the associated handle. * @note If the selected opamp is locked, initialization can't be performed. * To unlock the configuration, perform a system reset. * @param hopamp: OPAMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmp_csr = 0; /* Temporary variable to update register CSR, except bits ANAWSSELx, S7SEL2, OPA_RANGE, OPAxCALOUT */ /* Check the OPAMP handle allocation and lock status */ /* Init not allowed if calibration is ongoing */ if((hopamp == NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) ) { status = HAL_ERROR; } else { /* Check the parameter */ assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); /* Set OPAMP parameters */ assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode)); assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput)); assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode)); assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange)); assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); if (hopamp->Init.Mode != OPAMP_FOLLOWER_MODE) { assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput)); } if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL) { assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP)); assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN)); } else { assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower)); assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower)); } } /* Call MSP init function */ HAL_OPAMP_MspInit(hopamp); /* Set OPAMP parameters */ /* - Set internal switches in function of: */ /* - OPAMP selected mode: standalone or follower. */ /* - Non-inverting input connection */ /* - Inverting input connection */ /* - Set power supply range */ /* - Set power mode and associated calibration parameters */ /* Get OPAMP CSR register into temporary variable */ tmp_csr = OPAMP->CSR; /* Open all switches on non-inverting input, inverting input and output */ /* feedback. */ CLEAR_BIT(tmp_csr, __OPAMP_CSR_ALL_SWITCHES(hopamp)); /* Set internal switches in function of OPAMP mode selected: standalone */ /* or follower. */ /* If follower mode is selected, feedback switch S3 is closed and */ /* inverting inputs switches are let opened. */ /* If standalone mode is selected, feedback switch S3 is let opened and */ /* the selected inverting inputs switch is closed. */ if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE) { /* Follower mode: Close switches S3 and SanB */ SET_BIT(tmp_csr, __OPAMP_CSR_S3SELX(hopamp)); } else { /* Set internal switches in function of inverting input selected: */ /* Close switch to connect comparator inverting input to the selected */ /* input: dedicated IO pin or alternative IO pin available on some */ /* device packages. */ if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_VM0) { /* Close switch to connect comparator non-inverting input to */ /* dedicated IO pin low-leakage. */ SET_BIT(tmp_csr, __OPAMP_CSR_S4SELX(hopamp)); } else { /* Close switch to connect comparator inverting input to alternative */ /* IO pin available on some device packages. */ SET_BIT(tmp_csr, __OPAMP_CSR_ANAWSELX(hopamp)); } } /* Set internal switches in function of non-inverting input selected: */ /* Close switch to connect comparator non-inverting input to the selected */ /* input: dedicated IO pin or DAC channel. */ if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_VP0) { /* Close switch to connect comparator non-inverting input to */ /* dedicated IO pin low-leakage. */ SET_BIT(tmp_csr, __OPAMP_CSR_S5SELX(hopamp)); } else if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_DAC_CH1) { /* Particular case for connection to DAC channel 1: */ /* OPAMP_NONINVERTINGINPUT_DAC_CH1 available on OPAMP1 and OPAMP2 only */ /* (OPAMP3 availability depends on device category). */ if ((hopamp->Instance == OPAMP1) || (hopamp->Instance == OPAMP2)) { /* Close switch to connect comparator non-inverting input to */ /* DAC channel 1. */ SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); } else { /* Set HAL status to error if another OPAMP instance as OPAMP1 or */ /* OPAMP2 is intended to be connected to DAC channel 2. */ status = HAL_ERROR; } } else /* if (hopamp->Init.NonInvertingInput == */ /* OPAMP_NONINVERTINGINPUT_DAC_CH2 ) */ { /* Particular case for connection to DAC channel 2: */ /* OPAMP_NONINVERTINGINPUT_DAC_CH2 available on OPAMP2 and OPAMP3 only */ /* (OPAMP3 availability depends on device category). */ if (hopamp->Instance == OPAMP2) { /* Close switch to connect comparator non-inverting input to */ /* DAC channel 2. */ SET_BIT(tmp_csr, OPAMP_CSR_S7SEL2); } /* If OPAMP3 is selected (if available) */ else if (hopamp->Instance != OPAMP1) { /* Close switch to connect comparator non-inverting input to */ /* DAC channel 2. */ SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp)); } else { /* Set HAL status to error if another OPAMP instance as OPAMP2 or */ /* OPAMP3 (if available) is intended to be connected to DAC channel 2.*/ status = HAL_ERROR; } } /* Continue OPAMP configuration if settings of switches are correct */ if (status != HAL_ERROR) { /* Set power mode and associated calibration parameters */ if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER) { /* Set normal mode */ CLEAR_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { /* Set calibration mode (factory or user) and values for */ /* transistors differential pair high (PMOS) and low (NMOS) for */ /* normal mode. */ MODIFY_REG(OPAMP->OTR, OPAMP_OTR_OT_USER | __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , hopamp->Init.UserTrimming | __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) | __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP) ); } else { /* Set calibration mode to factory */ CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); } } else { /* Set low power mode */ SET_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp)); if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) { /* Set calibration mode to user trimming */ SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); /* Set values for transistors differential pair high (PMOS) and low */ /* (NMOS) for low power mode. */ MODIFY_REG(OPAMP->LPOTR, __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK) | __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK) , __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) | __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower) ); } else { /* Set calibration mode to factory trimming */ CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER); } } /* Configure the power supply range */ MODIFY_REG(tmp_csr, OPAMP_CSR_AOP_RANGE, hopamp->Init.PowerSupplyRange); /* Set OPAMP CSR register from temporary variable */ /* This allows to apply all changes on one time, in case of update on */ /* the fly with OPAMP previously set and running: */ /* - to avoid hazardous transient switches settings (risk of short */ /* circuit) */ /* - to avoid interruption of input signal */ OPAMP->CSR = tmp_csr; /* Update the OPAMP state */ /* If coming from state reset: Update from state RESET to state READY */ /* else: remain in state READY or BUSY (no update) */ if (hopamp->State == HAL_OPAMP_STATE_RESET) { hopamp->State = HAL_OPAMP_STATE_READY; } } } return status; }