示例#1
0
void board_init_f(ulong dummy)
{
	switch_to_main_crystal_osc();

	/* disable watchdog */
	at91_disable_wdt();

	/* PMC configuration */
	at91_pmc_init();

	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);

	matrix_init();

	redirect_int_from_saic_to_aic();

	timer_init();

	board_early_init_f();

	preloader_console_init();

	mem_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	board_init_r(NULL, 0);
}
示例#2
0
static int at91_detect(void)
{
	at91_soc_initdata.type = AT91_SOC_NONE;
	at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;

	soc_detect(AT91_BASE_DBGU0);
	if (!at91_soc_is_detected())
		soc_detect(AT91_BASE_DBGU1);

	if (!at91_soc_is_detected())
		panic("AT91: Impossible to detect the SOC type");

	pr_info("AT91: Detected soc type: %s\n",
		at91_get_soc_type(&at91_soc_initdata));
	pr_info("AT91: Detected soc subtype: %s\n",
		at91_get_soc_subtype(&at91_soc_initdata));

	if (!at91_soc_is_enabled())
		panic("AT91: Soc not enabled");

	/* Init clock subsystem */
	at91_clock_init();

	if (at91_boot_soc.init)
		at91_boot_soc.init();

	return 0;
}
void __init at91sam9261_initialize(unsigned long main_clock)
{
	/* Map peripherals */
	iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));

	if (cpu_is_at91sam9g10())
		iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
	else
		iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));


	at91_arch_reset = at91sam9261_reset;
	pm_power_off = at91sam9261_poweroff;
	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
			| (1 << AT91SAM9261_ID_IRQ2);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91sam9261_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9261_gpio, 3);
}
示例#4
0
static void __init carmeva_map_io(void)
{
	at91rm9200_map_io();

	/* Initialize clocks: 20.000 MHz crystal */
	at91_clock_init(20000000);

	/* Setup the serial ports and console */
	at91_init_serial(&carmeva_uart_config);
}
示例#5
0
static void __init eb9200_map_io(void)
{
	at91rm9200_map_io();

	/* Initialize clocks: 18.432 MHz crystal */
	at91_clock_init(18432000);

	/* Setup the serial ports and console */
	at91_init_serial(&eb9200_uart_config);
}
示例#6
0
static void __init ek_map_io(void)
{
	at91rm9200_map_io();

	/* Initialize clocks: 18.432 MHz crystal */
	at91_clock_init(18432000);

	/* Setup the LEDs */
	at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);

	/* Setup the serial ports and console */
	at91_init_serial(&ek_uart_config);
}
示例#7
0
static void __init csb637_map_io(void)
{
	at91rm9200_map_io();

	/* Initialize clocks: 3.6864 MHz crystal */
	at91_clock_init(3686400);

	/* Setup the LEDs */
	at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);

	/* Setup the serial ports and console */
	at91_init_serial(&csb637_uart_config);
}
示例#8
0
/* --------------------------------------------------------------------
 *  AT91RM9200 processor initialization
 * -------------------------------------------------------------------- */
static void __init at91rm9200_initialize(void)
{
	/* Init clock subsystem */
	at91_clock_init(AT91_MAIN_CLOCK);

	/* Register the processor-specific clocks */
	at91rm9200_register_clocks();

	/* Register GPIO subsystem */
	at91_add_rm9200_gpio(0, AT91RM9200_BASE_PIOA);
	at91_add_rm9200_gpio(1, AT91RM9200_BASE_PIOB);
	at91_add_rm9200_gpio(2, AT91RM9200_BASE_PIOC);
	at91_add_rm9200_gpio(3, AT91RM9200_BASE_PIOD);
}
void __init at91sam9263_initialize(unsigned long main_clock)
{
	at91_arch_reset = at91sam9_alt_reset;
	pm_power_off = at91sam9263_poweroff;
	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91sam9263_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9263_gpio, 5);
}
示例#10
0
static void at91sam9261_initialize(void)
{
	/* Init clock subsystem */
	at91_clock_init(AT91_MAIN_CLOCK);

	/* Register the processor-specific clocks */
	at91sam9261_register_clocks();

	/* Register GPIO subsystem */
	at91_add_rm9200_gpio(0, AT91SAM9261_BASE_PIOA);
	at91_add_rm9200_gpio(1, AT91SAM9261_BASE_PIOB);
	at91_add_rm9200_gpio(2, AT91SAM9261_BASE_PIOC);

	at91_add_pit(AT91SAM9261_BASE_PIT);
	at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);
}
void __init at91sam9263_initialize(unsigned long main_clock)
{
	
	iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));

	at91_arch_reset = at91sam9263_reset;
	pm_power_off = at91sam9263_poweroff;
	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

	
	at91_clock_init(main_clock);

	
	at91sam9263_register_clocks();

	
	at91_gpio_init(at91sam9263_gpio, 5);
}
示例#12
0
void __init at572d940hf_initialize(unsigned long main_clock)
{
	/* Map peripherals */
	iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));

	at91_arch_reset = at572d940hf_reset;
	at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
			| (1 << AT572D940HF_ID_IRQ2);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at572d940hf_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at572d940hf_gpio, 3);
}
示例#13
0
void __init at91rm9200_initialize(unsigned long main_clock)
{
	at91_arch_reset = at91rm9200_reset;
	at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
			| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
			| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
			| (1 << AT91RM9200_ID_IRQ6);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91rm9200_register_clocks();

	/* Initialize GPIO subsystem */
	at91_gpio_init(at91rm9200_gpio,
		cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
}
示例#14
0
void s_init(void)
{
	switch_to_main_crystal_osc();

	/* disable watchdog */
	at91_disable_wdt();

	/* PMC configuration */
	at91_pmc_init();

	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);

	timer_init();

	board_early_init_f();

	preloader_console_init();

	mem_init();
}
示例#15
0
文件: at91rm9200.c 项目: 274914765/C
/* --------------------------------------------------------------------
 *  AT91RM9200 processor initialization
 * -------------------------------------------------------------------- */
void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks)
{
    /* Map peripherals */
    iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));

    at91_arch_reset = at91rm9200_reset;
    at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
            | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
            | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
            | (1 << AT91RM9200_ID_IRQ6);

    /* Init clock subsystem */
    at91_clock_init(main_clock);

    /* Register the processor-specific clocks */
    at91rm9200_register_clocks();

    /* Initialize GPIO subsystem */
    at91_gpio_init(at91rm9200_gpio, banks);
}
示例#16
0
static void __init csb337_map_io(void)
{
	int serial[AT91C_NR_UART] = CSB337_UART_MAP;
	int i;

	at91rm9200_map_io();
	
	/* Initialize clocks; 3.6864 MHz crystal */
	at91_clock_init(3686400);

#ifdef CONFIG_SERIAL_AT91
	at91_console_port = CSB337_SERIAL_CONSOLE;
	memcpy(at91_serial_map, serial, sizeof(serial));

	/* Register UARTs */
	for (i = 0; i < AT91C_NR_UART; i++) {
		if (serial[i] >= 0)
			at91_register_uart(i, serial[i]);
	}
#endif
}
void __init at91cap9_initialize(unsigned long main_clock)
{
    at91_arch_reset = at91cap9_reset;
    pm_power_off = at91cap9_poweroff;
    at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);

    /* Init clock subsystem */
    at91_clock_init(main_clock);

    /* Register the processor-specific clocks */
    at91cap9_register_clocks();

    /* Register GPIO subsystem */
    at91_gpio_init(at91cap9_gpio, 4);

    /* Remember the silicon revision */
    if (cpu_is_at91cap9_revB())
        system_rev = 0xB;
    else if (cpu_is_at91cap9_revC())
        system_rev = 0xC;
}
示例#18
0
int misc_init_r(void)
{
	char		*str;
	char		buf[32];
	at91_pmc_t	*pmc = (at91_pmc_t *) ATMEL_BASE_PMC;

	/*
	 * Normally the processor clock has a divisor of 2.
	 * In some cases this this needs to be set to 4.
	 * Check the user has set environment mdiv to 4 to change the divisor.
	 */
	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
		writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
			AT91SAM9_PMC_MDIV_4, &pmc->mckr);
		at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
		serial_setbrg();
		/* Notify the user that the clock is not default */
		printf("Setting master clock to %s MHz\n",
			strmhz(buf, get_mck_clk_rate()));
	}

	return 0;
}
示例#19
0
int misc_init_r(void)
{
	char *str;
	char buf[32];

	/*
	 * Normally the processor clock has a divisor of 2.
	 * In some cases this this needs to be set to 4.
	 * Check the user has set environment mdiv to 4 to change the divisor.
	 */
	if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
		at91_sys_write(AT91_PMC_MCKR,
			(at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) |
			AT91SAM9_PMC_MDIV_4);
		at91_clock_init(0);
		serial_setbrg();
		/* Notify the user that the clock is not default */
		printf("Setting master clock to %s MHz\n",
			strmhz(buf, get_mck_clk_rate()));
	}

	return 0;
}
示例#20
0
void board_init_f(ulong dummy)
{
	int ret;

	switch_to_main_crystal_osc();

#ifdef CONFIG_SAMA5D2
	configure_2nd_sram_as_l2_cache();
#endif

	/* disable watchdog */
	at91_disable_wdt();

	/* PMC configuration */
	at91_pmc_init();

	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);

	matrix_init();

	redirect_int_from_saic_to_aic();

	timer_init();

	board_early_init_f();

	mem_init();

	ret = spl_init();
	if (ret) {
		debug("spl_init() failed: %d\n", ret);
		hang();
	}

	preloader_console_init();

}
示例#21
0
int arch_cpu_init(void)
{
	return at91_clock_init(AT91_MAIN_CLOCK);
}
示例#22
0
int arch_cpu_init(void)
{
    return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
}