void athn_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self; struct athn_softc *sc = &csc->sc_sc; struct cardbus_attach_args *ca = aux; cardbus_devfunc_t ct = ca->ca_ct; bus_addr_t base; int error; sc->sc_dmat = ca->ca_dmat; csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_intrline = ca->ca_intrline; csc->sc_pc = ca->ca_pc; /* Power management hooks. */ sc->sc_enable = athn_cardbus_enable; sc->sc_disable = athn_cardbus_disable; sc->sc_power = athn_cardbus_power; sc->ops.read = athn_cardbus_read; sc->ops.write = athn_cardbus_write; sc->ops.write_barrier = athn_cardbus_write_barrier; /* Map control/status registers. */ error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG, PCI_MAPREG_TYPE_MEM, 0, &csc->sc_st, &csc->sc_sh, &base, &csc->sc_mapsize); if (error != 0) { printf(": can't map mem space\n"); return; } csc->sc_bar_val = base | PCI_MAPREG_TYPE_MEM; /* Set up the PCI configuration registers. */ athn_cardbus_setup(csc); printf(": irq %d\n", csc->sc_intrline); athn_attach(sc); Cardbus_function_disable(ct); }
void athn_pci_attach(struct device *parent, struct device *self, void *aux) { struct athn_pci_softc *psc = (struct athn_pci_softc *)self; struct athn_softc *sc = &psc->sc_sc; struct pci_attach_args *pa = aux; const char *intrstr; pci_intr_handle_t ih; pcireg_t memtype, reg; pci_product_id_t subsysid; int error; sc->sc_dmat = pa->pa_dmat; psc->sc_pc = pa->pa_pc; psc->sc_tag = pa->pa_tag; sc->ops.read = athn_pci_read; sc->ops.write = athn_pci_write; sc->ops.write_barrier = athn_pci_write_barrier; /* * Get the offset of the PCI Express Capability Structure in PCI * Configuration Space (Linux hardcodes it as 0x60.) */ error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, &psc->sc_cap_off, NULL); if (error != 0) { /* Found. */ sc->sc_disable_aspm = athn_pci_disable_aspm; sc->flags |= ATHN_FLAG_PCIE; } /* * Clear device-specific "PCI retry timeout" register (41h) to prevent * PCI Tx retries from interfering with C3 CPU state. */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); if (reg & 0xff00) pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); /* * Set the cache line size to a reasonable value if it is 0. * Change latency timer; default value yields poor results. */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); if (PCI_CACHELINE(reg) == 0) { reg &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); reg |= 8 << PCI_CACHELINE_SHIFT; } reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= 168 << PCI_LATTIMER_SHIFT; pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); /* Determine if bluetooth is also supported (combo chip.) */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); subsysid = PCI_PRODUCT(reg); if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) sc->flags |= ATHN_FLAG_BTCOEX3WIRE; else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) sc->flags |= ATHN_FLAG_BTCOEX2WIRE; /* Map control/status registers. */ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->sc_st, &psc->sc_sh, NULL, &psc->sc_mapsize, 0); if (error != 0) { printf(": can't map mem space\n"); return; } if (pci_intr_map(pa, &ih) != 0) { printf(": can't map interrupt\n"); return; } intrstr = pci_intr_string(psc->sc_pc, ih); psc->sc_ih = pci_intr_establish(psc->sc_pc, ih, IPL_NET, athn_intr, sc, sc->sc_dev.dv_xname); if (psc->sc_ih == NULL) { printf(": can't establish interrupt"); if (intrstr != NULL) printf(" at %s", intrstr); printf("\n"); return; } printf(": %s\n", intrstr); athn_attach(sc); }
Static void athn_pci_attach(device_t parent, device_t self, void *aux) { struct athn_pci_softc *psc = device_private(self); struct athn_softc *sc = &psc->psc_sc; struct ieee80211com *ic = &sc->sc_ic; struct pci_attach_args *pa = aux; const char *intrstr; pcireg_t memtype, reg; pci_product_id_t subsysid; int error; sc->sc_dev = self; sc->sc_dmat = pa->pa_dmat; psc->psc_pc = pa->pa_pc; psc->psc_tag = pa->pa_tag; sc->sc_ops.read = athn_pci_read; sc->sc_ops.write = athn_pci_write; sc->sc_ops.write_barrier = athn_pci_write_barrier; /* * Get the offset of the PCI Express Capability Structure in PCI * Configuration Space (Linux hardcodes it as 0x60.) */ error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, &psc->psc_cap_off, NULL); if (error != 0) { /* Found. */ sc->sc_disable_aspm = athn_pci_disable_aspm; sc->sc_flags |= ATHN_FLAG_PCIE; } /* * Noone knows why this shit is necessary but there are claims that * not doing this may cause very frequent PCI FATAL interrupts from * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483 */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); if (reg & 0xff00) pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); /* Change latency timer; default value yields poor results. */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= 168 << PCI_LATTIMER_SHIFT; pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); /* Determine if bluetooth is also supported (combo chip.) */ reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); subsysid = PCI_PRODUCT(reg); if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) sc->sc_flags |= ATHN_FLAG_BTCOEX3WIRE; else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) sc->sc_flags |= ATHN_FLAG_BTCOEX2WIRE; /* * Setup memory-mapping of PCI registers. */ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ATHN_PCI_MMBA); if (memtype != PCI_MAPREG_TYPE_MEM && memtype != PCI_MAPREG_MEM_TYPE_64BIT) { aprint_error_dev(self, "bad pci register type %d\n", (int)memtype); goto fail; } error = pci_mapreg_map(pa, ATHN_PCI_MMBA, memtype, 0, &psc->psc_iot, &psc->psc_ioh, NULL, &psc->psc_mapsz); if (error != 0) { aprint_error_dev(self, "cannot map register space\n"); goto fail; } /* * Arrange interrupt line. */ if (pci_intr_map(pa, &psc->psc_pih) != 0) { aprint_error_dev(self, "couldn't map interrupt\n"); goto fail1; } intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih); psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET, athn_intr, sc); if (psc->psc_ih == NULL) { aprint_error_dev(self, "couldn't map interrupt\n"); goto fail1; } ic->ic_ifp = &sc->sc_if; if (athn_attach(sc) != 0) goto fail2; aprint_verbose_dev(self, "interrupting at %s\n", intrstr); if (pmf_device_register(self, athn_pci_suspend, athn_pci_resume)) { pmf_class_network_register(self, &sc->sc_if); pmf_device_suspend(self, &sc->sc_qual); } else aprint_error_dev(self, "couldn't establish power handler\n"); ieee80211_announce(ic); return; fail2: pci_intr_disestablish(psc->psc_pc, psc->psc_ih); psc->psc_ih = NULL; fail1: bus_space_unmap(psc->psc_iot, psc->psc_ioh, psc->psc_mapsz); psc->psc_mapsz = 0; fail: return; }