void __init arch_init_irq(void)
{
unsigned int i;
set_irq_priority();
/* clear interrupt counter for VPE0 and VPE1 */
if (isRT6855A)
tc_outl(CR_INTC_ITR, (1 << 18) | (1 << 10));
/* Disable all hardware interrupts */
clear_c0_status(ST0_IM);
clear_c0_cause(CAUSEF_IP);
/* Initialize IRQ action handlers */
for (i = 0; i < NR_IRQS; i++) {
#ifdef CONFIG_MIPS_TC3262
/*
* Only MT is using the software interrupts currently, so we just
* leave them uninitialized for other processors.
*/
if (cpu_has_mipsmt) {
if ((i == SI_SWINT1_INT0) || (i == SI_SWINT1_INT1) ||
(i == SI_SWINT_INT0) || (i == SI_SWINT_INT1)) {
set_irq_chip(i, &mips_mt_cpu_irq_controller);
continue;
}
}
if ((i == SI_TIMER_INT) || (i == SI_TIMER1_INT))
set_irq_chip_and_handler(i, &tc3162_irq_chip,
handle_percpu_irq);
else
set_irq_chip_and_handler(i, &tc3162_irq_chip,
handle_level_irq);
#else
set_irq_chip_and_handler(i, &tc3162_irq_chip,
handle_level_irq);
#endif
}
#ifdef CONFIG_MIPS_TC3262
if (cpu_has_veic || cpu_has_vint) {
write_c0_status((read_c0_status() & ~ST0_IM ) |
(STATUSF_IP0 | STATUSF_IP1));
/* register irq dispatch functions */
for (i = 0; i < NR_IRQS; i++)
set_vi_handler(i, irq_dispatch_tab[i]);
} else {
change_c0_status(ST0_IM, ALLINTS);
}
#else
/* Enable all interrupts */
change_c0_status(ST0_IM, ALLINTS);
#endif
#ifdef CONFIG_MIPS_MT_SMP
vsmp_int_init();
#endif
}
void play_dead(void)
{
idle_task_exit();
cpu_play_dead = 1;
/*
* Wakeup is on SW0 or SW1; disable everything else
* Use BEV !IV (BRCM_WARM_RESTART_VEC) to avoid the regular Linux
* IRQ handlers; this clears ST0_IE and returns immediately.
*/
clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
irq_disable_hazard();
/*
* wait for SW interrupt from brcmstb_boot_secondary(), then jump
* back to start_secondary()
*/
do {
__asm__ __volatile__(
" wait\n"
" nop\n"
: : : "memory");
} while (cpu_play_dead);
__asm__ __volatile__(
" j brcmstb_tp1_reentry\n"
: : : "memory");
}
void __init ip32_timer_setup (struct irqaction *irq)
{
u64 crime_time;
u32 cc_tick;
write_c0_count(0);
irq->handler = cc_timer_interrupt;
printk("Calibrating system timer... ");
crime_time = crime_read_64(CRIME_TIME) & CRIME_TIME_MASK;
cc_tick = read_c0_count();
while ((crime_read_64 (CRIME_TIME) & CRIME_TIME_MASK) - crime_time
< WAIT_MS * 1000000 / CRIME_NS_PER_TICK)
;
cc_tick = read_c0_count() - cc_tick;
cc_interval = cc_tick / HZ * (1000 / WAIT_MS);
/*
* The round-off seems unnecessary; in testing, the error of the
* above procedure is < 100 ticks, which means it gets filtered
* out by the HZ adjustment.
*/
cc_interval = (cc_interval / PER_MHZ) * PER_MHZ;
printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ));
setup_irq (CLOCK_IRQ, irq);
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
/* Set ourselves up for future interrupts */
write_c0_compare(read_c0_count() + cc_interval);
change_c0_status(ST0_IM, ALLINTS);
local_irq_enable();
}
void
brcm_irq_dispatch(struct pt_regs *regs)
{
u32 cause;
cause = read_c0_cause() &
read_c0_status() &
CAUSEF_IP;
#ifdef CONFIG_KERNPROF
change_c0_status(cause | 1, 1);
#else
clear_c0_status(cause);
#endif
if (cause & CAUSEF_IP7)
do_IRQ(7, regs);
if (cause & CAUSEF_IP2)
do_IRQ(2, regs);
if (cause & CAUSEF_IP3)
do_IRQ(3, regs);
if (cause & CAUSEF_IP4)
do_IRQ(4, regs);
if (cause & CAUSEF_IP5)
do_IRQ(5, regs);
if (cause & CAUSEF_IP6)
do_IRQ(6, regs);
}
void __init arch_init_irq(void)
{
unsigned int i = 0;
const int shift = 2;
/* Disable all hardware interrupts */
change_c0_status(ST0_IM, 0x00);
/*
* Hardware interrupt sources will get mapped to CPU interrupts
* 2 through 7. Below is the mapping:
*
* Timer 0 (15) -> IRQ Source 7 -> CPU IRQ 5
* Timer 1 (14) -> IRQ Source 6 -> CPU IRQ 4
* UART (9) -> IRQ Source 5 -> CPU IRQ 3
* Watchdog (8) -> IRQ Source 4 -> CPU IRQ 2
* Ethernet (13) -> IRQ Source 3 -> CPU IRQ 1
*
*/
writel(0, IRQ_MAP1);
i = (IRQ_SOURCE_TIMER0 << (IRQ_TIMER0 << shift));
i |= (IRQ_SOURCE_TIMER1 << (IRQ_TIMER1 << shift));
i |= (IRQ_SOURCE_UART << (IRQ_UART << shift));
i |= (IRQ_SOURCE_WATCHDOG << (IRQ_WATCHDOG << shift));
i |= (IRQ_SOURCE_ETHERNET << (IRQ_ETHERNET << shift));
writel(i, IRQ_MAP2);
/*
* Disable all interrupts
*
* 0xfffcfffc is the power-on default value
*/
writel(0xfffcfffc, IRQ_SET);
writel(0xfffcfffc, IRQ_MASK);
/* Initialize IRQ action handlers */
for (i = 0; i < 16; i++)
{
set_irq_chip_and_handler(i, &camelot_irq_controller, handle_level_irq);
}
/* Enable all interrupts */
change_c0_status(ST0_IM, CAMELOT_ALL_INTS);
}
/*
* SMP init and finish on secondary CPUs
*/
void __cpuinit sb1250_smp_init(void)
{
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Set interrupt mask, but don't enable */
change_c0_status(ST0_IM, imask);
}
/*
* Broadcom specific IRQ setup
*/
void __init arch_init_irq(void)
{
int irq;
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = ~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK);
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type;
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type;
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_PERFCOUNT_IRQ].chip = &brcm_mips_performance_type;
brcm_mips_performance_enable(0);
#endif
brcm_mips_int2_enable(0);
}
/*
* Post-config but pre-boot cleanup entry point
*/
static void __cpuinit msp_smtc_init_secondary(void)
{
int myvpe;
/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
myvpe = read_c0_tcbind() & TCBIND_CURVPE;
if (myvpe > 0)
change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
STATUSF_IP6 | STATUSF_IP7);
smtc_init_secondary();
}
static void __cpuinit msp_smtc_init_secondary(void)
{
int myvpe;
myvpe = read_c0_tcbind() & TCBIND_CURVPE;
if (myvpe > 0)
change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
STATUSF_IP6 | STATUSF_IP7);
smtc_init_secondary();
}
void __init arch_init_irq(void)
{
unsigned int i;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
}
init_sb1250_irqs();
/*
* Map the high 16 bits of the mailbox registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
/* Clear the mailboxes. The firmware may leave them dirty */
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
/*
* Note that the timer interrupts are also mapped, but this is
* done in sb1250_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
}
void __init sni_pcimt_irq_init(void)
{
int i;
*(volatile u8 *) PCIMT_IRQSEL = IT_ETH | IT_EISA;
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
set_irq_chip(i, &pcimt_irq_type);
sni_hwint = sni_pcimt_hwint;
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
}
/*
* On systems with i8259-style interrupt controllers we assume for
* driver compatibility reasons interrupts 0 - 15 to be the i8295
* interrupts even if the hardware uses a different interrupt numbering.
*/
void __init arch_init_irq(void)
{
int i;
init_i8259_irqs(); /* Integrated i8259 */
init_pciasic();
/* Actually we've got more interrupts to handle ... */
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
set_irq_chip(i, &pciasic_irq_type);
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
}
void __init init_IRQ(void)
{
set_except_vector(0, cobalt_handle_int);
init_i8259_irqs(); /* 0 ... 15 */
mips_cpu_irq_init(16); /* 16 ... 23 */
/*
* Mask all cpu interrupts
* (except IE4, we already masked those at VIA level)
*/
change_c0_status(ST0_IM, IE_IRQ4);
}
void __init arch_init_irq(void)
{
int i;
clear_c0_status(ST0_BEV);
change_c0_status(ST0_IM, (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4));
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].chip = &brcm_irq_type;
}
}
void __init sni_rm200_irq_init(void)
{
int i;
* (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f;
mips_cpu_irq_init();
/* Actually we've got more interrupts to handle ... */
for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
set_irq_chip(i, &rm200_irq_type);
sni_hwint = sni_rm200_hwint;
change_c0_status(ST0_IM, IE_IRQ0);
setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq);
}
static void __init ddb_timer_init(struct irqaction *irq)
{
/* set the clock to 1 Hz */
nile4_out32(NILE4_T2CTRL, 1000000);
/* enable the General-Purpose Timer */
nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
/* reset timer */
nile4_out32(NILE4_T2CNTR, 0);
/* enable interrupt */
setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
change_c0_status(ST0_IM,
IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
}
void __init arch_init_irq(void)
{
unsigned int irq;
/* Install our interrupt handler, then clear and disable all
* CRIME and MACE interrupts. */
crime->imask = 0;
crime->hard_int = 0;
crime->soft_int = 0;
mace->perif.ctrl.istat = 0;
mace->perif.ctrl.imask = 0;
mips_cpu_irq_init();
for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
switch (irq) {
case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
set_irq_chip(irq, &ip32_mace_interrupt);
break;
case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
set_irq_chip(irq, &ip32_macepci_interrupt);
break;
case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
set_irq_chip(irq, &crime_edge_interrupt);
break;
case CRIME_CPUERR_IRQ:
case CRIME_MEMERR_IRQ:
set_irq_chip(irq, &crime_level_interrupt);
break;
case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
set_irq_chip(irq, &crime_edge_interrupt);
break;
case CRIME_VICE_IRQ:
set_irq_chip(irq, &crime_edge_interrupt);
break;
default:
set_irq_chip(irq, &ip32_maceisa_interrupt);
break;
}
}
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
change_c0_status(ST0_IM, ALLINTS);
}
/*
* On systems with i8259-style interrupt controllers we assume for
* driver compatibility reasons interrupts 0 - 15 to be the i8295
* interrupts even if the hardware uses a different interrupt numbering.
*/
void __init arch_init_irq(void)
{
int i;
init_i8259_irqs(); /* Integrated i8259 */
init_pciasic();
/* Actually we've got more interrupts to handle ... */
for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &pciasic_irq_type;
}
change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
}
/*
* On systems with i8259-style interrupt controllers we assume for
* driver compatibility reasons interrupts 0 - 15 to be the i8259
* interrupts even if the hardware uses a different interrupt numbering.
*/
void __init arch_init_irq(void)
{
/*
* this is a hack to get back the still needed wired mapping
* killed by init_mm()
*/
/* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
/* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
/* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
init_i8259_irqs(); /* Integrated i8259 */
mips_cpu_irq_init();
init_r4030_ints();
change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
}
void __init
init_IRQ(void)
{
int i;
for (i = 0; i < NR_IRQS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &brcm_irq_type;
}
set_except_vector(0, brcmIRQ);
change_c0_status(ST0_IM, ALLINTS);
#ifdef CONFIG_REMOTE_DEBUG
printk("Breaking into debugger...\n");
set_debug_traps();
breakpoint();
#endif
}
void __init init_IRQ(void)
{
unsigned int irq;
init_generic_irq();
/* Install our interrupt handler, then clear and disable all
* CRIME and MACE interrupts. */
crime_write(0, CRIME_INT_MASK);
crime_write(0, CRIME_HARD_INT);
crime_write(0, CRIME_SOFT_INT);
mace_perif_ctrl_write(0, istat);
mace_perif_ctrl_write(0, imask);
set_except_vector(0, ip32_handle_int);
for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
hw_irq_controller *controller;
if (irq == IP32_R4K_TIMER_IRQ)
controller = &ip32_cpu_interrupt;
else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
controller = &ip32_mace_interrupt;
else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
controller = &ip32_macepci_interrupt;
else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
controller = &ip32_crime_interrupt;
else
controller = &ip32_maceisa_interrupt;
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 0;
irq_desc[irq].handler = controller;
}
setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
change_c0_status(ST0_IM, ALLINTS);
}
void __init arch_init_irq(void)
{
unsigned int i;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_IMR_REGISTER(1,
R_IMR_INTERRUPT_MAP_BASE) +
(i << 3)));
}
init_sb1250_irqs();
/*
* Map the high 16 bits of the mailbox registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
__raw_writeq(IMR_IP3_VAL,
IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
(K_INT_MBOX_0 << 3)));
/* Clear the mailboxes. The firmware may leave them dirty */
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
/* Mask everything except the mailbox registers for both cpus */
tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
sb1250_steal_irq(K_INT_MBOX_0);
/*
* Note that the timer interrupts are also mapped, but this is
* done in sb1250_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
#ifdef CONFIG_KGDB
imask |= STATUSF_IP6;
#endif
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
#ifdef CONFIG_KGDB
if (kgdb_flag) {
kgdb_irq = K_INT_UART_0 + kgdb_port;
#ifdef CONFIG_SIBYTE_SB1250_DUART
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
__raw_writeq(M_DUART_IMR_BRK,
IOADDR(A_DUART_IMRREG(kgdb_port)));
sb1250_steal_irq(kgdb_irq);
__raw_writeq(IMR_IP6_VAL,
IOADDR(A_IMR_REGISTER(0,
R_IMR_INTERRUPT_MAP_BASE) +
(kgdb_irq << 3)));
sb1250_unmask_irq(0, kgdb_irq);
}
#endif
}
void __init arch_init_irq(void)
{
unsigned int i, cpu;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
/* Start with _high registers which has no bit 0 interrupt source */
for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
}
}
/* Now do _low registers */
for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
}
}
init_bcm1480_irqs();
/*
* Map the high 16 bits of mailbox_0 registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(K_BCM1480_INT_MBOX_0_0 << 3)));
}
/* Clear the mailboxes. The firmware may leave them dirty */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
}
/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
}
tmp = ~((u64) 0);
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
}
bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
/*
* Note that the timer interrupts are also mapped, but this is
* done in bcm1480_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
#ifdef CONFIG_KGDB
imask |= STATUSF_IP6;
#endif
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
#ifdef CONFIG_KGDB
if (kgdb_flag) {
kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
#ifdef CONFIG_SIBYTE_SB1250_DUART
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
/* QQQ FIXME */
__raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
bcm1480_steal_irq(kgdb_irq);
__raw_writeq(IMR_IP6_VAL,
IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(kgdb_irq<<3));
bcm1480_unmask_irq(0, kgdb_irq);
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif
prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
set_debug_traps();
breakpoint();
}
#endif
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern asmlinkage void brcmIRQ(void);
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = ~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK);
set_except_vector(0, brcmIRQ);
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].handler = &brcm_mips_int7_type;
/* Install all the 7xxx IRQs */
#if 1
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
#endif
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].handler = &brcm_uart_type;
#ifdef CONFIG_KGDB
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].handler = &brcm_uart_type;
#endif
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_PERFCOUNT_IRQ].handler = &brcm_mips_performance_type;
brcm_mips_performance_enable(0);
#endif
brcm_mips_int2_enable(0);
//enable the UPG level UARTA int.
//*((volatile unsigned long*)BCHP_IRQ0_UARTA_IRQEN) |= BCHP_IRQ0_UARTA_IRQEN_uarta_MASK;
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern int noirqdebug;
printk("timer irq %d\n", BCM_LINUX_SYSTIMER_IRQ);
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff;
CPUINT1C->IntrW2MaskSet = 0xffffffff;
change_c0_status(ST0_IE, 0);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type;
DECLARE_SMTC_IRQ(BCM_LINUX_SYSTIMER_IRQ, 7);
PRINTK("setup timer int\n");
#if defined(CONFIG_SMP) && ! defined(CONFIG_MIPS_MT)
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].chip = &brcm_mips_int7_type;
/* S/W IPC interrupt */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].chip = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].chip = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 96; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
DECLARE_SMTC_IRQ(irq, 2);
g_brcm_intc_cnt[irq -1] = 0;
}
PRINTK("setup int 1 to 96\n");
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTA_IRQ, 2);
PRINTK("setup UARTA int\n");
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTB_IRQ, 2);
PRINTK("setup UARTB int\n");
noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also).
brcm_mips_int2_enable(0);
//enable the UPG level UARTA int.
*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) |= BCHP_IRQ0_IRQEN_uarta_irqen_MASK;
#ifdef CONFIG_MIPS_MT_SMTC
local_irq_disable(); /* set IXMT for this TC */
change_c0_status(ST0_IE, 1); /* global IE = 1 */
PRINTK("disable irq\n");
#endif
#ifdef CONFIG_MIPS_MT
/* NOTE: vectored interrupts are not properly supported yet */
set_vi_handler(2, plat_irq_dispatch);
set_vi_handler(7, plat_irq_dispatch);
PRINTK("set vi handler for int2 and 7\n");
#endif
}
void __init arch_init_irq(void)
{
unsigned int i, cpu;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
/* Start with _high registers which has no bit 0 interrupt source */
for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
}
}
/* Now do _low registers */
for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
}
}
init_bcm1480_irqs();
/*
* Map the high 16 bits of mailbox_0 registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(K_BCM1480_INT_MBOX_0_0 << 3)));
}
/* Clear the mailboxes. The firmware may leave them dirty */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
}
/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
}
tmp = ~((u64) 0);
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
}
/*
* Note that the timer interrupts are also mapped, but this is
* done in bcm1480_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
}
void __init arch_init_irq(void)
{
int irq;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C_TP1->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff;
CPUINT1C_TP1->IntrW1MaskSet = 0xffffffff;
#if L1_IRQS > 64
CPUINT1C_TP1->IntrW2MaskSet = 0xffffffff;
CPUINT1C->IntrW2MaskSet = 0xffffffff;
#endif
change_c0_status(ST0_IE, 0);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int7_type;
#ifdef CONFIG_SMP
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].chip = &brcm_mips_int7_type;
/* S/W IPC interrupts */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].chip = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].chip = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= L1_IRQS; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
#ifdef CONFIG_SMP
irq_desc[irq].affinity = cpumask_of_cpu(0);
#endif
}
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].chip = &brcm_mips_performance_type;
//brcm_mips_performance_enable(0);
#endif
/* enable IRQ2 (this runs on TP0). IRQ3 enabled during TP1 boot. */
set_c0_status(STATUSF_IP2);
/* enable L2 interrupts for UARTA, B, C */
#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
BDEV_SET(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
BCHP_IRQ0_UART_IRQEN_uartb_MASK |
BCHP_IRQ0_UART_IRQEN_uartc_MASK);
#else
BDEV_SET(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK |
BCHP_IRQ0_IRQEN_uartb_irqen_MASK |
BCHP_IRQ0_IRQEN_uartc_irqen_MASK);
#endif
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern asmlinkage void brcmIRQ(void);
extern int noirqdebug;
//printk("timer irq %d end %d\n",BCM_LINUX_SYSTIMER_IRQ, BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_reserved0_SHIFT+32);
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff; //~(BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK);
set_except_vector(0, brcmIRQ);
change_c0_status(ST0_IE, ST0_IE);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].handler = &brcm_mips_int7_type;
#ifdef CONFIG_SMP
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].handler = &brcm_mips_int7_type;
/* S/W IPC interrupt */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].handler = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].handler = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].handler = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].handler = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].handler = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTC_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTC_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTC_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTC_IRQ].handler = &brcm_uart_type;
irq_desc[BCM_LINUX_UARTD_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTD_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTD_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTD_IRQ].handler = &brcm_uart_type;
#if 0
/* Set up smartcard interrupts. */
irq_desc[BCM_LINUX_SCA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCA_IRQ].action = 0;
irq_desc[BCM_LINUX_SCA_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCA_IRQ].handler = &brcm_intc_type;
irq_desc[BCM_LINUX_SCB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCB_IRQ].action = 0;
irq_desc[BCM_LINUX_SCB_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCB_IRQ].handler = &brcm_intc_type;
#endif
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].handler = &brcm_mips_performance_type;
//brcm_mips_performance_enable(0);
#endif
irq_desc[BCM_LINUX_PATA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PATA_IRQ].action = 0;
irq_desc[BCM_LINUX_PATA_IRQ].depth = 1;
irq_desc[BCM_LINUX_PATA_IRQ].handler = &brcm_pata_type;
noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also).
brcm_mips_int2_enable(0);
#if 1 //#ifdef CONFIG_MIPS_BRCM_IKOS
//enable the UPG level UARTA int.
*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) |= BCHP_IRQ0_IRQEN_uarta_irqen_MASK;
//INTC->IrqMask |= 0x1UL << (BCM_LINUX_UPG_IRQ -1);
#endif
}
/*
* Broadcom specific IRQ setup
*/
void __init brcm_irq_setup(void)
{
int irq;
extern int noirqdebug;
//INTC->IrqMask = 0UL;
//INTC->IrqStatus = 0UL;
CPUINT1C->IntrW0MaskSet = 0xffffffff;
CPUINT1C->IntrW1MaskSet = 0xffffffff;
//CPUINT1C->IntrW2MaskSet = 0xffffffff;
change_c0_status(ST0_IE, 0);
/* Setup timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_IRQ].chip = &brcm_mips_int6_type;
#ifdef CONFIG_SMP
/* Setup 2nd timer interrupt */
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].action = 0;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_SYSTIMER_1_IRQ].chip = &brcm_mips_int6_type;
/* S/W IPC interrupt */
irq_desc[BCM_LINUX_IPC_0_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_0_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_0_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_0_IRQ].chip = &brcm_mips_int0_type;
irq_desc[BCM_LINUX_IPC_1_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_IPC_1_IRQ].action = 0;
irq_desc[BCM_LINUX_IPC_1_IRQ].depth = 1;
irq_desc[BCM_LINUX_IPC_1_IRQ].chip = &brcm_mips_int1_type;
#endif
/* Install all the 7xxx IRQs */
for (irq = 1; irq <= 32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
g_brcm_intc_cnt[irq -1] = 0;
}
for (irq = 32+1; irq <= 32+32; irq++)
{
irq_desc[irq].status = IRQ_DISABLED;
irq_desc[irq].action = 0;
irq_desc[irq].depth = 1;
irq_desc[irq].chip = &brcm_intc_type;
DECLARE_SMTC_IRQ(irq, 2);
g_brcm_intc_cnt[irq -1] = 0;
}
PRINTK("setup int 1 to 96\n");
/* Handle the Serial IRQs differently so they can have unique IRQs */
irq_desc[BCM_LINUX_UARTA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTA_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTA_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTA_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTA_IRQ, 2);
PRINTK("setup UARTA int\n");
irq_desc[BCM_LINUX_UARTB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTB_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTB_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTB_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTB_IRQ, 2);
PRINTK("setup UARTB int\n");
irq_desc[BCM_LINUX_UARTC_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTC_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTC_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTC_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTC_IRQ, 2);
PRINTK("setup UARTB int\n");
irq_desc[BCM_LINUX_UARTD_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_UARTD_IRQ].action = 0;
irq_desc[BCM_LINUX_UARTD_IRQ].depth = 1;
irq_desc[BCM_LINUX_UARTD_IRQ].chip = &brcm_uart_type;
DECLARE_SMTC_IRQ(BCM_LINUX_UARTD_IRQ, 2);
PRINTK("setup UARTB int\n");
#if 0
/* Set up smartcard interrupts. */
irq_desc[BCM_LINUX_SCA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCA_IRQ].action = 0;
irq_desc[BCM_LINUX_SCA_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCA_IRQ].chip = &brcm_intc_type;
irq_desc[BCM_LINUX_SCB_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_SCB_IRQ].action = 0;
irq_desc[BCM_LINUX_SCB_IRQ].depth = 1;
irq_desc[BCM_LINUX_SCB_IRQ].chip = &brcm_intc_type;
#endif
#ifdef CONFIG_OPROFILE
/* profile IRQ */
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].action = 0;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].depth = 1;
irq_desc[BCM_LINUX_PERFCOUNT_IRQ].chip = &brcm_mips_int7_type;
//brcm_mips_performance_enable(0);
#endif
#if 0
/* Not on 7443 */
irq_desc[BCM_LINUX_PATA_IRQ].status = IRQ_DISABLED;
irq_desc[BCM_LINUX_PATA_IRQ].action = 0;
irq_desc[BCM_LINUX_PATA_IRQ].depth = 1;
irq_desc[BCM_LINUX_PATA_IRQ].chip = &brcm_pata_type;
#endif
noirqdebug = 1; // THT Disable spurious interrupt checking, as UARTA would cause in BE, (USB also).
brcm_mips_int2_enable(0);
//enable the UPG level UARTA int.
*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) |= BCHP_IRQ0_IRQEN_uarta_irqen_MASK;
}
/* Special cp0 register init */
static void __cpuinit jzsoc_smp_init(void)
{
unsigned int imask = STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
change_c0_status(ST0_IM, imask);
}
