int s5p_g2d_probe(struct platform_device *pdev) { struct resource *res; int ret; #ifdef G2D_DEBUG printk("###########################s5p_g2d_probe called\n"); #endif /* find the IRQs */ s5p_g2d_irq_num = platform_get_irq(pdev, 0); if(s5p_g2d_irq_num <= 0) { printk(KERN_ERR "failed to get irq resouce\n"); return -ENOENT; } ret = request_irq(s5p_g2d_irq_num, s5p_g2d_irq, IRQF_DISABLED, pdev->name, NULL); if (ret) { printk("request_irq(g2d) failed.\n"); return ret; } /* get the memory region */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if(res == NULL) { printk(KERN_ERR "failed to get memory region resouce\n"); return -ENOENT; } s5p_g2d_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name); if(s5p_g2d_mem == NULL) { printk(KERN_ERR "failed to reserve memory region\n"); return -ENOENT; } s5p_g2d_base = ioremap(s5p_g2d_mem->start, s5p_g2d_mem->end - res->start + 1); if(s5p_g2d_base == NULL) { printk(KERN_ERR "failed ioremap\n"); return -ENOENT; } #if 1 s5p_g2d_clock = clk_get(&pdev->dev, "clk_g2d"); if (IS_ERR(s5p_g2d_clock)) { printk(KERN_ERR "failed to find g2d clock source\n"); return -ENOENT; } clk_enable(s5p_g2d_clock); #endif init_waitqueue_head(&waitq_g2d); ret = misc_register(&s5p_g2d_dev); if (ret) { printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", G2D_MINOR, ret); return ret; } h_rot_mutex = (struct mutex *)kmalloc(sizeof(struct mutex), GFP_KERNEL); if (h_rot_mutex == NULL) return -1; mutex_init(h_rot_mutex); clk_disable(s5p_g2d_clock); //#ifdef G2D_DEBUG printk(KERN_ALERT"##################### s5p_g2d_probe Success\n"); //#endif return 0; }
static int hawaii_camera_power_front(struct device *dev, int on) { unsigned int value; int ret = -1; struct clk *clock; struct clk *axi_clk; struct clk *axi_clk_0; struct clk *lp_clock_0; struct clk *lp_clock_1; static struct pi_mgr_dfs_node unicam_dfs_node; struct soc_camera_device *icd = to_soc_camera_dev(dev); struct soc_camera_link *icl = to_soc_camera_link(icd); printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off")); if (!unicam_dfs_node.valid) { ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam", PI_MGR_PI_ID_MM, PI_MGR_DFS_MIN_VALUE); if (ret) { return -1; } if (gpio_request_one(SENSOR_1_GPIO_PWRDN, GPIOF_DIR_OUT | GPIOF_INIT_LOW, "Cam1PWDN")) { printk(KERN_ERR "Unable to get CAM1PWDN\n"); return -1; } d_lvldo2_cam1_1v8 = regulator_get(NULL, icl->regulators[0].supply); if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8)) printk(KERN_ERR "Failed to get d_lvldo2_cam1_1v8\n"); if (d_1v8_mmc1_vcc == NULL) { d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply); if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc)) printk(KERN_ERR "Err d_1v8_mmc1_vcc\n"); } if (d_3v0_mmc1_vcc == NULL) { d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply); if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc)) printk(KERN_ERR "d_3v0_mmc1_vcc"); } if (d_gpsr_cam0_1v8 == NULL) { d_gpsr_cam0_1v8 = regulator_get(NULL, icl->regulators[3].supply); if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8)) printk(KERN_ERR "Fl d_gpsr_cam0_1v8 get fail"); } } ret = -1; lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR); if (IS_ERR_OR_NULL(lp_clock_0)) { printk(KERN_ERR "Unable to get %s clock\n", CSI0_LP_PERI_CLK_NAME_STR); goto e_clk_get; } lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR); if (IS_ERR_OR_NULL(lp_clock_1)) { printk(KERN_ERR "Unable to get %s clock\n", CSI1_LP_PERI_CLK_NAME_STR); goto e_clk_get; } clock = clk_get(NULL, SENSOR_1_CLK); if (IS_ERR_OR_NULL(clock)) { printk(KERN_ERR "Unable to get SENSOR_1 clock\n"); goto e_clk_get; } axi_clk_0 = clk_get(NULL, "csi0_axi_clk"); if (IS_ERR_OR_NULL(axi_clk_0)) { printk(KERN_ERR "Unable to get AXI clock 0\n"); goto e_clk_get; } axi_clk = clk_get(NULL, "csi1_axi_clk"); if (IS_ERR_OR_NULL(axi_clk)) { printk(KERN_ERR "Unable to get AXI clock 1\n"); goto e_clk_get; } if (on) { if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO)) printk("DVFS for UNICAM failed\n"); gpio_set_value(SENSOR_1_GPIO_PWRDN, 1); usleep_range(5000, 5010); regulator_enable(d_lvldo2_cam1_1v8); usleep_range(1000, 1010); regulator_enable(d_1v8_mmc1_vcc); usleep_range(1000, 1010); /* Secondary cam addition */ regulator_enable(d_gpsr_cam0_1v8); usleep_range(1000, 1010); regulator_enable(d_3v0_mmc1_vcc); usleep_range(1000, 1010); if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) { pr_err("failed to set BYTE1\n"); goto e_clk_pll; } if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) { pr_err("failed to set BYTE0\n"); goto e_clk_pll; } if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) { pr_err("failed to set PIXPLL\n"); goto e_clk_pll; } value = clk_enable(lp_clock_0); if (value) { printk(KERN_ERR "Failed to enable lp clock 0\n"); goto e_clk_lp0; } value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ); if (value) { pr_err("Failed to set lp clock 0\n"); goto e_clk_set_lp0; } value = clk_enable(lp_clock_1); if (value) { pr_err(KERN_ERR "Failed to enable lp clock 1\n"); goto e_clk_lp1; } value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ); if (value) { pr_err("Failed to set lp clock 1\n"); goto e_clk_set_lp1; } value = clk_enable(axi_clk_0); if (value) { printk(KERN_ERR "Failed to enable axi clock 0\n"); goto e_clk_axi_clk_0; } value = clk_enable(axi_clk); if (value) { printk(KERN_ERR "Failed to enable axi clock 1\n"); goto e_clk_axi; } value = clk_enable(clock); if (value) { printk("Failed to enable sensor 1 clock\n"); goto e_clk_clock; } value = clk_set_rate(clock, SENSOR_1_CLK_FREQ); if (value) { printk("Failed to set sensor 1 clock\n"); goto e_clk_set_clock; } usleep_range(10000, 10100); gpio_set_value(SENSOR_1_GPIO_PWRDN, 0); msleep(30); } else { gpio_set_value(SENSOR_1_GPIO_PWRDN, 1); clk_disable(lp_clock_0); clk_disable(lp_clock_1); clk_disable(clock); clk_disable(axi_clk); clk_disable(axi_clk_0); regulator_disable(d_lvldo2_cam1_1v8); regulator_disable(d_1v8_mmc1_vcc); regulator_disable(d_gpsr_cam0_1v8); regulator_disable(d_3v0_mmc1_vcc); if (pi_mgr_dfs_request_update (&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) { printk("Failed to set DVFS for unicam\n"); } } return 0; e_clk_set_clock: clk_disable(clock); e_clk_clock: clk_disable(axi_clk); e_clk_axi: clk_disable(axi_clk_0); e_clk_axi_clk_0: e_clk_set_lp1: clk_disable(lp_clock_1); e_clk_lp1: e_clk_set_lp0: clk_disable(lp_clock_0); e_clk_lp0: e_clk_pll: e_clk_get: return ret; }
static int s3c_rtc_probe(struct platform_device *pdev) { struct rtc_device *rtc; struct rtc_time rtc_tm; struct resource *res; int ret; int tmp; dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev); /* find the IRQs */ s3c_rtc_tickno = platform_get_irq(pdev, 1); if (s3c_rtc_tickno < 0) { dev_err(&pdev->dev, "no irq for rtc tick\n"); return s3c_rtc_tickno; } s3c_rtc_alarmno = platform_get_irq(pdev, 0); if (s3c_rtc_alarmno < 0) { dev_err(&pdev->dev, "no irq for alarm\n"); return s3c_rtc_alarmno; } dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", s3c_rtc_tickno, s3c_rtc_alarmno); /* get the memory region */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(&pdev->dev, "failed to get memory region resource\n"); return -ENOENT; } s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(s3c_rtc_base)) return PTR_ERR(s3c_rtc_base); rtc_clk = devm_clk_get(&pdev->dev, "rtc"); if (IS_ERR(rtc_clk)) { dev_err(&pdev->dev, "failed to find rtc clock source\n"); ret = PTR_ERR(rtc_clk); rtc_clk = NULL; return ret; } clk_prepare_enable(rtc_clk); /* check to see if everything is setup correctly */ s3c_rtc_enable(pdev, 1); dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", readw(s3c_rtc_base + S3C2410_RTCCON)); device_init_wakeup(&pdev->dev, 1); /* register RTC and exit */ rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, THIS_MODULE); if (IS_ERR(rtc)) { dev_err(&pdev->dev, "cannot attach rtc\n"); ret = PTR_ERR(rtc); goto err_nortc; } s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev); /* Check RTC Time */ s3c_rtc_gettime(NULL, &rtc_tm); if (rtc_valid_tm(&rtc_tm)) { rtc_tm.tm_year = 100; rtc_tm.tm_mon = 0; rtc_tm.tm_mday = 1; rtc_tm.tm_hour = 0; rtc_tm.tm_min = 0; rtc_tm.tm_sec = 0; s3c_rtc_settime(NULL, &rtc_tm); dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); } if (s3c_rtc_cpu_type != TYPE_S3C2410) rtc->max_user_freq = 32768; else rtc->max_user_freq = 128; if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) { tmp = readw(s3c_rtc_base + S3C2410_RTCCON); tmp |= S3C2443_RTCCON_TICSEL; writew(tmp, s3c_rtc_base + S3C2410_RTCCON); } platform_set_drvdata(pdev, rtc); s3c_rtc_setfreq(&pdev->dev, 1); ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq, 0, "s3c2410-rtc alarm", rtc); if (ret) { dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret); goto err_alarm_irq; } ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq, 0, "s3c2410-rtc tick", rtc); if (ret) { dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret); goto err_alarm_irq; } clk_disable(rtc_clk); return 0; err_alarm_irq: platform_set_drvdata(pdev, NULL); err_nortc: s3c_rtc_enable(pdev, 0); clk_disable_unprepare(rtc_clk); return ret; }
static int __devinit dw_spi_mmio_probe(struct platform_device *pdev) { struct dw_spi_mmio *dwsmmio; struct dw_spi *dws; struct resource *mem, *ioarea; int ret; dwsmmio = kzalloc(sizeof(struct dw_spi_mmio), GFP_KERNEL); if (!dwsmmio) { ret = -ENOMEM; goto err_end; } dws = &dwsmmio->dws; /* Get basic io resource and map it */ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(&pdev->dev, "no mem resource?\n"); ret = -EINVAL; goto err_kfree; } ioarea = request_mem_region(mem->start, resource_size(mem), pdev->name); if (!ioarea) { dev_err(&pdev->dev, "SPI region already claimed\n"); ret = -EBUSY; goto err_kfree; } dws->regs = ioremap_nocache(mem->start, resource_size(mem)); if (!dws->regs) { dev_err(&pdev->dev, "SPI region already mapped\n"); ret = -ENOMEM; goto err_release_reg; } dws->irq = platform_get_irq(pdev, 0); if (dws->irq < 0) { dev_err(&pdev->dev, "no irq resource?\n"); ret = dws->irq; /* -ENXIO */ goto err_unmap; } dwsmmio->clk = clk_get(&pdev->dev, NULL); if (!dwsmmio->clk) { ret = -ENODEV; goto err_irq; } clk_enable(dwsmmio->clk); dws->parent_dev = &pdev->dev; dws->bus_num = 0; dws->num_cs = 4; dws->max_freq = clk_get_rate(dwsmmio->clk); ret = dw_spi_add_host(dws); if (ret) goto err_clk; platform_set_drvdata(pdev, dwsmmio); return 0; err_clk: clk_disable(dwsmmio->clk); clk_put(dwsmmio->clk); dwsmmio->clk = NULL; err_irq: free_irq(dws->irq, dws); err_unmap: iounmap(dws->regs); err_release_reg: release_mem_region(mem->start, resource_size(mem)); err_kfree: kfree(dwsmmio); err_end: return ret; }
static void ep93xx_stop_hc(struct device *dev) { clk_disable(usb_host_clock); }
void sysmmu_clk_disable(sysmmu_ips ips) { if (sysmmu_clk[ips]) clk_disable(sysmmu_clk[ips]); }
static int camdrv_ss_sr030pc50_sensor_power(int on) { unsigned int value; int ret = -1; struct clk *clock; struct clk *axi_clk; struct clk *axi_clk_0; struct clk *lp_clock_0; struct clk *lp_clock_1; CAM_INFO_PRINTK("%s:camera power %s\n", __func__, (on ? "on" : "off")); ret = -1; lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR); if (IS_ERR_OR_NULL(lp_clock_0)) { printk(KERN_ERR "Unable to get %s clock\n", CSI0_LP_PERI_CLK_NAME_STR); goto e_clk_get; } lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR); if (IS_ERR_OR_NULL(lp_clock_1)) { printk(KERN_ERR "Unable to get %s clock\n", CSI1_LP_PERI_CLK_NAME_STR); goto e_clk_get; } clock = clk_get(NULL, SENSOR_0_CLK); if (IS_ERR_OR_NULL(clock)) { printk(KERN_ERR "Unable to get SENSOR_1 clock\n"); goto e_clk_get; } axi_clk_0 = clk_get(NULL, "csi0_axi_clk"); if (IS_ERR_OR_NULL(axi_clk_0)) { printk(KERN_ERR "Unable to get AXI clock 0\n"); goto e_clk_get; } axi_clk = clk_get(NULL, "csi1_axi_clk"); if (IS_ERR_OR_NULL(axi_clk)) { CAM_ERROR_PRINTK("%s: Unable to get AXI clock 1\n", __func__); goto e_clk_get; } VCAM_A_2_8_V = regulator_get(NULL, VCAM_A_2_8V_REGULATOR); if(IS_ERR(VCAM_A_2_8_V)) { CAM_ERROR_PRINTK("can not get VCAM_A_2_8_V.8V\n"); return -1; } VCAM_IO_1_8_V = regulator_get(NULL, VCAM_IO_1_8V_REGULATOR); if(IS_ERR(VCAM_IO_1_8_V)) { CAM_ERROR_PRINTK("can not get VCAM_IO_1.8V\n"); return -1; } #if 1// defined(CONFIG_MACH_HAWAII_SS_GOLDENVEN)\ // || defined(CONFIG_MACH_HAWAII_SS_CODINAN) VCAM0_IO_1_8_V = regulator_get(NULL, VCAM0_IO_1_8V_REGULATOR); if(IS_ERR(VCAM0_IO_1_8_V)) { CAM_ERROR_PRINTK("can not get VCAM0_IO_1.8V\n"); return -1; } #endif VCAM_CORE_1_2_V = regulator_get(NULL, VCAM_CORE_1_2V_REGULATOR); if(IS_ERR(VCAM_CORE_1_2_V)) { CAM_ERROR_PRINTK("can not get VCAM_CORE_1_2_V\n"); return -1; } CAM_INFO_PRINTK("set cam_rst cam_stnby to low\n"); gpio_request(CAM0_RESET, "cam0_rst"); gpio_direction_output(CAM0_RESET, 0); gpio_request(CAM0_STNBY, "cam0_stnby"); gpio_direction_output(CAM0_STNBY, 0); gpio_request(CAM1_RESET, "cam1_rst"); gpio_direction_output(CAM1_RESET, 0); gpio_request(CAM1_STNBY, "cam1_stnby"); gpio_direction_output(CAM1_STNBY, 0); if(on) { CAM_INFO_PRINTK("power on the sensor \n"); //@HW regulator_set_voltage(VCAM_A_2_8_V, VCAM_A_2_8V_REGULATOR_uV, VCAM_A_2_8V_REGULATOR_uV); regulator_set_voltage(VCAM_IO_1_8_V, VCAM_IO_1_8V_REGULATOR_uV, VCAM_IO_1_8V_REGULATOR_uV); #if 1//defined(CONFIG_MACH_HAWAII_SS_GOLDENVEN)\ // || defined(CONFIG_MACH_HAWAII_SS_CODINAN) regulator_set_voltage(VCAM0_IO_1_8_V,1800000,1800000); #endif value = regulator_set_voltage(VCAM_CORE_1_2_V, VCAM_CORE_1_2V_REGULATOR_uV, VCAM_CORE_1_2V_REGULATOR_uV); if (value) CAM_ERROR_PRINTK("%s:regulator_set_voltage VCAM_CORE_1_2_V failed \n", __func__); if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) { pr_err("failed to set BYTE1\n"); goto e_clk_pll; } if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) { pr_err("failed to set BYTE0\n"); goto e_clk_pll; } if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) { pr_err("failed to set PIXPLL\n"); goto e_clk_pll; } value = clk_enable(lp_clock_0); if (value) { printk(KERN_ERR "Failed to enable lp clock 0\n"); goto e_clk_lp0; } value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ); if (value) { pr_err("Failed to set lp clock 0\n"); goto e_clk_set_lp0; } value = clk_enable(lp_clock_1); if (value) { pr_err(KERN_ERR "Failed to enable lp clock 1\n"); goto e_clk_lp1; } value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ); if (value) { pr_err("Failed to set lp clock 1\n"); goto e_clk_set_lp1; } value = clk_enable(axi_clk_0); if (value) { printk(KERN_ERR "Failed to enable axi clock 0\n"); goto e_clk_axi_clk_0; } value = clk_enable(axi_clk); if (value) { CAM_ERROR_PRINTK("%s:Failed to enable axi clock 1\n", __func__); goto e_clk_axi; } msleep(100); CAM_INFO_PRINTK("power on the sensor's power supply\n"); //@HW regulator_enable(VCAM_A_2_8_V); regulator_enable(VCAM_IO_1_8_V); #if 1//defined(CONFIG_MACH_HAWAII_SS_GOLDENVEN)\ // || defined(CONFIG_MACH_HAWAII_SS_CODINAN) regulator_enable(VCAM0_IO_1_8_V); #endif //msleep(5); regulator_enable(VCAM_CORE_1_2_V); msleep(2); regulator_disable(VCAM_CORE_1_2_V); msleep(12); //changed by aska for delay MCLK on time value = clk_enable(clock); if (value) { CAM_ERROR_PRINTK("%s: failed to enable clock %s\n", __func__,SENSOR_0_CLK); goto e_clk_clock; } CAM_INFO_PRINTK("enable camera clock\n"); value = clk_set_rate(clock, SENSOR_0_CLK_FREQ); if (value) { CAM_ERROR_PRINTK("%s: failed to set the clock %s to freq %d\n",__func__, SENSOR_0_CLK, SENSOR_0_CLK_FREQ); goto e_clk_set_clock; } CAM_INFO_PRINTK("set rate\n"); msleep(5); gpio_set_value(CAM1_STNBY,1); msleep(5); gpio_set_value(CAM1_RESET,1); msleep(50); if (ANTI_BANDING_60HZ == camera_antibanding_get()) { ret = camdrv_ss_sr030pc50_check_table_size_for_60hz(); if(ret != 0) { CAM_ERROR_PRINTK("%s: Fail - the table num is %d \n", __func__, ret); return -1; } camdrv_ss_sr030pc50_copy_files_for_60hz(); } } else { printk("power off the sensor \n"); //@HW /* enable reset gpio */ gpio_set_value(CAM1_RESET,0); msleep(1); gpio_set_value(CAM1_STNBY,0); msleep(1); clk_disable(lp_clock_0); clk_disable(lp_clock_1); clk_disable(clock); clk_disable(axi_clk); clk_disable(axi_clk_0); msleep(1); /* enable power down gpio */ regulator_disable(VCAM_IO_1_8_V); regulator_disable(VCAM_A_2_8_V); #if 1//defined(CONFIG_MACH_HAWAII_SS_GOLDENVEN)\ //|| defined(CONFIG_MACH_HAWAII_SS_CODINAN) regulator_disable(VCAM0_IO_1_8_V); #endif } return 0; e_clk_set_clock: clk_disable(clock); e_clk_clock: clk_disable(axi_clk); e_clk_axi: clk_disable(axi_clk_0); e_clk_axi_clk_0: e_clk_set_lp1: clk_disable(lp_clock_1); e_clk_lp1: e_clk_set_lp0: clk_disable(lp_clock_0); e_clk_lp0: e_clk_pll: e_clk_get: return ret; }
static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev) { struct usb_hcd *hcd = 0; struct ohci_hcd *ohci; const struct hc_driver *driver = &ohci_nxp_hc_driver; struct i2c_adapter *i2c_adap; struct i2c_board_info i2c_info; int ret = 0, irq; dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name); if (usb_disabled()) { err("USB is disabled"); ret = -ENODEV; goto out; } if (pdev->num_resources != 2 || pdev->resource[0].flags != IORESOURCE_MEM || pdev->resource[1].flags != IORESOURCE_IRQ) { err("Invalid resource configuration"); ret = -ENODEV; goto out; } /* Enable AHB slave USB clock, needed for further USB clock control */ __raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL); ret = i2c_add_driver(&isp1301_driver); if (ret < 0) { err("failed to add ISP1301 driver"); goto out; } i2c_adap = i2c_get_adapter(2); memset(&i2c_info, 0, sizeof(struct i2c_board_info)); strlcpy(i2c_info.type, "isp1301_nxp", I2C_NAME_SIZE); isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info, normal_i2c, NULL); i2c_put_adapter(i2c_adap); if (!isp1301_i2c_client) { err("failed to connect I2C to ISP1301 USB Transceiver"); ret = -ENODEV; goto out_i2c_driver; } isp1301_configure(); /* Enable USB PLL */ usb_clk = clk_get(&pdev->dev, "ck_pll5"); if (IS_ERR(usb_clk)) { err("failed to acquire USB PLL"); ret = PTR_ERR(usb_clk); goto out1; } ret = clk_enable(usb_clk); if (ret < 0) { err("failed to start USB PLL"); goto out2; } ret = clk_set_rate(usb_clk, 48000); if (ret < 0) { err("failed to set USB clock rate"); goto out3; } __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); /* Set to enable all needed USB clocks */ __raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL); while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) != USB_CLOCK_MASK) ; hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { err("Failed to allocate HC buffer"); ret = -ENOMEM; goto out3; } /* Set all USB bits in the Start Enable register */ nxp_set_usb_bits(); hcd->rsrc_start = pdev->resource[0].start; hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { dev_dbg(&pdev->dev, "request_mem_region failed\n"); ret = -ENOMEM; goto out4; } hcd->regs = (void __iomem *)pdev->resource[0].start; irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = -ENXIO; goto out4; } nxp_start_hc(); platform_set_drvdata(pdev, hcd); ohci = hcd_to_ohci(hcd); ohci_hcd_init(ohci); dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq); ret = usb_add_hcd(hcd, irq, 0); if (ret == 0) return ret; nxp_stop_hc(); out4: nxp_unset_usb_bits(); usb_put_hcd(hcd); out3: clk_disable(usb_clk); out2: clk_put(usb_clk); out1: i2c_unregister_device(isp1301_i2c_client); isp1301_i2c_client = NULL; out_i2c_driver: i2c_del_driver(&isp1301_driver); out: return ret; }
/* Initiliaze WKUP_M3, load the binary blob and let it run */ static int wkup_m3_init(void) { struct clk *m3_clk; struct omap_hwmod *wkup_m3_oh; const struct firmware *firmware; int ret = 0; int ipc_reg_r = 0; wkup_m3_oh = omap_hwmod_lookup("wkup_m3"); if (!wkup_m3_oh) { pr_err("%s: could not find omap_hwmod\n", __func__); ret = -ENODEV; goto exit; } ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8); if (!ipc_regs) { pr_err("Could not ioremap the IPC area\b"); ret = -ENOMEM; goto exit; } m3_eoi = ioremap(M3_TXEV_EOI, 0x4); if (!m3_eoi) { pr_err("Could not ioremap the EOI register\n"); ret = -ENOMEM; goto err1; } /* Reserve the MBOX for sending messages to M3 */ m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier); if (IS_ERR(m3_mbox)) { pr_err("Could not reserve mailbox for A8->M3 IPC\n"); ret = -ENODEV; goto err2; } /* Enable access to the M3 code and data area from A8 */ m3_clk = clk_get(NULL, "wkup_m3_fck"); if (IS_ERR(m3_clk)) { pr_err("%s failed to enable WKUP_M3 clock\n", __func__); goto err3; } if (clk_enable(m3_clk)) { pr_err("%s WKUP_M3: clock enable Failed\n", __func__); goto err4; } m3_code = ioremap(M3_UMEM, SZ_16K); if (!m3_code) { pr_err("%s Could not ioremap M3 code space\n", __func__); ret = -ENOMEM; goto err5; } pr_info("Trying to load am335x-pm-firmware.bin (60 secs timeout)\n"); ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev); if (ret < 0) { dev_err(mpu_dev, "request_firmware failed\n"); goto err6; } else { memcpy(m3_code, firmware->data, firmware->size); pr_info("Copied the M3 firmware to UMEM\n"); } ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler, IRQF_DISABLED, "wkup_m3_txev", NULL); if (ret) { pr_err("%s request_irq failed for 0x%x\n", __func__, AM33XX_IRQ_M3_M3SP_TXEV); goto err6; } m3_state = M3_STATE_RESET; /* * Invalidate M3 firmware version before hardreset. * Write invalid version in lower 4 nibbles of parameter * register (ipc_regs + 0x8). */ ipc_reg_r = readl(ipc_regs + 0x8); ipc_reg_r &= 0xffff0000; m3_version |= ipc_reg_r; writel(m3_version, ipc_regs + 0x8); ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3"); if (ret) { pr_err("Could not deassert the reset for WKUP_M3\n"); goto err6; } else { return 0; } err6: release_firmware(firmware); iounmap(m3_code); err5: clk_disable(m3_clk); err4: clk_put(m3_clk); err3: omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier); err2: iounmap(m3_eoi); err1: iounmap(ipc_regs); exit: return ret; }
static int __devinit sdhci_pxav3_probe(struct platform_device *pdev) { struct sdhci_pltfm_host *pltfm_host; struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; struct device *dev = &pdev->dev; struct sdhci_host *host = NULL; struct sdhci_pxa *pxa = NULL; int ret; struct clk *clk; pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); if (!pxa) return -ENOMEM; host = sdhci_pltfm_init(pdev, NULL); if (IS_ERR(host)) { kfree(pxa); return PTR_ERR(host); } pltfm_host = sdhci_priv(host); pltfm_host->priv = pxa; clk = clk_get(dev, "PXA-SDHCLK"); if (IS_ERR(clk)) { dev_err(dev, "failed to get io clock\n"); ret = PTR_ERR(clk); goto err_clk_get; } pltfm_host->clk = clk; clk_enable(clk); host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | SDHCI_QUIRK_32BIT_ADMA_SIZE; /* enable 1/8V DDR capable */ host->mmc->caps |= MMC_CAP_1_8V_DDR; if (pdata) { if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { /* on-chip device */ host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; host->mmc->caps |= MMC_CAP_NONREMOVABLE; } /* If slot design supports 8 bit data, indicate this to MMC. */ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; if (pdata->quirks) host->quirks |= pdata->quirks; if (pdata->host_caps) host->mmc->caps |= pdata->host_caps; if (pdata->pm_caps) host->mmc->pm_caps |= pdata->pm_caps; } host->ops = &pxav3_sdhci_ops; ret = sdhci_add_host(host); if (ret) { dev_err(&pdev->dev, "failed to add host\n"); goto err_add_host; } platform_set_drvdata(pdev, host); return 0; err_add_host: clk_disable(clk); clk_put(clk); err_clk_get: sdhci_pltfm_free(pdev); kfree(pxa); return ret; }
#include <linux/module.h>
static int tegra_camera_disable_csi(struct tegra_camera_dev *dev) { clk_disable(dev->csi_clk); return 0; }
static int tegra_camera_disable_isp(struct tegra_camera_dev *dev) { clk_disable(dev->isp_clk); return 0; }
static int __devinit sh_mobile_sdhi_probe(struct platform_device *pdev) { struct sh_mobile_sdhi *priv; struct tmio_mmc_data *mmc_data; struct sh_mobile_sdhi_info *p = pdev->dev.platform_data; struct tmio_mmc_host *host; char clk_name[8]; int irq, ret, i = 0; bool multiplexed_isr = true; priv = kzalloc(sizeof(struct sh_mobile_sdhi), GFP_KERNEL); if (priv == NULL) { dev_err(&pdev->dev, "kzalloc failed\n"); return -ENOMEM; } mmc_data = &priv->mmc_data; p->pdata = mmc_data; snprintf(clk_name, sizeof(clk_name), "sdhi%d", pdev->id); priv->clk = clk_get(&pdev->dev, clk_name); if (IS_ERR(priv->clk)) { dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); ret = PTR_ERR(priv->clk); goto eclkget; } clk_enable(priv->clk); mmc_data->hclk = clk_get_rate(priv->clk); mmc_data->set_pwr = sh_mobile_sdhi_set_pwr; mmc_data->get_cd = sh_mobile_sdhi_get_cd; mmc_data->capabilities = MMC_CAP_MMC_HIGHSPEED; if (p) { mmc_data->flags = p->tmio_flags; if (mmc_data->flags & TMIO_MMC_HAS_IDLE_WAIT) mmc_data->write16_hook = sh_mobile_sdhi_write16_hook; mmc_data->ocr_mask = p->tmio_ocr_mask; mmc_data->capabilities |= p->tmio_caps; if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) { priv->param_tx.slave_id = p->dma_slave_tx; priv->param_rx.slave_id = p->dma_slave_rx; priv->dma_priv.chan_priv_tx = &priv->param_tx; priv->dma_priv.chan_priv_rx = &priv->param_rx; priv->dma_priv.alignment_shift = 1; /* 2-byte alignment */ mmc_data->dma = &priv->dma_priv; } } /* * All SDHI blocks support 2-byte and larger block sizes in 4-bit * bus width mode. */ mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; /* * All SDHI blocks support SDIO IRQ signalling. */ mmc_data->flags |= TMIO_MMC_SDIO_IRQ; ret = tmio_mmc_host_probe(&host, pdev, mmc_data); if (ret < 0) goto eprobe; /* * Allow one or more specific (named) ISRs or * one or more multiplexed (un-named) ISRs. */ irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_CARD_DETECT); if (irq >= 0) { multiplexed_isr = false; ret = request_irq(irq, tmio_mmc_card_detect_irq, 0, dev_name(&pdev->dev), host); if (ret) goto eirq_card_detect; } irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_SDIO); if (irq >= 0) { multiplexed_isr = false; ret = request_irq(irq, tmio_mmc_sdio_irq, 0, dev_name(&pdev->dev), host); if (ret) goto eirq_sdio; } irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_SDCARD); if (irq >= 0) { multiplexed_isr = false; ret = request_irq(irq, tmio_mmc_sdcard_irq, 0, dev_name(&pdev->dev), host); if (ret) goto eirq_sdcard; } else if (!multiplexed_isr) { dev_err(&pdev->dev, "Principal SD-card IRQ is missing among named interrupts\n"); ret = irq; goto eirq_sdcard; } if (multiplexed_isr) { while (1) { irq = platform_get_irq(pdev, i); if (irq < 0) break; i++; ret = request_irq(irq, tmio_mmc_irq, 0, dev_name(&pdev->dev), host); if (ret) goto eirq_multiplexed; } /* There must be at least one IRQ source */ if (!i) goto eirq_multiplexed; } dev_info(&pdev->dev, "%s base at 0x%08lx clock rate %u MHz\n", mmc_hostname(host->mmc), (unsigned long) (platform_get_resource(pdev,IORESOURCE_MEM, 0)->start), mmc_data->hclk / 1000000); return ret; eirq_multiplexed: while (i--) { irq = platform_get_irq(pdev, i); free_irq(irq, host); } eirq_sdcard: irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_SDIO); if (irq >= 0) free_irq(irq, host); eirq_sdio: irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_CARD_DETECT); if (irq >= 0) free_irq(irq, host); eirq_card_detect: tmio_mmc_host_remove(host); eprobe: clk_disable(priv->clk); clk_put(priv->clk); eclkget: kfree(priv); return ret; }
static inline void __init apollon_init_smc91x(void) { unsigned long base; unsigned int rate; struct clk *gpmc_fck; int eth_cs; gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ if (IS_ERR(gpmc_fck)) { WARN_ON(1); return; } clk_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); eth_cs = APOLLON_ETH_CS; /* Make sure CS1 timings are correct */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); if (rate >= 160000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else if (rate >= 130000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else {/* rate = 100000000 */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); } if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); goto out; } apollon_smc91x_resources[0].start = base + 0x300; apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); omap_cfg_reg(W4__24XX_GPIO74); if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); gpmc_cs_free(APOLLON_ETH_CS); goto out; } gpio_direction_input(APOLLON_ETHR_GPIO_IRQ); out: clk_disable(gpmc_fck); clk_put(gpmc_fck); }
static int __init mmc_omap_probe(struct platform_device *pdev) { struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; struct mmc_omap_host *host = NULL; struct resource *res; int i, ret = 0; int irq; if (pdata == NULL) { dev_err(&pdev->dev, "platform data missing\n"); return -ENXIO; } if (pdata->nr_slots == 0) { dev_err(&pdev->dev, "no slots\n"); return -ENXIO; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); if (res == NULL || irq < 0) return -ENXIO; res = request_mem_region(res->start, resource_size(res), pdev->name); if (res == NULL) return -EBUSY; host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); if (host == NULL) { ret = -ENOMEM; goto err_free_mem_region; } INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, (unsigned long) host); spin_lock_init(&host->clk_lock); setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); spin_lock_init(&host->dma_lock); setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host); spin_lock_init(&host->slot_lock); init_waitqueue_head(&host->slot_wq); host->pdata = pdata; host->dev = &pdev->dev; platform_set_drvdata(pdev, host); host->id = pdev->id; host->mem_res = res; host->irq = irq; host->use_dma = 1; host->dev->dma_mask = &pdata->dma_mask; host->dma_ch = -1; host->irq = irq; host->phys_base = host->mem_res->start; host->virt_base = ioremap(res->start, resource_size(res)); if (!host->virt_base) goto err_ioremap; host->iclk = clk_get(&pdev->dev, "ick"); if (IS_ERR(host->iclk)) { ret = PTR_ERR(host->iclk); goto err_free_mmc_host; } clk_enable(host->iclk); host->fclk = clk_get(&pdev->dev, "fck"); if (IS_ERR(host->fclk)) { ret = PTR_ERR(host->fclk); goto err_free_iclk; } ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); if (ret) goto err_free_fclk; if (pdata->init != NULL) { ret = pdata->init(&pdev->dev); if (ret < 0) goto err_free_irq; } host->nr_slots = pdata->nr_slots; for (i = 0; i < pdata->nr_slots; i++) { ret = mmc_omap_new_slot(host, i); if (ret < 0) { while (--i >= 0) mmc_omap_remove_slot(host->slots[i]); goto err_plat_cleanup; } } host->reg_shift = (cpu_is_omap7xx() ? 1 : 2); return 0; err_plat_cleanup: if (pdata->cleanup) pdata->cleanup(&pdev->dev); err_free_irq: free_irq(host->irq, host); err_free_fclk: clk_put(host->fclk); err_free_iclk: clk_disable(host->iclk); clk_put(host->iclk); err_free_mmc_host: iounmap(host->virt_base); err_ioremap: kfree(host); err_free_mem_region: release_mem_region(res->start, resource_size(res)); return ret; }
static void mx6q_sabrelite_sata_exit(struct device *dev) { clk_disable(sata_clk); clk_put(sata_clk); }
static int __devinit hisik3_wdt_probe(struct platform_device *pdev) { int ret = 0; struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { ret = -ENOENT; dev_warn(&pdev->dev, "WDT memory resource not defined\n"); goto err; } if (!request_mem_region(res->start, resource_size(res), pdev->name)) { dev_warn(&pdev->dev, "WDT failed to get memory region resource\n"); ret = -ENOENT; goto err; } wdt = kzalloc(sizeof(*wdt), GFP_KERNEL); if (!wdt) { dev_warn(&pdev->dev, "WDT kzalloc failed\n"); ret = -ENOMEM; goto err_kzalloc; } wdt->clk = clk_get(NULL,"clk_wd"); if (IS_ERR(wdt->clk)) { dev_warn(&pdev->dev, "WDT clock not found\n"); ret = PTR_ERR(wdt->clk); goto err_clk_get; } wdt->base = ioremap(res->start, resource_size(res)); if (!wdt->base) { ret = -ENOMEM; dev_warn(&pdev->dev, "WDT ioremap fail\n"); goto err_ioremap; } spin_lock_init(&wdt->lock); /* This checks if system booted after watchdog reset or not */ ret = clk_enable(wdt->clk); if (ret) { dev_warn(&pdev->dev, "clock enable fail"); goto err_clk_enable; } wdt->pdev = pdev; wdt_default_init(DEFAULT_TIMEOUT); wdt_default_config(); INIT_DELAYED_WORK(&wdt->k3_wdt_delayed_work, wdt_mond); schedule_delayed_work(&wdt->k3_wdt_delayed_work, 0); ret = misc_register(&hisik3_wdt_miscdev); if (ret < 0) { dev_warn(&pdev->dev, "WDT cannot register misc device\n"); goto err_misc_register; } wdt_enable(); dev_warn(&pdev->dev,"WDT probing has been finished\n"); return 0; err_misc_register: clk_disable(wdt->clk); err_clk_enable: iounmap(wdt->base); err_ioremap: clk_put(wdt->clk); err_clk_get: kfree(wdt); wdt = NULL; err_kzalloc: release_mem_region(res->start, resource_size(res)); err: dev_warn(&pdev->dev, "WDT probe failed!!!\n"); return ret; }
static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) { clk_disable(mcspi->ick); clk_disable(mcspi->fck); }
/* * Configure the SSC. */ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); int id = dai->id; struct atmel_ssc_info *ssc_p = &ssc_info[id]; struct atmel_pcm_dma_params *dma_params; int dir, channels, bits; u32 tfmr, rfmr, tcmr, rcmr; int start_event; int ret; /* * Currently, there is only one set of dma params for * each direction. If more are added, this code will * have to be changed to select the proper set. */ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = 0; else dir = 1; dma_params = &ssc_dma_params[id][dir]; dma_params->ssc = ssc_p->ssc; dma_params->substream = substream; ssc_p->dma_params[dir] = dma_params; /* * The snd_soc_pcm_stream->dma_data field is only used to communicate * the appropriate DMA parameters to the pcm driver hw_params() * function. It should not be used for other purposes * as it is common to all substreams. */ snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_params); channels = params_channels(params); /* * Determine sample size in bits and the PDC increment. */ switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: bits = 8; dma_params->pdc_xfer_size = 1; break; case SNDRV_PCM_FORMAT_S16_LE: bits = 16; dma_params->pdc_xfer_size = 2; break; case SNDRV_PCM_FORMAT_S24_LE: bits = 24; dma_params->pdc_xfer_size = 4; break; case SNDRV_PCM_FORMAT_S32_LE: bits = 32; dma_params->pdc_xfer_size = 4; break; default: printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); return -EINVAL; } /* * Compute SSC register settings. */ switch (ssc_p->daifmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: /* * I2S format, SSC provides BCLK and LRC clocks. * * The SSC transmit and receive clocks are generated * from the MCK divider, and the BCLK signal * is output on the SSC TK line. */ rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | SSC_BF(RCMR_STTDLY, START_DELAY) | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, SSC_CKS_DIV); rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) | SSC_BF(RFMR_FSLEN, (bits - 1)) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | SSC_BF(TCMR_STTDLY, START_DELAY) | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) | SSC_BF(TCMR_CKS, SSC_CKS_DIV); tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | SSC_BF(TFMR_FSLEN, (bits - 1)) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: /* * I2S format, CODEC supplies BCLK and LRC clocks. * * The SSC transmit clock is obtained from the BCLK signal on * on the TK line, and the SSC receive clock is * generated from the transmit clock. * * For single channel data, one sample is transferred * on the falling edge of the LRC clock. * For two channel data, one sample is * transferred on both edges of the LRC clock. */ start_event = ((channels == 1) ? SSC_START_FALLING_RF : SSC_START_EDGE_RF); rcmr = SSC_BF(RCMR_PERIOD, 0) | SSC_BF(RCMR_STTDLY, START_DELAY) | SSC_BF(RCMR_START, start_event) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, SSC_CKS_PIN); rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | SSC_BF(RFMR_FSLEN, 0) | SSC_BF(RFMR_DATNB, 0) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, 0) | SSC_BF(TCMR_STTDLY, START_DELAY) | SSC_BF(TCMR_START, start_event) | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | SSC_BF(TCMR_CKS, SSC_CKS_CLOCK); tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | SSC_BF(TFMR_FSLEN, 0) | SSC_BF(TFMR_DATNB, 0) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: /* * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. * * The SSC transmit and receive clocks are generated from the * MCK divider, and the BCLK signal is output * on the SSC TK line. */ rcmr = SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period) | SSC_BF(RCMR_STTDLY, 1) | SSC_BF(RCMR_START, SSC_START_RISING_RF) | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | SSC_BF(RCMR_CKS, SSC_CKS_DIV); rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) | SSC_BF(RFMR_FSLEN, 0) | SSC_BF(RFMR_DATNB, (channels - 1)) | SSC_BIT(RFMR_MSBF) | SSC_BF(RFMR_LOOP, 0) | SSC_BF(RFMR_DATLEN, (bits - 1)); tcmr = SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period) | SSC_BF(TCMR_STTDLY, 1) | SSC_BF(TCMR_START, SSC_START_RISING_RF) | SSC_BF(TCMR_CKI, SSC_CKI_RISING) | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) | SSC_BF(TCMR_CKS, SSC_CKS_DIV); tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | SSC_BF(TFMR_FSDEN, 0) | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) | SSC_BF(TFMR_FSLEN, 0) | SSC_BF(TFMR_DATNB, (channels - 1)) | SSC_BIT(TFMR_MSBF) | SSC_BF(TFMR_DATDEF, 0) | SSC_BF(TFMR_DATLEN, (bits - 1)); break; case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: default: printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", ssc_p->daifmt); return -EINVAL; } pr_debug("atmel_ssc_hw_params: " "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr, rfmr, tcmr, tfmr); if (!ssc_p->initialized) { /* Enable PMC peripheral clock for this SSC */ pr_debug("atmel_ssc_dai: Starting clock\n"); clk_enable(ssc_p->ssc->clk); /* Reset the SSC and its PDC registers */ ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, ssc_p->name, ssc_p); if (ret < 0) { printk(KERN_WARNING "atmel_ssc_dai: request_irq failure\n"); pr_debug("Atmel_ssc_dai: Stoping clock\n"); clk_disable(ssc_p->ssc->clk); return ret; } ssc_p->initialized = 1; } /* set SSC clock mode register */ ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div); /* set receive clock mode and format */ ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); /* set transmit clock mode and format */ ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); return 0; }
static void dss_clks_disable(void) { clk_disable(dss_ick); clk_disable(dss_dss_fclk); clk_disable(dss_sys_fclk); }
static int ath79_wdt_remove(struct platform_device *pdev) { misc_deregister(&ath79_wdt_miscdev); clk_disable(wdt_clk); return 0; }
static inline void __init h4_init_debug(void) { int eth_cs; unsigned long cs_mem_base; unsigned int muxed, rate; struct clk *gpmc_fck; eth_cs = H4_SMC91X_CS; gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ if (IS_ERR(gpmc_fck)) { WARN_ON(1); return; } clk_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); clk_disable(gpmc_fck); clk_put(gpmc_fck); if (is_gpmc_muxed()) muxed = 0x200; else muxed = 0; /* Make sure CS1 timings are correct */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011000 | muxed); if (rate >= 160000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else if (rate >= 130000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else {/* rate = 100000000 */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); } if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); goto out; } udelay(100); omap_cfg_reg(M15_24XX_GPIO92); if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) gpmc_cs_free(eth_cs); out: clk_disable(gpmc_fck); clk_put(gpmc_fck); }
static int __devinit s5p_tv_probe(struct platform_device *pdev) { int irq_num; int ret; int i; s5ptv_status.dev_fb = &pdev->dev; suspend_resume_sync = 0; is_tv_clk_on = false; is_tv_phy_enable = false; //enable power /* Get csis power domain regulator */ s5ptv_status.tv_regulator = regulator_get(&pdev->dev, "pd"); if (IS_ERR(s5ptv_status.tv_regulator)) { printk(KERN_ERR "%s %d: failed to get resource %s\n", __func__, __LINE__, "s3c-tv20 pd"); return PTR_ERR(s5ptv_status.tv_regulator); } s5ptv_status.tv_tvout = regulator_get(NULL, "tvout"); if (IS_ERR(s5ptv_status.tv_tvout)) { printk(KERN_ERR "%s %d: failed to get resource %s\n", __func__, __LINE__, "s3c-tv20 tvout"); return PTR_ERR(s5ptv_status.tv_tvout); } s5ptv_status.tv_tv = regulator_get(NULL, "hdmi"); if (IS_ERR(s5ptv_status.tv_tv)) { printk(KERN_ERR "%s %d: failed to get resource %s\n", __func__, __LINE__, "s3c-tv20 tv"); return PTR_ERR(s5ptv_status.tv_tv); } regulator_enable(s5ptv_status.tv_tv); regulator_enable(s5ptv_status.tv_tvout); s5ptv_status.dev_fb = &pdev->dev; __s5p_sdout_probe(pdev, 0); __s5p_vp_probe(pdev, 1); __s5p_mixer_probe(pdev, 2); #ifdef CONFIG_CPU_S5PV210 tv_clk_get(pdev, &s5ptv_status); s5p_tv_clk_gate(true); #endif #ifdef CONFIG_CPU_S5PV210 __s5p_hdmi_probe(pdev, 3, 4); __s5p_hdcp_init(); #endif #ifdef FIX_27M_UNSTABLE_ISSUE /* for smdkc100 pop */ writel(0x1, S5PC1XX_GPA0_BASE + 0x56c); #endif #ifdef I2C_BASE /* for dev_dbg err. */ spin_lock_init(&slock_hpd); /* for bh */ INIT_WORK(&ws_hpd, (void *)set_ddc_port); #endif /* check EINT init state */ #ifdef CONFIG_MACH_STEALTHV gpio_set_value(GPIO_HDMI_EN1, 1); #endif s5ptv_status.hpd_status= 0; dev_info(&pdev->dev, "hpd status is cable %s\n", s5ptv_status.hpd_status ? "inserted":"removed"); /* interrupt */ TVOUT_IRQ_INIT(irq_num, ret, pdev, 0, out, __s5p_mixer_irq, "mixer"); TVOUT_IRQ_INIT(irq_num, ret, pdev, 1, out_hdmi_irq, __s5p_hdmi_irq , "hdmi"); TVOUT_IRQ_INIT(irq_num, ret, pdev, 2, out_tvenc_irq, s5p_tvenc_irq, "tvenc"); /* v4l2 video device registration */ for (i = 0; i < S5P_TVMAX_CTRLS; i++) { s5ptv_status.video_dev[i] = &s5p_tvout[i]; if (video_register_device(s5ptv_status.video_dev[i], VFL_TYPE_GRABBER, s5p_tvout[i].minor) != 0) { dev_err(&pdev->dev, "Couldn't register tvout driver.\n"); return 0; } } #ifdef CONFIG_TV_FB mutex_init(&s5ptv_status.fb_lock); /* for default start up */ _s5p_tv_if_init_param(); s5ptv_status.tvout_param.disp_mode = TVOUT_720P_60; s5ptv_status.tvout_param.out_mode = TVOUT_OUTPUT_HDMI; #ifndef CONFIG_USER_ALLOC_TVOUT s5p_tv_clk_gate(true); if(s5ptv_status.tvout_param.out_mode == TVOUT_OUTPUT_HDMI || s5ptv_status.tvout_param.out_mode == TVOUT_OUTPUT_HDMI_RGB || s5ptv_status.tvout_param.out_mode == TVOUT_OUTPUT_DVI) tv_phy_power(true); _s5p_tv_if_set_disp(); #endif s5ptvfb_set_lcd_info(&s5ptv_status); /* prepare memory */ if (s5ptvfb_alloc_framebuffer()) goto err_alloc; if (s5ptvfb_register_framebuffer()) goto err_alloc; #ifndef CONFIG_USER_ALLOC_TVOUT s5ptvfb_display_on(&s5ptv_status); #endif #endif mutex_for_fo = kmalloc(sizeof(struct mutex), GFP_KERNEL); if (mutex_for_fo == NULL) { dev_err(&pdev->dev, "failed to create mutex handle\n"); goto out; } #ifdef I2C_BASE mutex_for_i2c = kmalloc(sizeof(struct mutex), GFP_KERNEL); if (mutex_for_i2c == NULL) { dev_err(&pdev->dev, "failed to create mutex handle\n"); goto out; } mutex_init(mutex_for_i2c); #endif mutex_init(mutex_for_fo); #ifdef CONFIG_CPU_S5PV210 /* added for phy cut off when boot up */ clk_enable(s5ptv_status.i2c_phy_clk); __s5p_hdmi_phy_power(false); clk_disable(s5ptv_status.i2c_phy_clk); s5p_tv_clk_gate(false); #endif regulator_disable(s5ptv_status.tv_tv); regulator_disable(s5ptv_status.tv_tvout); printk("tv_base_probe is successfully\n"); return 0; #ifdef CONFIG_TV_FB err_alloc: #endif out_tvenc_irq: free_irq(IRQ_HDMI, pdev); out_hdmi_irq: free_irq(IRQ_MIXER, pdev); out: printk(KERN_ERR "not found (%d). \n", ret); return ret; }
static inline void omap2_mbox_shutdown(struct omap_mbox *mbox) { clk_disable(mbox_ick_handle); clk_put(mbox_ick_handle); }
int s5p_tv_clk_gate(bool on) { if (on) { if (!is_tv_clk_on) { #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_enable("vp_pd") < 0) { printk(KERN_ERR "[Error]The power is not on for VP\n"); goto err_pm; } #endif clk_enable(s5ptv_status.vp_clk); #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_enable("mixer_pd") < 0) { printk(KERN_ERR "[Error]The power is not on for mixer\n"); goto err_pm; } #endif clk_enable(s5ptv_status.mixer_clk); #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_enable("tv_enc_pd") < 0) { printk(KERN_ERR "[Error]The power is not on for TV ENC\n"); goto err_pm; } #endif clk_enable(s5ptv_status.tvenc_clk); #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_enable("hdmi_pd") < 0) { printk(KERN_ERR "[Error]The power is not on for HDMI\n"); goto err_pm; } #endif clk_enable(s5ptv_status.hdmi_clk); is_tv_clk_on = true; } } else { if (is_tv_clk_on) { /* off */ clk_disable(s5ptv_status.vp_clk); #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_disable("vp_pd") < 0) { printk(KERN_ERR "[Error]The power is not off for VP\n"); goto err_pm; } #endif clk_disable(s5ptv_status.mixer_clk); #ifdef CONFIG_S5PV210_PM if (0 != s5pv210_pd_disable("mixer_pd")) { printk(KERN_ERR "[Error]The power is not off for mixer\n"); goto err_pm; } #endif clk_disable(s5ptv_status.tvenc_clk); #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_disable("tv_enc_pd") < 0) { printk(KERN_ERR "[Error]The power is not off for TV ENC\n"); goto err_pm; } #endif clk_disable(s5ptv_status.hdmi_clk); #ifdef CONFIG_S5PV210_PM if (s5pv210_pd_disable("hdmi_pd") < 0) { printk(KERN_ERR "[Error]The power is not off for HDMI\n"); goto err_pm; } #endif is_tv_clk_on = false; } } return 0; #ifdef CONFIG_S5PV210_PM err_pm: return -1; #endif }
static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) { struct rtc_time *alm_tm = &alrm->time; void __iomem *base = s3c_rtc_base; unsigned int alm_en; clk_enable(rtc_clk); alm_tm->tm_sec = readb(base + S3C2410_ALMSEC); alm_tm->tm_min = readb(base + S3C2410_ALMMIN); alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR); alm_tm->tm_mon = readb(base + S3C2410_ALMMON); alm_tm->tm_mday = readb(base + S3C2410_ALMDATE); alm_tm->tm_year = readb(base + S3C2410_ALMYEAR); alm_en = readb(base + S3C2410_RTCALM); alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", alm_en, 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); /* decode the alarm enable field */ if (alm_en & S3C2410_RTCALM_SECEN) alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); else alm_tm->tm_sec = -1; if (alm_en & S3C2410_RTCALM_MINEN) alm_tm->tm_min = bcd2bin(alm_tm->tm_min); else alm_tm->tm_min = -1; if (alm_en & S3C2410_RTCALM_HOUREN) alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); else alm_tm->tm_hour = -1; if (alm_en & S3C2410_RTCALM_DAYEN) alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); else alm_tm->tm_mday = -1; if (alm_en & S3C2410_RTCALM_MONEN) { alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); alm_tm->tm_mon -= 1; } else { alm_tm->tm_mon = -1; } if (alm_en & S3C2410_RTCALM_YEAREN) alm_tm->tm_year = bcd2bin(alm_tm->tm_year); else alm_tm->tm_year = -1; clk_disable(rtc_clk); return 0; }
static int tegra_camera_disable_emc(struct tegra_camera_dev *dev) { clk_disable(dev->emc_clk); return tegra_emc_enable_eack(); }
/* * davinci_spi_probe - probe function for SPI Master Controller * @pdev: platform_device structure which contains plateform specific data * * According to Linux Device Model this function will be invoked by Linux * with plateform_device struct which contains the device specific info. * This function will map the SPI controller's memory, register IRQ, * Reset SPI controller and setting its registers to default value. * It will invoke spi_bitbang_start to create work queue so that client driver * can register transfer method to work queue. */ static int davinci_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct davinci_spi *davinci_spi; struct davinci_spi_platform_data *pdata; struct resource *r, *mem; resource_size_t dma_rx_chan = DAVINCI_SPI_NO_RESOURCE; resource_size_t dma_tx_chan = DAVINCI_SPI_NO_RESOURCE; resource_size_t dma_eventq = DAVINCI_SPI_NO_RESOURCE; int i = 0, ret = 0; pdata = pdev->dev.platform_data; if (pdata == NULL) { ret = -ENODEV; goto err; } master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); if (master == NULL) { ret = -ENOMEM; goto err; } dev_set_drvdata(&pdev->dev, master); davinci_spi = spi_master_get_devdata(master); if (davinci_spi == NULL) { ret = -ENOENT; goto free_master; } r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (r == NULL) { ret = -ENOENT; goto free_master; } davinci_spi->pbase = r->start; davinci_spi->region_size = resource_size(r); davinci_spi->pdata = pdata; mem = request_mem_region(r->start, davinci_spi->region_size, pdev->name); if (mem == NULL) { ret = -EBUSY; goto free_master; } davinci_spi->base = (struct davinci_spi_reg __iomem *) ioremap(r->start, davinci_spi->region_size); if (davinci_spi->base == NULL) { ret = -ENOMEM; goto release_region; } davinci_spi->irq = platform_get_irq(pdev, 0); if (davinci_spi->irq <= 0) { ret = -EINVAL; goto unmap_io; } ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED, dev_name(&pdev->dev), davinci_spi); if (ret != 0) { ret = -EAGAIN; goto unmap_io; } /* Allocate tmp_buf for tx_buf */ davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL); if (davinci_spi->tmp_buf == NULL) { ret = -ENOMEM; goto err1; } davinci_spi->bitbang.master = spi_master_get(master); if (davinci_spi->bitbang.master == NULL) { ret = -ENODEV; goto free_tmp_buf; } davinci_spi->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(davinci_spi->clk)) { ret = -ENODEV; goto put_master; } clk_enable(davinci_spi->clk); master->bus_num = pdev->id; master->num_chipselect = pdata->num_chipselect; master->setup = davinci_spi_setup; master->cleanup = davinci_spi_cleanup; davinci_spi->bitbang.chipselect = davinci_spi_chipselect; davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; davinci_spi->version = pdata->version; use_dma = pdata->use_dma; davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; if (davinci_spi->version == SPI_VERSION_2) davinci_spi->bitbang.flags |= SPI_READY; if (use_dma) { dma_rx_chan = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_RX_CHAN); dma_tx_chan = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_TX_CHAN); dma_eventq = davinci_spi_get_dma_by_flag(pdev, IORESOURCE_DMA_EVENT_Q); } if (!use_dma || dma_rx_chan == DAVINCI_SPI_NO_RESOURCE || dma_tx_chan == DAVINCI_SPI_NO_RESOURCE || dma_eventq == DAVINCI_SPI_NO_RESOURCE) { davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; use_dma = 0; } else { davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; davinci_spi->dma_channels = kzalloc(master->num_chipselect * sizeof(struct davinci_spi_dma), GFP_KERNEL); if (davinci_spi->dma_channels == NULL) { ret = -ENOMEM; goto free_clk; } for (i = 0; i < master->num_chipselect; i++) { davinci_spi->dma_channels[i].dma_rx_channel = -1; davinci_spi->dma_channels[i].dma_rx_sync_dev = dma_rx_chan; davinci_spi->dma_channels[i].dma_tx_channel = -1; davinci_spi->dma_channels[i].dma_tx_sync_dev = dma_tx_chan; davinci_spi->dma_channels[i].eventq = dma_eventq; } dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" "Using RX channel = %d , TX channel = %d and " "event queue = %d", dma_rx_chan, dma_tx_chan, dma_eventq); } davinci_spi->get_rx = davinci_spi_rx_buf_u8; davinci_spi->get_tx = davinci_spi_tx_buf_u8; init_completion(&davinci_spi->done); /* Reset In/OUT SPI module */ iowrite32(0, davinci_spi->base + SPIGCR0); udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); /* Clock internal */ if (davinci_spi->pdata->clk_internal) set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); else clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); /* master mode default */ set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); if (davinci_spi->pdata->intr_level) iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); else iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); ret = spi_bitbang_start(&davinci_spi->bitbang); if (ret != 0) goto free_clk; dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base); if (!pdata->poll_mode) dev_info(&pdev->dev, "Operating in interrupt mode" " using IRQ %d\n", davinci_spi->irq); return ret; free_clk: clk_disable(davinci_spi->clk); clk_put(davinci_spi->clk); put_master: spi_master_put(master); free_tmp_buf: kfree(davinci_spi->tmp_buf); err1: free_irq(davinci_spi->irq, davinci_spi); unmap_io: iounmap(davinci_spi->base); release_region: release_mem_region(davinci_spi->pbase, davinci_spi->region_size); free_master: kfree(master); err: return ret; }
static int s5p_g2d_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { s5p_g2d_params *params; ROT_DEG eRotDegree; int ret = 0; #ifdef G2D_DEBUG printk("##########%s:start \n", __FUNCTION__); #endif params = (s5p_g2d_params*)file->private_data; if (copy_from_user(params, (s5p_g2d_params*)arg, sizeof(s5p_g2d_params))) { return -EFAULT; } #ifndef G2D_CLK_CTRL clk_enable(s5p_g2d_clock); #else s5p_g2d_clk_enable(); #endif #if 0 //Handle G2D limitation for 1:x and x:1 input /* G2D work around */ if((params->src_work_width == 1) || (params->src_work_height == 1) || (params->dst_work_width == 1) || (params->dst_work_height == 1)) { params->dst_start_x = 0; params->dst_start_y = 0; if((cmd == S3C_G2D_ROTATOR_0) || (cmd == S3C_G2D_ROTATOR_180)) { if((params->src_work_width == 1) || (params->dst_work_width == 1)) { params->src_work_width++; params->dst_work_width++; if(params->src_work_width + params->src_start_x > params->src_full_width) params->src_start_x = (params->src_start_x > 0)? (params->src_start_x - 1):params->src_start_x; } if((params->src_work_height == 1) || (params->dst_work_height == 1)) { params->src_work_height++; params->dst_work_height++; if(params->src_work_height + params->src_start_y > params->src_full_height) params->src_start_y = (params->src_start_y > 0)? (params->src_start_y - 1):params->src_start_y; } } else { if((params->src_work_width == 1) || (params->dst_work_height == 1)) { params->src_work_width++; params->dst_work_height++; if(params->src_work_width + params->src_start_x > params->src_full_width) params->src_start_x = (params->src_start_x > 0)? (params->src_start_x - 1):params->src_start_x; } if((params->src_work_height == 1) || (params->dst_work_width == 1)){ params->src_work_height++; params->dst_work_width++; if(params->src_work_height + params->src_start_y > params->src_full_height) params->src_start_y = (params->src_start_y > 0)? (params->src_start_y - 1):params->src_start_y; } } } #endif mutex_lock(h_rot_mutex); switch(cmd) { case S3C_G2D_ROTATOR_0: eRotDegree = ROT_0; ret = s5p_g2d_start(params, eRotDegree); break; case S3C_G2D_ROTATOR_90: eRotDegree = ROT_90; ret = s5p_g2d_start(params, eRotDegree); break; case S3C_G2D_ROTATOR_180: eRotDegree = ROT_180; ret = s5p_g2d_start(params, eRotDegree); break; case S3C_G2D_ROTATOR_270: eRotDegree = ROT_270; ret = s5p_g2d_start(params, eRotDegree); break; case S3C_G2D_ROTATOR_X_FLIP: eRotDegree = ROT_X_FLIP; ret = s5p_g2d_start(params, eRotDegree); break; case S3C_G2D_ROTATOR_Y_FLIP: eRotDegree = ROT_Y_FLIP; ret = s5p_g2d_start(params, eRotDegree); break; default: ret = -EINVAL; goto err_cmd; } if(ret != 0){ printk(KERN_ERR "\n%s:G2d error !!!!\n"); goto err_cmd; } // block mode if(!(file->f_flags & O_NONBLOCK)) { if (interruptible_sleep_on_timeout(&waitq_g2d, msecs_to_jiffies(G2D_TIMEOUT)) == 0) { #ifdef G2D_DEBUG printk(KERN_ERR "\n%s: Waiting for interrupt is timeout\n", __FUNCTION__); printk("###2##%s::src_fw %d src_fh %d src_w %d src_h %d src_x %d src_y %d dst_fw %d dst_fh %d dst_w %d dst_h %d dst_x %d dst_y %d cmd %d\n", __FUNCTION__, params->src_full_width, params->src_full_height, params->src_work_width, params->src_work_height, params->src_start_x, params->src_start_y, params->dst_full_width, params->dst_full_height, params->dst_work_width, params->dst_work_height, params->dst_start_x, params->dst_start_y, cmd); #endif //ret = -EINVAL; ret = 0; } } #ifdef G2D_DEBUG printk("##########%s:end \n", __FUNCTION__); #endif err_cmd: s5p_g2d_cache_reset(); #ifndef G2D_CLK_CTRL clk_disable(s5p_g2d_clock); #else s5p_g2d_clk_disable(); #endif mutex_unlock(h_rot_mutex); return ret; }