static void
commpage_init_cpu_capabilities( void )
{
uint64_t bits;
int cpus;
ml_cpu_info_t cpu_info;
bits = 0;
ml_cpu_get_info(&cpu_info);
switch (cpu_info.vector_unit) {
case 9:
bits |= kHasAVX1_0;
/* fall thru */
case 8:
bits |= kHasSSE4_2;
/* fall thru */
case 7:
bits |= kHasSSE4_1;
/* fall thru */
case 6:
bits |= kHasSupplementalSSE3;
/* fall thru */
case 5:
bits |= kHasSSE3;
/* fall thru */
case 4:
bits |= kHasSSE2;
/* fall thru */
case 3:
bits |= kHasSSE;
/* fall thru */
case 2:
bits |= kHasMMX;
default:
break;
}
switch (cpu_info.cache_line_size) {
case 128:
bits |= kCache128;
break;
case 64:
bits |= kCache64;
break;
case 32:
bits |= kCache32;
break;
default:
break;
}
cpus = commpage_cpus(); // how many CPUs do we have
bits |= (cpus << kNumCPUsShift);
bits |= kFastThreadLocalStorage; // we use %gs for TLS
#define setif(_bits, _bit, _condition) \
if (_condition) _bits |= _bit
setif(bits, kUP, cpus == 1);
setif(bits, k64Bit, cpu_mode_is64bit());
setif(bits, kSlow, tscFreq <= SLOW_TSC_THRESHOLD);
setif(bits, kHasAES, cpuid_features() &
CPUID_FEATURE_AES);
setif(bits, kHasF16C, cpuid_features() &
CPUID_FEATURE_F16C);
setif(bits, kHasRDRAND, cpuid_features() &
CPUID_FEATURE_RDRAND);
setif(bits, kHasFMA, cpuid_features() &
CPUID_FEATURE_FMA);
setif(bits, kHasBMI1, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_BMI1);
setif(bits, kHasBMI2, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_BMI2);
setif(bits, kHasRTM, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_RTM);
setif(bits, kHasHLE, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_HLE);
setif(bits, kHasAVX2_0, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_AVX2);
setif(bits, kHasRDSEED, cpuid_features() &
CPUID_LEAF7_FEATURE_RDSEED);
setif(bits, kHasADX, cpuid_features() &
CPUID_LEAF7_FEATURE_ADX);
setif(bits, kHasMPX, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_MPX);
setif(bits, kHasSGX, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_SGX);
uint64_t misc_enable = rdmsr64(MSR_IA32_MISC_ENABLE);
setif(bits, kHasENFSTRG, (misc_enable & 1ULL) &&
(cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_ERMS));
_cpu_capabilities = bits; // set kernel version for use by drivers etc
}
static void
commpage_init_cpu_capabilities( void )
{
uint64_t bits;
int cpus;
ml_cpu_info_t cpu_info;
bits = 0;
ml_cpu_get_info(&cpu_info);
switch (cpu_info.vector_unit) {
case 9:
bits |= kHasAVX1_0;
/* fall thru */
case 8:
bits |= kHasSSE4_2;
/* fall thru */
case 7:
bits |= kHasSSE4_1;
/* fall thru */
case 6:
bits |= kHasSupplementalSSE3;
/* fall thru */
case 5:
bits |= kHasSSE3;
/* fall thru */
case 4:
bits |= kHasSSE2;
/* fall thru */
case 3:
bits |= kHasSSE;
/* fall thru */
case 2:
bits |= kHasMMX;
default:
break;
}
switch (cpu_info.cache_line_size) {
case 128:
bits |= kCache128;
break;
case 64:
bits |= kCache64;
break;
case 32:
bits |= kCache32;
break;
default:
break;
}
cpus = commpage_cpus(); // how many CPUs do we have
/** Sinetek: by default we'd like some reasonable values,
** so that the userspace runs correctly.
**
** On Mountain Lion, kHasSSE4_2 provides vanilla SSE2 routines.
** On Mavericks, we need a bit more support: SSE3, SSE3X.
**/
if (IsAmdCPU()) {
bits |= kHasSSE4_2;
bits &= ~kHasSupplementalSSE3;
#define MAVERICKS_AMD
#ifdef MAVERICKS_AMD
bits |= kHasSSE3;
// bits |= kHasSupplementalSSE3;
bits &= ~kHasSSE4_2;
#endif
}
bits |= (cpus << kNumCPUsShift);
bits |= kFastThreadLocalStorage; // we use %gs for TLS
#define setif(_bits, _bit, _condition) \
if (_condition) _bits |= _bit
setif(bits, kUP, cpus == 1);
setif(bits, k64Bit, cpu_mode_is64bit());
setif(bits, kSlow, tscFreq <= SLOW_TSC_THRESHOLD);
setif(bits, kHasAES, cpuid_features() &
CPUID_FEATURE_AES);
setif(bits, kHasF16C, cpuid_features() &
CPUID_FEATURE_F16C);
setif(bits, kHasRDRAND, cpuid_features() &
CPUID_FEATURE_RDRAND);
setif(bits, kHasFMA, cpuid_features() &
CPUID_FEATURE_FMA);
setif(bits, kHasBMI1, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_BMI1);
setif(bits, kHasBMI2, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_BMI2);
setif(bits, kHasRTM, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_RTM);
setif(bits, kHasHLE, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_HLE);
setif(bits, kHasAVX2_0, cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_AVX2);
uint64_t misc_enable = rdmsr64(MSR_IA32_MISC_ENABLE);
setif(bits, kHasENFSTRG, (misc_enable & 1ULL) &&
(cpuid_leaf7_features() &
CPUID_LEAF7_FEATURE_ENFSTRG));
_cpu_capabilities = bits; // set kernel version for use by drivers etc
}