示例#1
0
BYTE lcd_read_byte(void)
{
   BYTE low,high;

 #if defined(__PCB__)
   set_tris_lcd(LCD_INPUT_MAP);
 #else
  #if (defined(LCD_DATA4) && defined(LCD_DATA5) && defined(LCD_DATA6) && defined(LCD_DATA7))
   output_float(LCD_DATA4);
   output_float(LCD_DATA5);
   output_float(LCD_DATA6);
   output_float(LCD_DATA7);
  #else
   lcdtris.data = 0xF;
  #endif
 #endif
        
   lcd_output_rw(1);
   delay_cycles(1);
   lcd_output_enable(1);
   delay_cycles(1);
   high = lcd_read_nibble();
      
   lcd_output_enable(0);
   delay_cycles(1);
   lcd_output_enable(1);
   delay_us(1);
   low = lcd_read_nibble();
      
   lcd_output_enable(0);

 #if defined(__PCB__)
   set_tris_lcd(LCD_INPUT_MAP);
 #else
  #if (defined(LCD_DATA4) && defined(LCD_DATA5) && defined(LCD_DATA6) && defined(LCD_DATA7))
   output_drive(LCD_DATA4);
   output_drive(LCD_DATA5);
   output_drive(LCD_DATA6);
   output_drive(LCD_DATA7);
  #else
   lcdtris.data = 0x0;
  #endif
 #endif

   return( (high<<4) | low);
}
/**
 * \brief Delay loop to delay at least n number of microseconds
 *
 * \param n  Number of microseconds to wait
 */
void delay_cycles_us(
		uint32_t n)
{
	while (n--) {
		/* Divide up to blocks of 10u */
		delay_cycles(cycles_per_us);
	}
}
/**
 * \brief Delay loop to delay at least n number of milliseconds
 *
 * \param n  Number of milliseconds to wait
 */
void delay_cycles_ms(
		uint32_t n)
{
	while (n--) {
		/* Devide up to blocks of 1ms */
		delay_cycles(cycles_per_ms);
	}
}
BYTE lcd_read_byte() {
      BYTE low,high;
      set_tris_lcd(LCD_READ);
      lcd.rw = 1;
      delay_cycles(1);
      lcd.enable = 1;
      delay_cycles(1);
      high = lcd.data;
      lcd.enable = 0;
      delay_cycles(1);
      lcd.enable = 1;
      delay_us(1);
      low = lcd.data;
      lcd.enable = 0;
      set_tris_lcd(LCD_WRITE);
      return( (high<<4) | low);
}
示例#5
0
void ncr5380n_device::send_byte()
{
	state = (state & STATE_MASK) | (SEND_WAIT_SETTLE << SUB_SHIFT);
	scsi_bus->data_w(scsi_refid, m_dmalatch);

	scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
	scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
	delay_cycles(sync_period);
}
示例#6
0
static void write_nibble(unsigned char nibble) {
    io_lcd_assert_bus(nibble_map[nibble]);

    io_lcd_assert_e();
    delay_cycles(SystemCoreClock / 1000000 / 2);
    io_lcd_deassert_e();

    io_lcd_release_bus();
}
示例#7
0
static unsigned char read_nibble(void) {
    io_lcd_assert_e();
    delay_cycles(SystemCoreClock / 1000000 / 2);

    unsigned char nibble = io_lcd_read_bus();
    io_lcd_deassert_e();

    return nibble_map[nibble];    
}
示例#8
0
文件: pwm.c 项目: dromer/msp3n1s
int
main(void)
{
	watchdog_off();
	clock_init_1MHz();

	/* set all pins to output high */
	port1_direction = 0xFF;
	port1_output = 0xFF;

	pin_low(LED1);

	pin_function_primary(LED2);
	/* set capture/compare module 1 in reset/set output mode,
	 * that is:
	 *   pin 1.6 is set high when timera_count == timera_cc0
	 *   pin 1.6 is set low  when timera_count == timera_cc1
	 */
	timera_cc1_config(TIMERA_CC_OUTPUT_RESETSET);

	/* use the system clock as timer source,
	 * count from 0 up to timera_cc0 before resetting the counter,
	 * and reset the counter now */
	timera_config(TIMERA_CLOCK_SMCLK | TIMERA_MODE_UP | TIMERA_CLEAR);

	/* count from 0 to 1024, that is a frequency of
	 * 1 MHz / 1024 = just under 1kHz. */
	timera_cc0 = 1024;

	while (1) {
		/* sweep timer_cc1 up */
		for (timera_cc1 = 1; timera_cc1 < 1024; timera_cc1 <<= 1)
			delay_cycles(50000);

		/* ..and down in exponential steps */
		do {
			timera_cc1 >>= 1;
			timera_clear();
			delay_cycles(50000);
		} while (timera_cc1 > 0);
		delay_cycles(50000);
	}
}
static void LCD_SPI_SS(bool select)
{
    delay_cycles(0x4FFF);

    GPBCON&=~0x30000;
    GPBCON|=0x10000;

    if(select)
        GPBDAT|=0x100;
    else
        GPBDAT&=~0x100;
}
示例#10
0
byte _spi_read()
{
	int i;
	byte ch=0;

	for(i=0; i<8; i++)
	{
		output_low(NRF_SCK);

		//delay_us(1);
		delay_cycles(1);
		output_high(NRF_SCK);
		//delay_us(1);
		delay_cycles(1);
		if(input(NRF_DI))
			bit_set(ch, 7-i);
	}	
	
	output_low(NRF_SCK);
	
	return ch;
}
示例#11
0
byte _spi_write(byte nData)
{
	int i, resp;
	resp = 0;
	output_low(NRF_SCK);
	for(i=0; i<8; i++)
	{
		resp <<= 1;
		if(bit_test(nData, 7-i))
			output_high(NRF_DO);
		else
			output_low(NRF_DO);
		//delay_us(1);
		delay_cycles(1);
		output_high(NRF_SCK);
		//delay_us(1);
		delay_cycles(1);
		output_low(NRF_SCK);
		resp |= input(NRF_DI);
	}	
	return resp;
}
示例#12
0
void go_to_sleep()
{
   clear_interrupt(INT_EXT);        // RTC
   
   set_usart_int();

   wakeup_mode = WAKEON_BAD;
   
   kill_wd();
   
   sleep();
   delay_cycles(1); // pre-fetched NOP
}
void vfd_putc(char data)
{
  int8 i;
  output_low(VFD_SCK);
  if (input(VFD_MB)) {
   while (input(VFD_MB)) { }
   delay_us(10);
  }
  output_low(VFD_SS);
  for (i=0;i<8;i++) {
   output_bit(VFD_SIN,data & 0b10000000);
   output_high(VFD_SCK);
   output_low(VFD_SCK);
#IFNDEF VFD_ULTRAFAST
   delay_cycles(4);
#ENDIF
   data <<= 1;
  }
  output_high(VFD_SS);
#IFNDEF VFD_ULTRAFAST
  delay_cycles(4);
#ENDIF
}
示例#14
0
uint8_t spi_transfer(uint8_t message)
{
	uint8_t* reg_ptr;
	uint8_t timeout = SPI_TIMEOUT;
	uint8_t receive_char;
	uint8_t i, temp, temp2;
	
	reg_ptr = SPDR_BASE;
	
	// Commence the SPI message.
	SS_set_low();
	*reg_ptr = message;
		
	reg_ptr = SPSR_BASE;

	while(!(*reg_ptr & SPI_SPSR_SPIF))		// Check if the transmission has completed yet.
	{
		if(!timeout--)
		{
			//SS_set_high();
			return 0x00;						// Something went wrong, so the function times out.
			if(SELF_ID != 1)
			{
				PIN_toggle(LED2);
			}
		}
	}	

	
	reg_ptr = SPDR_BASE;
	receive_char = *reg_ptr;
	
		//SS_set_high();
		
		delay_cycles(10);
	// I was assuming that SPI messages would be received MSB first.
	// Comment out the following if that is not the case.
	
	//temp = 0, temp2 = 0;
	//
	//for (i = 0; i < 8; i ++)
	//{
		//temp2 = receive_char << (7 - i);	// reverses the order of the bits.
		//temp2 = temp2 >> 7;
		//temp2 = temp2 << (7 - i);		
		//temp += temp2;
	//}
	
	return receive_char;					// Transmission was successful, return the character that was received.
}
示例#15
0
//------------------------------------- 
void lcd_send_nibble(char nibble) 
{ 
	// Note:  !! converts an integer expression 
	// to a boolean (1 or 0). 
	output_bit(LCD_DB4, !!(nibble & 1)); 
	output_bit(LCD_DB5, !!(nibble & 2));  
	output_bit(LCD_DB6, !!(nibble & 4));    
	output_bit(LCD_DB7, !!(nibble & 8));    
	
	delay_cycles(1); 
	output_high(LCD_E); 
	delay_us(2); 
	output_low(LCD_E); 
} 
示例#16
0
char lcd_read_byte(void) 
{ 
	char low; 
	char high; 
	
	output_high(LCD_RW); 
	delay_cycles(1); 
	
	high = lcd_read_nibble(); 
	
	low = lcd_read_nibble(); 
	
	return( (high<<4) | low); 
} 
示例#17
0
uint8_t spi_transfer2(uint8_t message)
{
	uint8_t* reg_ptr;
	uint8_t timeout = SPI_TIMEOUT;
	uint8_t receive_char;
	uint8_t i, temp, temp2;
	
	//cmd_str(SRES);
	
	reg_ptr = SPDR_BASE;
	
	// Commence the SPI message.
	PORTD &= (0xF7);
	//delay_cycles(10);
	*reg_ptr = message;
	//delay_cycles(10);
	reg_ptr = SPSR_BASE;

	while(!(*reg_ptr & SPI_SPSR_SPIF))		// Check if the transmission has completed yet.
	{
		if(!timeout--)
		{
			SS_set_high();
			return 0x00;						// Something went wrong, so the function times out.
		}
	}
	delay_cycles(7);
	SS_set_high();
	
	delay_cycles(10);
		
	reg_ptr = SPDR_BASE;
	receive_char = *reg_ptr;
		
	return receive_char;					// Transmission was successful, return the character that was received.
}
示例#18
0
void init_rs232() {
   bit_clear(PIR1,4);  //TXIF=0
   bit_clear(PIR1,5);  //RCIF=0
   bit_clear(PIE1,5);  //RCIE=0
   bit_clear(RCSTA,7); //SPEN=0
   bit_clear(RCSTA,4); //CREN=0
    bit_clear(TXSTA,4); //SYNC=0
    bit_clear(TXSTA,5); //TXEN=0
   delay_cycles(10);
   bit_set(RCSTA,4); //CREN=1
   bit_set(RCSTA,7); //SPEN=1
    bit_set(TXSTA,5); //TXEN=1
   bit_set(PIE1,5); //RCIE=1

}
示例#19
0
char vs_spi_write(char aa){
char h;
char i;
	h=0;
	i=7;
	XCLK_l=0;delay_cycles(10);
	do{ 
		XDI_l=bit_test(aa,i);	
		XCLK_l=1;
		delay_us(10);
		if(XDO==1){bit_set(h,i);}	
		XCLK_l=0;
		delay_us(10);
	}while((i--)>0);
	return (h);
}
示例#20
0
文件: lcd.c 项目: Manouchehri/ELN9204
void sendLCD(int address, int n)
{
    output_low (LCD_E);
    delay_us (60); /*Might be a little long?*/

    if(address)
        output_high (LCD_RS);
    else
        output_low (LCD_RS);

    delay_cycles(1);
    output_d (n);
    output_high (LCD_E);
    delay_ms (1);
    output_low (LCD_E);
    delay_ms(5);
}
示例#21
0
void lcd_send_nibble(BYTE n)
{
  #if (defined(LCD_DATA4) && defined(LCD_DATA5) && defined(LCD_DATA6) && defined(LCD_DATA7))
   /* Write to the data port */
   output_bit(LCD_DATA4, bit_test(n, 0));
   output_bit(LCD_DATA5, bit_test(n, 1));
   output_bit(LCD_DATA6, bit_test(n, 2));
   output_bit(LCD_DATA7, bit_test(n, 3));
  #else      
   lcdlat.data = n;
  #endif
      
   delay_cycles(1);
   lcd_output_enable(1);
   delay_us(2);
   lcd_output_enable(0);
}
示例#22
0
void lcd_send_byte(int8 address, int8 n) 
{ 
   output_low(LCD_RS); 
   delay_us(60);  
    
   if(address) 
      output_high(LCD_RS); 
   else 
      output_low(LCD_RS); 
         
   delay_cycles(1); 
    
   output_low(LCD_E); 
    
   lcd_send_nibble(n >> 4); 
   lcd_send_nibble(n & 0xf); 
} 
示例#23
0
void sendLCD(int address, int n)
{
    output_low (LCD_E);
    delay_us (60);

    if(address)
        output_high (LCD_RS);
    else
        output_low (LCD_RS);

    delay_cycles(1);
    output_d (n);
    output_high (LCD_E);
    delay_ms (1);
    output_low (LCD_E);
    delay_ms(5);
}
示例#24
0
文件: ncr5390.c 项目: clobber/UME
void ncr5390_device::send_byte()
{
	if(!fifo_pos)
		fatalerror("ncr5390_device::send_byte - !fifo_pos\n");

	state = (state & STATE_MASK) | (SEND_WAIT_SETTLE << SUB_SHIFT);
	if((state & STATE_MASK) != INIT_XFR_SEND_PAD &&
		((state & STATE_MASK) != DISC_SEL_SEND_BYTE ||
		command_length))
		scsi_bus->data_w(scsi_refid, fifo_pop());
	else
		scsi_bus->data_w(scsi_refid, 0);

	scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
	scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
	delay_cycles(sync_period);
}
示例#25
0
文件: main.c 项目: catslab/BLE_strain
void ADS()
{
    LED=1;
    ADC_result = 0;
    unsigned int8 i;
    // Start a conversion with a lo pulse on ADC_CONVERT
    //ADC_CS = 0; // LOWER NOT-CS
    ADC_CLK = 0; //  clock low
    delay_cycles(4);
    ADC_CS = 0; // START CONVERT not CS line
    delay_cycles(4);

    for ( i = 0 ; i < 8 ; i++ )
    {
        ADC_CLK = 1;
        delay_cycles(4);
        IF ( !ADC_IN )
        BREAK;
        ELSE
        ADC_CLK = 0;
        delay_cycles(4);
    }

//   IF (8==i) BADDIE(51); // GLOBAL TIMED OUT WARN
    ADC_CLK = 0;   // produce a new lo-to-high clock
    delay_cycles(4);      // wait for a bit

    // now read data
    for (i=0; i<16; i++) {
        ADC_CLK = 1;  // now after rising edge
        delay_cycles(8);      // OR input pin with 16bit int
        ADC_result |= ADC_IN; //   OR input pin with 16bit int
        ADC_CLK = 0;   // produce a new lo-to-high clock
        if (i !=15)
            ADC_result=ADC_result<<1;         // and shift that bit along toward MSB
        delay_cycles(4);
    }
    // PREP FOR NEXT CYCLE
    ADC_CLK = 0;
    delay_cycles(8);
    ADC_CS = 1; // SHUT OFF CONVERTER
    LED = 0;
}
void vfd_putc(char data)
{
  int8 i;
  output_low(VFD_CLK);
  output_low(VFD_TX);
  while (input(VFD_BUSY)) { }
  delay_us(10);
  for (i=0;i<8;i++) {
//   disable_interrupts(global);
   output_bit(VFD_TX, shift_left(&data,1,0) );
   delay_cycles(4);
   output_high(VFD_CLK);
//   enable_interrupts(global);
   delay_us(10);
   output_low(VFD_CLK);
   delay_us(10);
  }
}
示例#27
0
char lcd_read_nibble(void) 
{ 
	char retval; 
	// Create bit variables so that we can easily set 
	// individual bits in the retval variable. 
	#bit retval_0 = retval.0 
	#bit retval_1 = retval.1 
	#bit retval_2 = retval.2 
	#bit retval_3 = retval.3 
	
	retval = 0; 
	    
	output_high(LCD_E); 
	delay_cycles(1); 
	
	retval_0 = input(LCD_DB4); 
	retval_1 = input(LCD_DB5); 
	retval_2 = input(LCD_DB6); 
	retval_3 = input(LCD_DB7); 
	  
	output_low(LCD_E); 
	    
	return(retval);    
}    
示例#28
0
文件: main.c 项目: dotignore/GitHub
// Отсюда начинается выполнение пользовательского кода.
// * точка входа
int main(void)
    {
// Светодиоды сидят на порту D и выводах 12 - 15.

// Первым делом надо включить тактирование порту D.
// За это отвечает 3 бит (GPIODEN) в регистре RCC_AHB1ENR (Reference manual, p.110)
        RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN;

// Дальше надо настроить выводы как выходы типа Push-pull, с максимальной частотой,
// например, 50 МГц (от частоты зависит энергопотребление ножки).

// Первый регистр, GPIOx_MODER: режим работы выхода, (RM, p. 148)
// 2 бита на каждую ножку
// 0: Вход, 1: выход, 2: альтернативная функция, 3: аналоговый
        GPIOD->MODER |= (1UL << 12 * 2) | (1UL << 13 * 2) | (1UL << 14 * 2) | (1UL << 15 * 2);

// Второй регистр, GPIOx_OTYPER: тип выхода. Двухтактный (0) али открытый коллектор (1)
// Один бит на каждую ножку. По умолчанию всё так, как и надо.

// Третий регистр, GPIOx_OSPEEDR: максимальная скорость порта.
//				  (199 страница Reference manual)
// По умолчанию 2 МГц, так что ок.

// Четвёртый регистр, GPIOx_PUPDR: куда он будет по умолчанию подтягивать, если выбран двухтактный режим.
// 0: никуда, 1: питание, 2: земля, 3: резервировано. Два бита на вывод.
// Допустим, к питанию.
        GPIOD->PUPDR |= (1UL << 12 * 2) | (1UL << 13 * 2) | (1UL << 14 * 2) | (1UL << 15 * 2);

// Регистр вывода: GPIOx_ODR. Что запишешь, то на ножках и будет.
// Есть регистр для установки битов и для их сброса (GPIOx_BSRR).
// Младшие 2 байта отвечают за установку, старшие - за сброс.

// Жги!
        GPIOD->BSRRL = (1UL << 12) | (1UL << 13) | (1UL << 14) | (1UL << 15);
        delay_cycles(1000000UL);

// Утухни
        GPIOD->BSRRH = (1UL << 12) | (1UL << 13) | (1UL << 14) | (1UL << 15);
        delay_cycles(1000000UL);

// запускаем цикл

        while(1)
        {
/*
// on 13й, задержка включения, off 13
        	GPIOD->BSRRL = (1UL << 13);
        	delay_cycles(500000UL);
// Погасим 13й
        	GPIOD->BSRRH = (1UL << 13);
        	delay_cycles(500000UL);

        	GPIOD->BSRRL = (1UL << 15);
        	delay_cycles(500000UL);
// Погасим 13й
        	GPIOD->BSRRH = (1UL << 15);
        	delay_cycles(500000UL);
*/


// Зажжём 12й
        	GPIOD->BSRRL = (1UL << 12);
        	delay_cycles(200000UL);
// Погасим 12й
        	GPIOD->BSRRH = (1UL << 12);

// Зажжём 15й
            GPIOD->BSRRL = (1UL << 15);
            delay_cycles(200000UL);
// Погасим 15й
            GPIOD->BSRRH = (1UL << 15);

// Зажжём 14й
            GPIOD->BSRRL = (1UL << 14);
            delay_cycles(200000UL);
// Погасим 14й
            GPIOD->BSRRH = (1UL << 14);

// on 13й, задержка включения, off 13
            GPIOD->BSRRL = (1UL << 13);
            delay_cycles(200000UL);
// Погасим 13й
            GPIOD->BSRRH = (1UL << 13);

        }

/*
while(1)
		{
	GPIOD->BSRRL = (1UL << 15);
	delay_cycles(500000UL);
// Погасим 13й
	GPIOD->BSRRH = (1UL << 15);
	delay_cycles(500000UL);
		}
*/

}
示例#29
0
文件: ncr5390.c 项目: clobber/UME
void ncr5390_device::step(bool timeout)
{
	UINT32 ctrl = scsi_bus->ctrl_r();
	UINT32 data = scsi_bus->data_r();
	UINT8 c     = command[0] & 0x7f;

	if(0)
		logerror("%s: state=%d.%d %s\n",
					tag(), state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT,
					timeout ? "timeout" : "change");

	if(mode == MODE_I && !(ctrl & S_BSY)) {
		state = IDLE;
		istatus |= I_DISCONNECT;
		reset_disconnect();
		check_irq();
	}
	switch(state & SUB_MASK ? state & SUB_MASK : state & STATE_MASK) {
	case IDLE:
		break;

	case ARB_COMPLETE << SUB_SHIFT: {
		if(!timeout)
			break;

		int win;
		for(win=7; win>=0 && !(data & (1<<win)); win--);
		if(win != scsi_id) {
			scsi_bus->data_w(scsi_refid, 0);
			scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
			fatalerror("need to wait for bus free\n");
			break;
		}
		state = (state & STATE_MASK) | (ARB_ASSERT_SEL << SUB_SHIFT);
		scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL);
		delay(6);
		break;
	}

	case ARB_ASSERT_SEL << SUB_SHIFT:
		if(!timeout)
			break;

		scsi_bus->data_w(scsi_refid, (1<<scsi_id) | (1<<bus_id));
		state = (state & STATE_MASK) | (ARB_SET_DEST << SUB_SHIFT);
		delay_cycles(4);
		break;

	case ARB_SET_DEST << SUB_SHIFT:
		if(!timeout)
			break;

		state = (state & STATE_MASK) | (ARB_RELEASE_BUSY << SUB_SHIFT);
		scsi_bus->ctrl_w(scsi_refid, c == CD_SELECT_ATN || c == CD_SELECT_ATN_STOP ? S_ATN : 0, S_ATN|S_BSY);
		delay(2);
		break;

	case ARB_RELEASE_BUSY << SUB_SHIFT:
		if(!timeout)
			break;

		if(ctrl & S_BSY) {
			state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
			if(c == CD_RESELECT)
				scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
			delay_cycles(2);
		} else {
			state = (state & STATE_MASK) | (ARB_TIMEOUT_BUSY << SUB_SHIFT);
#ifdef DELAY_HACK
			delay(1);
#else
			delay(8192*select_timeout);
#endif
		}
		break;

	case ARB_DESKEW_WAIT << SUB_SHIFT:
		if(!timeout)
			break;

		scsi_bus->data_w(scsi_refid, 0);
		scsi_bus->ctrl_w(scsi_refid, 0, S_SEL);

		if(c == CD_RESELECT) {
			logerror("%s: mode switch to Target\n", tag());
			mode = MODE_T;
		} else {
			logerror("%s: mode switch to Initiator\n", tag());
			mode = MODE_I;
		}
		state &= STATE_MASK;
		step(true);
		break;

	case ARB_TIMEOUT_BUSY << SUB_SHIFT:
		if(timeout) {
			scsi_bus->data_w(scsi_refid, 0);
			logerror("%s: select timeout\n", tag());
			state = (state & STATE_MASK) | (ARB_TIMEOUT_ABORT << SUB_SHIFT);
			delay(1000);
		} else if(ctrl & S_BSY) {
			state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
			if(c == CD_RESELECT)
				scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
			delay_cycles(2);
		}
		break;

	case ARB_TIMEOUT_ABORT << SUB_SHIFT:
		if(!timeout)
			break;

		if(ctrl & S_BSY) {
			state = (state & STATE_MASK) | (ARB_DESKEW_WAIT << SUB_SHIFT);
			if(c == CD_RESELECT)
				scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
			delay_cycles(2);
		} else {
			scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
			state = IDLE;
			istatus |= I_DISCONNECT;
			reset_disconnect();
			check_irq();
		}
		break;

	case SEND_WAIT_SETTLE << SUB_SHIFT:
		if(!timeout)
			break;

		state = (state & STATE_MASK) | (SEND_WAIT_REQ_0 << SUB_SHIFT);
		step(false);
		break;

	case SEND_WAIT_REQ_0 << SUB_SHIFT:
		if(ctrl & S_REQ)
			break;
		state = state & STATE_MASK;
		scsi_bus->data_w(scsi_refid, 0);
		scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
		step(false);
		break;

	case RECV_WAIT_REQ_1 << SUB_SHIFT:
		if(!(ctrl & S_REQ))
			break;

		state = (state & STATE_MASK) | (RECV_WAIT_SETTLE << SUB_SHIFT);
		delay_cycles(sync_period);
		break;

	case RECV_WAIT_SETTLE << SUB_SHIFT:
		if(!timeout)
			break;

		if((state & STATE_MASK) != INIT_XFR_RECV_PAD)
			fifo_push(scsi_bus->data_r());
		scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
		state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
		step(false);
		break;

	case RECV_WAIT_REQ_0 << SUB_SHIFT:
		if(ctrl & S_REQ)
			break;
		state = state & STATE_MASK;
		step(false);
		break;

	case DISC_SEL_ARBITRATION:
		if(c == CD_SELECT) {
			state = DISC_SEL_WAIT_REQ;
			command_length = derive_msg_size(fifo[0]);
		} else
			state = DISC_SEL_ATN_WAIT_REQ;

		scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
		if(ctrl & S_REQ)
			step(false);
		break;

	case DISC_SEL_ATN_WAIT_REQ:
		if(!(ctrl & S_REQ))
			break;
		if((ctrl & S_PHASE_MASK) != S_PHASE_MSG_OUT) {
			function_complete();
			break;
		}
		if(c == CD_SELECT_ATN)
			scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
		state = DISC_SEL_ATN_SEND_BYTE;
		send_byte();
		break;

	case DISC_SEL_ATN_SEND_BYTE:
		if(c == CD_SELECT_ATN_STOP) {
			seq = 1;
			function_complete();
		} else {
			command_length = derive_msg_size(fifo[0]);
			state = DISC_SEL_WAIT_REQ;
		}
		break;

	case DISC_SEL_WAIT_REQ:
		if(!(ctrl & S_REQ))
			break;
		if((ctrl & S_PHASE_MASK) != S_PHASE_COMMAND) {
			if(!command_length)
				seq = 4;
			scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
			function_bus_complete();
			break;
		}
		if(seq < 3)
			seq = 3;
		state = DISC_SEL_SEND_BYTE;
		send_byte();
		break;

	case DISC_SEL_SEND_BYTE:
		if(command_length) {
			command_length--;
			if(!command_length)
				seq = 4;
		}

		state = DISC_SEL_WAIT_REQ;
		break;

	case INIT_CPT_RECV_BYTE_ACK:
		state = INIT_CPT_RECV_WAIT_REQ;
		scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
		break;

	case INIT_CPT_RECV_WAIT_REQ:
		if(!(ctrl & S_REQ))
			break;

		if((ctrl & S_PHASE_MASK) != S_PHASE_MSG_IN) {
			command_pos = 0;
			bus_complete();
		} else {
			state = INIT_CPT_RECV_BYTE_NACK;
			recv_byte();
		}
		break;

	case INIT_CPT_RECV_BYTE_NACK:
		scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
		function_complete();
		break;

	case INIT_MSG_WAIT_REQ:
		if((ctrl & (S_REQ|S_BSY)) == S_BSY)
			break;
		bus_complete();
		break;

	case INIT_XFR:
		switch(xfr_phase) {
		case S_PHASE_DATA_OUT:
			dma_set(DMA_OUT);
			if(tcount == 0 && fifo_pos == 1)
				scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
			state = INIT_XFR_SEND_BYTE;
			send_byte();
			break;

		case S_PHASE_DATA_IN:
			dma_set(DMA_IN);
			state = tcount == fifo_pos+1 ?
				INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK;
			recv_byte();
			break;

		default:
			logerror("%s: xfer on phase %d\n", tag(), scsi_bus->ctrl_r() & S_PHASE_MASK);
			function_complete();
			break;
		}
		break;

	case INIT_XFR_WAIT_REQ:
		if(!(ctrl & S_REQ))
			break;

		if((ctrl & S_PHASE_MASK) != xfr_phase) {
			command_pos = 0;
			bus_complete();
		} else {
			state = INIT_XFR;
			step(false);
		}
		break;

	case INIT_XFR_SEND_BYTE:
		if(tcount == 0 && fifo_pos == 0)
			bus_complete();
		else
			state = INIT_XFR_WAIT_REQ;
		break;

	case INIT_XFR_RECV_BYTE_ACK:
		state = INIT_XFR_WAIT_REQ;
		scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
		break;

	case INIT_XFR_RECV_BYTE_NACK:
		function_complete();
		break;

	case INIT_XFR_SEND_PAD_WAIT_REQ:
		if(!(ctrl & S_REQ))
			break;

		if((ctrl & S_PHASE_MASK) != xfr_phase) {
			command_pos = 0;
			bus_complete();
		} else {
			state = INIT_XFR_SEND_PAD;
			send_byte();
		}
		break;

	case INIT_XFR_SEND_PAD:
		tcount--;
		if(tcount) {
			state = INIT_XFR_SEND_PAD_WAIT_REQ;
			step(false);
		} else
			function_complete();
		break;

	case INIT_XFR_RECV_PAD_WAIT_REQ:
		if(!(ctrl & S_REQ))
			break;

		if((ctrl & S_PHASE_MASK) != xfr_phase) {
			command_pos = 0;
			bus_complete();
		} else {
			state = INIT_XFR_RECV_PAD;
			recv_byte();
		}
		break;

	case INIT_XFR_RECV_PAD:
		tcount--;
		if(tcount) {
			state = INIT_XFR_RECV_PAD_WAIT_REQ;
			scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
			step(false);
		} else
			function_complete();
		break;

	default:
		logerror("%s: step() unexpected state %d.%d\n",
					tag(),
					state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT);
		exit(0);
	}
}
示例#30
0
int next_dir_buffer()
{
	unsigned char data[32];
	int32 ccltemp, eocmark;;

	++curr_window;

	if(curr_window==1)
	{
		fp_dir_nentries=0;
		reset_title(&fp_dir_entries[0]);
	} else {
		fp_dir_entries[0] = fp_dir_entries[MAX_DIR_ENTRY];
		fp_dir_nentries=1;
		reset_title(&fp_dir_entries[1]);
	}

	do {		

		if (fp_cur_sector==BPB_SecPerClus)
		{
			// Going to next cluster
			fp_cur_cluster=readfat(fp_cur_cluster);
			fp_cur_sector=0;
		}
	
		eocmark=fp_cur_cluster & 0x0FFFFFFF;		

		if( eocmark<0x0ffffff0 )
		{

			ccltemp=fp_cur_cluster-2;
			ccltemp=ccltemp * (int32)BPB_SecPerClus;
			ccltemp=ccltemp + (int32)datsec;
			ccltemp=ccltemp + (int32)fp_cur_sector;
			if (mmc_open_block(ccltemp) != 0)
			{
				//LED=0;
				error=8;
			}

		 	mmc_skip(fp_sec_offset);
		
			do {				

				int32 ccl;

				mmc_read();
				if((data_lo==0x00)||(data_lo == 0xe5)){//these are either blank entries or deleted ones. probably should escape from the loop if they are blank, but just to be sure we'll look to the end.
					mmc_skip(15); 
				} else {

		
					signed int i;
					char Emm,Pee,Three;
					int32 Largeccl /*, ccltemp */;
					struct t_dir_entry* entry = &fp_dir_entries[fp_dir_nentries];

					for(i=0;i<30;)
					{
						data[i]=data_lo;
						i++;
						data[i]=data_hi;
						i++;
						mmc_read();
					}
					data[i]=data_lo;
					data[i+1]=data_hi;
				
					if ( (data[11] & 0xFCU) == 0x20  && 
							data[0] >= '0' && data[0] <= '9' &&
							data[1] >= '0' && data[1] <= '9' &&
							data[2] >= '0' && data[2] <= '9' &&
							data[3] >= '0' && data[3] <= '9' )
					{
						int indexs[4];
						int16 track;

						for(i=0;i<4;i++)
						{
							indexs[i] = data[i] - 48;
						}

						track = indexs[0]*1000 + indexs[1]*100 + indexs[2]*10 + indexs[3];

							Emm=	data[8];		//Emm=data_lo;
							Pee=	data[9];		//Pee=data_hi;
							Three=	data[10];		//Three=data_lo;
		
							if (	((Emm=='m') || (Emm=='M')|| (Emm=='W')|| (Emm=='w')) && 
									((Pee=='P') || (Pee=='p')|| (Pee=='A')|| (Pee=='a')) && 
									((Three=='3')||(Three=='V')||(Three=='v')) )
							{
								int32 songlength;
								Largeccl= ((int16)data[21]<<8)+data[20];
								Largeccl=Largeccl<<16;
								ccl= ((int32)data[27]<<8)+data[26];


								*(((char*)&songlength)+0)=data[28];
					 			*(((char*)&songlength)+1)=data[29];
								*(((char*)&songlength)+2)=data[30];
								*(((char*)&songlength)+3)=data[31];

								if( track > 0)
								{

									fp_dir_entries[fp_dir_nentries].ccl = ccl+ Largeccl;   //add on the high bytes of the cluster address

									fp_dir_entries[fp_dir_nentries].songlength = songlength;
									fp_dir_entries[fp_dir_nentries].track = track;
			
									entry->tit_offset = 0;
		
									entry->title[entry->tit_p]=' ';
		
									// Entry in 8.3 format
									if( entry->tit_p==31 && !entry->tit_full)
									{	
										get_short_name_entry(entry,data);
									}
		
									
									++fp_dir_nentries;
									++fp_dir_global_entries;
		
									if( fp_dir_nentries < (MAX_DIR_ENTRY+1))
										reset_title(&fp_dir_entries[fp_dir_nentries]);
								
								} else {

									cclzero = ccl+ Largeccl;   //add on the high bytes of the cluster address
									songlengthzero = songlength;

								}
						}
					}  else if ( data[11] == 0x0F )
					{
						get_long_name_entry(entry,data);
					} 
				}
				fp_sec_offset += 16;
			} while ( fp_sec_offset!=0 && fp_dir_nentries<(MAX_DIR_ENTRY+1) );
	
			if( fp_sec_offset == 0 )
			{
				++fp_cur_sector;
			}			

			mmc_skip(256-fp_sec_offset);
			mmc_close_block();
		}

	}while(eocmark<0x0ffffff0 &&  fp_dir_nentries<(MAX_DIR_ENTRY+1)); //	printf("file does not exist!");putc(13);putc(10);	

	delay_cycles(1);

	return (eocmark<0x0ffffff0);
}