static void rtlx_dispatch(struct pt_regs *regs) { do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs); }
void brcm_mips_int1_dispatch(struct pt_regs *regs) { do_IRQ(BCM_LINUX_IPC_1_IRQ,regs); }
asmlinkage inline void pci_intD(struct pt_regs *regs) { do_IRQ(GT_INTD, regs); }
static void ipi_resched_dispatch(void) { do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); }
void brcm_mips_performance_dispatch(struct pt_regs *regs) { if(performance_enabled) do_IRQ(BCM_LINUX_PERFCOUNT_IRQ, regs); }
static void mips_timer_dispatch(void) { do_IRQ(mips_cpu_timer_irq); }
static void vi_timer_irqdispatch(void) { do_IRQ(cp0_compare_irq); }
static void ip32_irq5(void) { do_IRQ(MIPS_CPU_IRQ_BASE + 7); }
static void ar71xx_misc_irq_dispatch(void) { u32 pending; pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); if (pending & MISC_INT_UART) do_IRQ(AR71XX_MISC_IRQ_UART); else if (pending & MISC_INT_DMA) do_IRQ(AR71XX_MISC_IRQ_DMA); else if (pending & MISC_INT_PERFC) do_IRQ(AR71XX_MISC_IRQ_PERFC); else if (pending & MISC_INT_TIMER) do_IRQ(AR71XX_MISC_IRQ_TIMER); else if (pending & MISC_INT_OHCI) do_IRQ(AR71XX_MISC_IRQ_OHCI); else if (pending & MISC_INT_ERROR) do_IRQ(AR71XX_MISC_IRQ_ERROR); else if (pending & MISC_INT_GPIO) ar71xx_gpio_irq_dispatch(); else if (pending & MISC_INT_WDOG) do_IRQ(AR71XX_MISC_IRQ_WDOG); else if (pending & MISC_INT_TIMER2) do_IRQ(AR71XX_MISC_IRQ_TIMER2); else if (pending & MISC_INT_TIMER3) do_IRQ(AR71XX_MISC_IRQ_TIMER3); else if (pending & MISC_INT_TIMER4) do_IRQ(AR71XX_MISC_IRQ_TIMER4); else if (pending & MISC_INT_DDR_PERF) do_IRQ(AR71XX_MISC_IRQ_DDR_PERF); else if (pending & MISC_INT_ENET_LINK) do_IRQ(AR71XX_MISC_IRQ_ENET_LINK); else spurious_interrupt(); }
void winch(int sig, struct uml_pt_regs *regs) { do_IRQ(WINCH_IRQ, regs); }
/* * timer_interrupt - gets called when the decrementer overflows, * with interrupts disabled. * We set it up to overflow again in 1/HZ seconds. */ void timer_interrupt(struct pt_regs * regs) { int next_dec; unsigned long cpu = smp_processor_id(); unsigned jiffy_stamp = last_jiffy_stamp(cpu); extern void do_IRQ(struct pt_regs *); if (atomic_read(&ppc_n_lost_interrupts) != 0) do_IRQ(regs); irq_enter(); while ((next_dec = tb_ticks_per_jiffy - tb_delta(&jiffy_stamp)) <= 0) { jiffy_stamp += tb_ticks_per_jiffy; profile_tick(CPU_PROFILING, regs); update_process_times(user_mode(regs)); if (smp_processor_id()) continue; /* We are in an interrupt, no need to save/restore flags */ write_seqlock(&xtime_lock); tb_last_stamp = jiffy_stamp; do_timer(1); /* * update the rtc when needed, this should be performed on the * right fraction of a second. Half or full second ? * Full second works on mk48t59 clocks, others need testing. * Note that this update is basically only used through * the adjtimex system calls. Setting the HW clock in * any other way is a /dev/rtc and userland business. * This is still wrong by -0.5/+1.5 jiffies because of the * timer interrupt resolution and possible delay, but here we * hit a quantization limit which can only be solved by higher * resolution timers and decoupling time management from timer * interrupts. This is also wrong on the clocks * which require being written at the half second boundary. * We should have an rtc call that only sets the minutes and * seconds like on Intel to avoid problems with non UTC clocks. */ if ( ppc_md.set_rtc_time && ntp_synced() && xtime.tv_sec - last_rtc_update >= 659 && abs((xtime.tv_nsec / 1000) - (1000000-1000000/HZ)) < 500000/HZ) { if (ppc_md.set_rtc_time(xtime.tv_sec+1 + timezone_offset) == 0) last_rtc_update = xtime.tv_sec+1; else /* Try again one minute later */ last_rtc_update += 60; } write_sequnlock(&xtime_lock); } if ( !disarm_decr[smp_processor_id()] ) set_dec(next_dec); last_jiffy_stamp(cpu) = jiffy_stamp; if (ppc_md.heartbeat && !ppc_md.heartbeat_count--) ppc_md.heartbeat(); irq_exit(); }
void sead_hw1_irqdispatch(struct pt_regs *regs) { do_IRQ(1, regs); }
static void rtlx_dispatch(void) { do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); }
asmlinkage void plat_irq_dispatch(struct pt_regs *regs) { u32 pending; pending = read_c0_status() & read_c0_cause(); /* * jump to the correct interrupt routine * These are arranged in priority order and the timer * comes first! */ #ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */ if (pending & C_IRQ4) /* do the peripherals first, that's the timer */ msp_cic_irq_dispatch(); else if (pending & C_IRQ0) do_IRQ(MSP_INT_MAC0); else if (pending & C_IRQ1) do_IRQ(MSP_INT_MAC1); else if (pending & C_IRQ2) do_IRQ(MSP_INT_USB); else if (pending & C_IRQ3) do_IRQ(MSP_INT_SAR); else if (pending & C_IRQ5) do_IRQ(MSP_INT_SEC); #else if (pending & C_IRQ5) do_IRQ(MSP_INT_TIMER); else if (pending & C_IRQ0) do_IRQ(MSP_INT_MAC0); else if (pending & C_IRQ1) do_IRQ(MSP_INT_MAC1); else if (pending & C_IRQ3) do_IRQ(MSP_INT_VE); else if (pending & C_IRQ4) msp_slp_irq_dispatch(); #endif else if (pending & C_SW0) /* do software after hardware */ do_IRQ(MSP_INT_SW0); else if (pending & C_SW1) do_IRQ(MSP_INT_SW1); }
static void ltq_sw1_irqdispatch(void) { do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); }
static void ar913x_ip2_handler(void) { ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC); do_IRQ(AR71XX_CPU_IRQ_IP2); }
void winch(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs) { do_IRQ(WINCH_IRQ, regs); }
static void ar934x_ip2_handler(void) { ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE); do_IRQ(AR71XX_CPU_IRQ_IP2); }
static void mips_perf_dispatch(void) { do_IRQ(mips_cpu_perf_irq); }
static void ar933x_ip3_handler(void) { ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB); do_IRQ(AR71XX_CPU_IRQ_USB); }
/* * timer_interrupt - gets called when the decrementer overflows, * with interrupts disabled. * We set it up to overflow again in 1/HZ seconds. */ int timer_interrupt(struct pt_regs * regs) { int next_dec; unsigned long cpu = smp_processor_id(); unsigned jiffy_stamp = last_jiffy_stamp(cpu); extern void do_IRQ(struct pt_regs *); if (atomic_read(&ppc_n_lost_interrupts) != 0) do_IRQ(regs); hardirq_enter(cpu); while ((next_dec = tb_ticks_per_jiffy - tb_delta(&jiffy_stamp)) < 0) { jiffy_stamp += tb_ticks_per_jiffy; if (!user_mode(regs)) ppc_do_profile(instruction_pointer(regs)); if (unlikely(!heartbeat_count(cpu)--) && heartbeat_reset(cpu)) { ppc_md.heartbeat(); heartbeat_count(cpu) = heartbeat_reset(cpu); } if (cpu) continue; /* We are in an interrupt, no need to save/restore flags */ write_lock(&xtime_lock); tb_last_stamp = jiffy_stamp; do_timer(regs); /* * update the rtc when needed, this should be performed on the * right fraction of a second. Half or full second ? * Full second works on mk48t59 clocks, others need testing. * Note that this update is basically only used through * the adjtimex system calls. Setting the HW clock in * any other way is a /dev/rtc and userland business. * This is still wrong by -0.5/+1.5 jiffies because of the * timer interrupt resolution and possible delay, but here we * hit a quantization limit which can only be solved by higher * resolution timers and decoupling time management from timer * interrupts. This is also wrong on the clocks * which require being written at the half second boundary. * We should have an rtc call that only sets the minutes and * seconds like on Intel to avoid problems with non UTC clocks. */ if ( ppc_md.set_rtc_time && (time_status & STA_UNSYNC) == 0 && xtime.tv_sec - last_rtc_update >= 659 && abs(xtime.tv_usec - (1000000-1000000/HZ)) < 500000/HZ && jiffies - wall_jiffies == 1) { if (ppc_md.set_rtc_time(xtime.tv_sec+1 + time_offset) == 0) last_rtc_update = xtime.tv_sec+1; else /* Try again one minute later */ last_rtc_update += 60; } write_unlock(&xtime_lock); } if (!disarm_decr[cpu]) set_dec(next_dec); last_jiffy_stamp(cpu) = jiffy_stamp; #ifdef CONFIG_SMP smp_local_timer_interrupt(regs); #endif /* CONFIG_SMP */ hardirq_exit(cpu); if (softirq_pending(cpu)) do_softirq(); return 1; /* lets ret_from_int know we can do checks */ }
static void ar934x_ip3_handler(void) { do_IRQ(AR71XX_CPU_IRQ_USB); }
static void ipi_call_dispatch(void) { do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); }
asmlinkage void plat_irq_dispatch(void) { const u32 interrupts = read_c0_cause() >> 8, mask = ((read_c0_status() >> 8) & 0x000000ff) | (read_c0_intcontrol() & 0x0000ff00), pending = interrupts & mask; u32 msgintflags, msgintmask, msgint; /* process timer interrupt */ if (pending & (1 << TIMER_IRQ)) { do_IRQ(TIMER_IRQ); return; } /* Process PCI interrupts */ #if USB_IRQ < 10 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10)); msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10)); msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20)); if ((pending & (1 << USB_IRQ)) && msgint) { #else if (pending & (1 << USB_IRQ)) { #endif do_IRQ(USB_IRQ); return; } /* Process TITAN interrupts */ msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10)); msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10)); msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20)); if ((pending & (1 << TITAN_IRQ)) && msgint) { ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); #if defined(CONFIG_KGDB) excite_kgdb_inthdl(); #endif do_IRQ(TITAN_IRQ); return; } /* Process FPGA line #0 interrupts */ msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10)); msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10)); msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20)); if ((pending & (1 << FPGA0_IRQ)) && msgint) { do_IRQ(FPGA0_IRQ); return; } /* Process FPGA line #1 interrupts */ msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10)); msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10)); msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20)); if ((pending & (1 << FPGA1_IRQ)) && msgint) { do_IRQ(FPGA1_IRQ); return; } /* Process PHY interrupts */ msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10)); msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10)); msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20)); if ((pending & (1 << PHY_IRQ)) && msgint) { do_IRQ(PHY_IRQ); return; } /* Process spurious interrupts */ spurious_interrupt(); }
void brcm_mips_int2_dispatch(struct pt_regs *regs) { unsigned int pendingIrqs,pendingIrqs1, shift,irq; brcm_mips_int2_disable(0); pendingIrqs = CPUINT1C->IntrW0Status; gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus); pendingIrqs1 = CPUINT1C->IntrW1Status; gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus); for (irq=1; irq<=32; irq++) { shift = irq-1; if ((0x1 << shift) & pendingIrqs) { if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT) { do_IRQ(BCM_LINUX_UARTA_IRQ, regs); } else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT) { if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK) && (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) ) { do_IRQ(BCM_LINUX_UARTB_IRQ, regs); } if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK) && (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) ) { do_IRQ(BCM_LINUX_UARTC_IRQ, regs); } if ( (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_udirq_MASK) && (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ud_irqen_MASK) ) { do_IRQ(BCM_LINUX_UARTD_IRQ, regs); } } else if (irq == BCM_LINUX_CPU_ENET_IRQ) { //if (*((volatile unsigned long *)0xb0082418) & 0x2 ) if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 ) do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs); else printk("unsolicited ENET interrupt!!!\n"); } else do_IRQ(irq, regs); } } for (irq = 32+1; irq <= 32+32; irq++) { shift = irq - 32 -1; if (shift == BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IDE_CPU_INTR_SHIFT) { unsigned long l2status = *((volatile unsigned long*)BCM_PATA_IRQ_CPU_STATUS); if (l2status & BCHP_IDE_L2_CPU_STATUS_IDE_PRI_INT_MASK) { do_IRQ(BCM_LINUX_PATA_IRQ, regs); } } else if ((0x1 << shift) & pendingIrqs1) do_IRQ(irq, regs); } brcm_mips_int2_enable(0); }
static void ltq_hw5_irqdispatch(void) { do_IRQ(MIPS_CPU_TIMER_IRQ); }
/* * the first level int-handler will jump here if it is a emma2rh irq */ void emma2rh_irq_dispatch(void) { u32 intStatus; u32 bitmask; u32 i; intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); #ifdef EMMA2RH_SW_CASCADE if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) { u32 swIntStatus; swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { if (swIntStatus & bitmask) { do_IRQ(EMMA2RH_SW_IRQ_BASE + i); return; } } } /* Skip S/W interrupt */ intStatus &= ~(1UL << EMMA2RH_SW_CASCADE); #endif for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { if (intStatus & bitmask) { do_IRQ(EMMA2RH_IRQ_BASE + i); return; } } intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); #ifdef EMMA2RH_GPIO_CASCADE if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) { u32 gpioIntStatus; gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { if (gpioIntStatus & bitmask) { do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i); return; } } } /* Skip GPIO interrupt */ intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32)); #endif for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { if (intStatus & bitmask) { do_IRQ(EMMA2RH_IRQ_BASE + i); return; } } intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2); for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { if (intStatus & bitmask) { do_IRQ(EMMA2RH_IRQ_BASE + i); return; } } }
static void ltq_sw0_irqdispatch(void) { do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); }
static void intc_irq_dispatch(void) { #ifdef IRQ_TIME_MONITOR_DEBUG unsigned long long time_num[2]; unsigned long long time_sub; unsigned int irq_con; #endif unsigned long ipr[2],gpr[2]; unsigned long ipr_intc; #ifdef CONFIG_SMP unsigned long cpuid = smp_processor_id(); unsigned long nextcpu; #endif ipr_intc = readl(intc_base + IPR_OFF); #ifdef CONFIG_SMP ipr[0] = ipr_intc & cpu_irq_unmask[cpuid]; #else ipr[0] = ipr_intc; #endif gpr[0] = ipr[0] & 0x3f000; ipr[0] &= ~0x3f000; ipr[1] = readl(intc_base + PART_OFF + IPR_OFF); gpr[1] = ipr[1] & 0x9f0f0004; ipr[1] &= ~0x9f0f0004; #ifdef IRQ_TIME_MONITOR_DEBUG time_num[0] = sched_clock(); if(gpr[1] & 0x1f000000) { generic_handle_irq(ffs(gpr[1]) +31 +IRQ_INTC_BASE); irq_con = ffs(gpr[1]) +31 +IRQ_INTC_BASE; }else { if (ipr[0]) { generic_handle_irq(ffs(ipr[0]) -1 +IRQ_INTC_BASE); irq_con = ffs(ipr[0]) -1 +IRQ_INTC_BASE; } if (gpr[0]) { generic_handle_irq(ffs(gpr[0]) -1 +IRQ_INTC_BASE); irq_con = ffs(gpr[0]) -1 +IRQ_INTC_BASE; } if (ipr[1]) { generic_handle_irq(ffs(ipr[1]) +31 +IRQ_INTC_BASE); irq_con = ffs(ipr[1]) +31 +IRQ_INTC_BASE; } if (gpr[1]) { generic_handle_irq(ffs(gpr[1]) +31 +IRQ_INTC_BASE); irq_con = ffs(gpr[1]) +31 +IRQ_INTC_BASE; } } time_num[1] = sched_clock(); time_sub = time_num[1] - time_num[0]; if (echo_success && (time_sub > time_monitor[499])) time_over[irq_con] += 1; if (time_sub > time_monitor[irq_con]) time_monitor[irq_con] = time_sub; #else if (ipr[0]) { do_IRQ(ffs(ipr[0]) -1 +IRQ_INTC_BASE); } if (gpr[0]) { generic_handle_irq(ffs(gpr[0]) -1 +IRQ_INTC_BASE); } if (ipr[1]) { do_IRQ(ffs(ipr[1]) +31 +IRQ_INTC_BASE); } if (gpr[1]) { generic_handle_irq(ffs(gpr[1]) +31 +IRQ_INTC_BASE); } #endif #ifdef CONFIG_SMP nextcpu = switch_cpu_irq(cpuid); if(nextcpu & 0x80000000) { nextcpu &= ~0x80000000; ipr_intc = ipr_intc & cpu_irq_affinity[nextcpu]; if(ipr_intc) { cpu_mask_affinity[nextcpu] |= ipr_intc; writel(ipr_intc, intc_base + IMSR_OFF); } }else if(nextcpu) { if(cpu_mask_affinity[nextcpu]) { writel(cpu_mask_affinity[nextcpu], intc_base + IMCR_OFF); cpu_mask_affinity[nextcpu] = 0; } } #endif }
asmlinkage void rt_irq_dispatch(void) { unsigned long mips_cp0_status, mips_cp0_cause, irq_x, irq, i; static unsigned char pci_order = 0; #if defined(CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \ defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855) || \ defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628) unsigned long pci_status=0; #endif mips_cp0_cause = read_32bit_cp0_register(CP0_CAUSE); mips_cp0_status = read_32bit_cp0_register(CP0_STATUS); irq_x = mips_cp0_cause & mips_cp0_status & 0xfc00; irq_x >>= 10; //start from HW_INT#0 /* from low to high priority */ /* irq = 0; for (i = 0; i< 6; i++) { if(irq_x & 0x1) { if(irq != 0) do_IRQ(irq, regs); else surfboard_hw0_irqdispatch(regs); } irq++; irq_x >>= 1; } */ /* from high to low priority */ irq = 4; pci_order^=1; for (i = 0; i< 5; i++) { if(irq_x & 0x10) { clear_c0_status(0x7c00); if(irq > 2) do_IRQ(irq); else if(irq == 2) { #if defined (CONFIG_RALINK_RT2883) do_IRQ(2); #elif defined (CONFIG_RALINK_RT3883) pci_status = RALINK_PCI_PCIINT_ADDR; if(pci_status &0x100000) { do_IRQ(16); } else if(pci_status &0x40000) { do_IRQ(2); } else if(pci_status &0x80000) { do_IRQ(15); } else { } #elif defined (CONFIG_RALINK_RT3052) #elif defined (CONFIG_RALINK_RT3352) #elif defined (CONFIG_RALINK_RT5350) #elif defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628) pci_status = RALINK_PCI_PCIINT_ADDR; if(pci_status &(1<<20)) { do_IRQ(RALINK_INT_PCIE0); } #elif defined (CONFIG_RALINK_RT6855) pci_status = RALINK_PCI_PCIINT_ADDR; if(pci_order==0) { if(pci_status &(1<<20)) { //PCIe0 do_IRQ(RALINK_INT_PCIE0); } else if(pci_status &(1<<21)) { //PCIe1 do_IRQ(RALINK_INT_PCIE1); } else { //printk("pcie inst = %x\n", (unsigned int)pci_status); } } else { if(pci_status &(1<<21)) { //PCIe1 do_IRQ(RALINK_INT_PCIE1); } else if(pci_status &(1<<20)) { //PCIe0 do_IRQ(RALINK_INT_PCIE0); } else { //printk("pcie inst = %x\n", (unsigned int)pci_status); } } #else // 2880 #if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT3883) pci_status = RALINK_PCI_PCIINT_ADDR; #endif if(pci_order ==0) { #if defined(CONFIG_RT2880_ASIC) if(pci_status &0x40000) #elif defined(CONFIG_RT2880_FPGA) if(pci_status &0x80000) #endif do_IRQ(2); else // if(pci_status & 0x40000) do_IRQ(15); } else { #if defined(CONFIG_RT2880_ASIC) if(pci_status &0x80000) #elif defined(CONFIG_RT2880_FPGA) if(pci_status &0x40000) #endif do_IRQ(15); else // if(pci_status & 0x80000) do_IRQ(2); } #endif //CONFIG_RALINK_RT2883// } else { surfboard_hw0_irqdispatch(); } set_c0_status(0x7c00); } irq--; irq_x <<= 1; } return; }