int emu10k1_mpuin_start(struct emu10k1_card *card)
{
struct emu10k1_mpuin *card_mpuin = card->mpuin;
u8 dummy;
DPF(2, "emu10k1_mpuin_start()\n");
/* Set timestamp if not set */
if (card_mpuin->status & FLAGS_MIDM_STARTED) {
DPF(2, "Time Stamp not changed\n");
} else {
while (!emu10k1_mpu_read_data(card, &dummy));
card_mpuin->status |= FLAGS_MIDM_STARTED; /* set */
/* Set new time stamp */
card_mpuin->timestart = (jiffies * 1000) / HZ;
DPD(2, "New Time Stamp = %d\n", card_mpuin->timestart);
card_mpuin->qhead = 0;
card_mpuin->qtail = 0;
emu10k1_irq_enable(card, card->is_audigy ? A_INTE_MIDIRXENABLE : INTE_MIDIRXENABLE);
}
return 0;
}
VOID
ActivateCAMDXmit( struct Hook* hook,
struct EMU10kxBase* EMU10kxBase,
struct ActivateMessage* msg )
{
struct DriverBase* AHIsubBase = (struct DriverBase*) EMU10kxBase;
struct EMU10kxData* dd = EMU10kxBase->driverdatas[ msg->PortNum ];
ULONG b;
// KPrintF( "ActivateCAMDXmit(%08lx)\n", msg->PortNum );
emu10k1_irq_enable( &dd->card, INTE_MIDITXENABLE );
// The interrupt handler will now fetch the bytes and transmit them.
}
ULONG
OpenCAMDPort( struct Hook* hook,
struct EMU10kxBase* EMU10kxBase,
struct OpenMessage* msg )
{
struct DriverBase* AHIsubBase = (struct DriverBase*) EMU10kxBase;
struct EMU10kxData* dd;
BOOL in_use;
// KPrintF( "OpenCAMDPort(%ld,%ld)\n", msg->PortNum, msg->V40Mode );
if( msg->PortNum >= EMU10kxBase->cards_found ||
EMU10kxBase->driverdatas[ msg->PortNum ] == NULL )
{
Req( "No valid EMU10kxData for CAMD port %ld.", msg->PortNum );
return FALSE;
}
dd = EMU10kxBase->driverdatas[ msg->PortNum ];
ObtainSemaphore( &EMU10kxBase->semaphore );
in_use = ( dd->camd_transmitfunc != NULL ||
dd->camd_receivefunc != NULL );
if( !in_use )
{
dd->camd_v40 = msg->V40Mode;
dd->camd_transmitfunc = msg->TransmitFunc;
dd->camd_receivefunc = msg->ReceiveFunc;
}
ReleaseSemaphore( &EMU10kxBase->semaphore );
if( in_use )
{
return FALSE;
}
emu10k1_irq_disable( &dd->card, INTE_MIDIRXENABLE );
emu10k1_irq_disable( &dd->card, INTE_MIDITXENABLE );
emu10k1_mpu_reset( &dd->card );
emu10k1_irq_enable( &dd->card, INTE_MIDIRXENABLE );
return TRUE;
}
static int hw_init(struct emu10k1_card *card)
{
int nCh;
u32 pagecount; /* tmp */
int ret;
/* Disable audio and lock cache */
emu10k1_writefn0(card, HCFG, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE);
/* Reset recording buffers */
sblive_writeptr_tag(card, 0,
MICBS, ADCBS_BUFSIZE_NONE,
MICBA, 0,
FXBS, ADCBS_BUFSIZE_NONE,
FXBA, 0,
ADCBS, ADCBS_BUFSIZE_NONE,
ADCBA, 0,
TAGLIST_END);
/* Disable channel interrupt */
emu10k1_writefn0(card, INTE, 0);
sblive_writeptr_tag(card, 0,
CLIEL, 0,
CLIEH, 0,
SOLEL, 0,
SOLEH, 0,
TAGLIST_END);
/* Init envelope engine */
for (nCh = 0; nCh < NUM_G; nCh++) {
sblive_writeptr_tag(card, nCh,
DCYSUSV, 0,
IP, 0,
VTFT, 0xffff,
CVCF, 0xffff,
PTRX, 0,
//CPF, 0,
CCR, 0,
PSST, 0,
DSL, 0x10,
CCCA, 0,
Z1, 0,
Z2, 0,
FXRT, 0xd01c0000,
ATKHLDM, 0,
DCYSUSM, 0,
IFATN, 0xffff,
PEFE, 0,
FMMOD, 0,
TREMFRQ, 24, /* 1 Hz */
FM2FRQ2, 24, /* 1 Hz */
TEMPENV, 0,
/*** These are last so OFF prevents writing ***/
LFOVAL2, 0,
LFOVAL1, 0,
ATKHLDV, 0,
ENVVOL, 0,
ENVVAL, 0,
TAGLIST_END);
sblive_writeptr(card, CPF, nCh, 0);
}
/*
** Init to 0x02109204 :
** Clock accuracy = 0 (1000ppm)
** Sample Rate = 2 (48kHz)
** Audio Channel = 1 (Left of 2)
** Source Number = 0 (Unspecified)
** Generation Status = 1 (Original for Cat Code 12)
** Cat Code = 12 (Digital Signal Mixer)
** Mode = 0 (Mode 0)
** Emphasis = 0 (None)
** CP = 1 (Copyright unasserted)
** AN = 0 (Digital audio)
** P = 0 (Consumer)
*/
sblive_writeptr_tag(card, 0,
/* SPDIF0 */
SPCS0, (SPCS_CLKACCY_1000PPM | 0x002000000 |
SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | SPCS_GENERATIONSTATUS | 0x00001200 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT),
/* SPDIF1 */
SPCS1, (SPCS_CLKACCY_1000PPM | 0x002000000 |
SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | SPCS_GENERATIONSTATUS | 0x00001200 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT),
/* SPDIF2 & SPDIF3 */
SPCS2, (SPCS_CLKACCY_1000PPM | 0x002000000 |
SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC | SPCS_GENERATIONSTATUS | 0x00001200 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT),
TAGLIST_END);
ret = fx_init(card); /* initialize effects engine */
if (ret < 0)
return ret;
card->tankmem.size = 0;
card->virtualpagetable.size = MAXPAGES * sizeof(u32);
card->virtualpagetable.addr = pci_alloc_consistent(card->pci_dev, card->virtualpagetable.size, &card->virtualpagetable.dma_handle);
if (card->virtualpagetable.addr == NULL) {
ERROR();
ret = -ENOMEM;
goto err0;
}
card->silentpage.size = EMUPAGESIZE;
card->silentpage.addr = pci_alloc_consistent(card->pci_dev, card->silentpage.size, &card->silentpage.dma_handle);
if (card->silentpage.addr == NULL) {
ERROR();
ret = -ENOMEM;
goto err1;
}
for (pagecount = 0; pagecount < MAXPAGES; pagecount++)
((u32 *) card->virtualpagetable.addr)[pagecount] = cpu_to_le32((card->silentpage.dma_handle * 2) | pagecount);
/* Init page table & tank memory base register */
sblive_writeptr_tag(card, 0,
PTB, card->virtualpagetable.dma_handle,
TCB, 0,
TCBS, 0,
TAGLIST_END);
for (nCh = 0; nCh < NUM_G; nCh++) {
sblive_writeptr_tag(card, nCh,
MAPA, MAP_PTI_MASK | (card->silentpage.dma_handle * 2),
MAPB, MAP_PTI_MASK | (card->silentpage.dma_handle * 2),
TAGLIST_END);
}
/* Hokay, now enable the AUD bit */
/* Enable Audio = 1 */
/* Mute Disable Audio = 0 */
/* Lock Tank Memory = 1 */
/* Lock Sound Memory = 0 */
/* Auto Mute = 1 */
if (card->model == 0x20 || card->model == 0xc400 ||
(card->model == 0x21 && card->chiprev < 6))
emu10k1_writefn0(card, HCFG, HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE);
else
emu10k1_writefn0(card, HCFG, HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE);
/* Enable Vol_Ctrl irqs */
emu10k1_irq_enable(card, INTE_VOLINCRENABLE | INTE_VOLDECRENABLE | INTE_MUTEENABLE | INTE_FXDSPENABLE);
/* FIXME: TOSLink detection */
card->has_toslink = 0;
#ifdef lcs
/* Initialize digital passthrough variables */
card->pt.pos_gpr = card->pt.intr_gpr = card->pt.enable_gpr = -1;
card->pt.selected = 0;
card->pt.state = PT_STATE_INACTIVE;
card->pt.spcs_to_use = 0x01;
card->pt.patch_name = "AC3pass";
card->pt.intr_gpr_name = "count";
card->pt.enable_gpr_name = "enable";
card->pt.pos_gpr_name = "ptr";
spin_lock_init(&card->pt.lock);
init_waitqueue_head(&card->pt.wait);
#endif
/* tmp = sblive_readfn0(card, HCFG);
if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
sblive_writefn0(card, HCFG, tmp | 0x800);
udelay(512);
if (tmp != (sblive_readfn0(card, HCFG) & ~0x800)) {
card->has_toslink = 1;
sblive_writefn0(card, HCFG, tmp);
}
}
*/
return 0;
err1:
pci_free_consistent(card->pci_dev, card->virtualpagetable.size, card->virtualpagetable.addr, card->virtualpagetable.dma_handle);
err0:
fx_cleanup(&card->mgr);
return ret;
}