void ft_board_setup(void *blob, bd_t *bd) { u32 val[4]; int rc; ft_cpu_setup(blob, bd); /* Fixup NOR mapping */ val[0] = 0; /* chip select number */ val[1] = 0; /* always 0 */ val[2] = gd->bd->bi_flashstart; val[3] = gd->bd->bi_flashsize; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, sizeof(val), 1); if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); #if defined (CFG_FPGA_BASE) memset(val, 0, sizeof(val)); val[0] = CFG_FPGA_BASE; rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg", val, sizeof(val), 1); if (rc) printf("Unable to update property \"fpga\", err=%s\n", fdt_strerror(rc)); #endif }
void ft_board_setup(void *blob, bd_t *bd) { __ft_board_setup(blob, bd); fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", "disabled", sizeof("disabled"), 1); fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", "disabled", sizeof("disabled"), 1); }
void ft_board_setup(void *blob, bd_t *bd) { u32 val[8]; int rc, i = 0; ft_cpu_setup(blob, bd); #ifdef CONFIG_FDT_FIXUP_PARTITIONS fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); #endif #if defined(CONFIG_VIDEO) fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf); #endif /* Fixup NOR FLASH mapping */ val[i++] = 0; /* chip select number */ val[i++] = 0; /* always 0 */ val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; /* Fixup MRAM mapping */ val[i++] = 2; /* chip select number */ val[i++] = 0; /* always 0 */ val[i++] = CONFIG_SYS_MRAM_BASE; val[i++] = CONFIG_SYS_MRAM_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); if (rc) printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); /* Fixup reg property in NOR Flash node */ i = 0; val[i++] = 0; /* always 0 */ val[i++] = 0; /* start at offset 0 */ val[i++] = flash_info[0].size; /* size of Bank 0 */ /* Second Bank available? */ if (flash_info[1].size > 0) { val[i++] = 0; /* always 0 */ val[i++] = flash_info[0].size; /* offset of Bank 1 */ val[i++] = flash_info[1].size; /* size of Bank 1 */ } rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg", val, i * sizeof(u32), 1); if (rc) printf("Unable to update flash reg property, err=%s\n", fdt_strerror(rc)); }
int ft_board_setup(void *blob, bd_t *bd) { u32 val[12]; int rc, i = 0; ft_cpu_setup(blob, bd); /* Fixup NOR FLASH mapping */ val[i++] = 0; /* chip select number */ val[i++] = 0; /* always 0 */ val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { /* Fixup LIME mapping */ val[i++] = 2; /* chip select number */ val[i++] = 0; /* always 0 */ val[i++] = CONFIG_SYS_LIME_BASE; val[i++] = CONFIG_SYS_LIME_SIZE; } /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ val[i++] = CONFIG_SYS_FPGA_BASE; val[i++] = CONFIG_SYS_FPGA_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); if (rc) printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); return 0; }
void ft_board_setup(void *blob, bd_t *bd) { uint8_t enetaddr[6]; /* MAC addr */ if (eth_getenv_enetaddr("ethaddr", enetaddr)) { fdt_find_and_setprop(blob, "/fec", "local-mac-address", enetaddr, 6, 1); } }
void do_bootvx_fdt(bootm_headers_t *images) { #if defined(CONFIG_OF_LIBFDT) int ret; char *bootline; ulong of_size = images->ft_len; char **of_flat_tree = &images->ft_addr; struct lmb *lmb = &images->lmb; if (*of_flat_tree) { boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree); ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size); if (ret) return; ret = fdt_add_subnode(*of_flat_tree, 0, "chosen"); if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) { bootline = getenv("bootargs"); if (bootline) { ret = fdt_find_and_setprop(*of_flat_tree, "/chosen", "bootargs", bootline, strlen(bootline) + 1, 1); if (ret < 0) { printf("## ERROR: %s : %s\n", __func__, fdt_strerror(ret)); return; } } } else { printf("## ERROR: %s : %s\n", __func__, fdt_strerror(ret)); return; } } #endif boot_prep_vxworks(images); bootstage_mark(BOOTSTAGE_ID_RUN_OS); #if defined(CONFIG_OF_LIBFDT) printf("## Starting vxWorks at 0x%08lx, device tree at 0x%08lx ...\n", (ulong)images->ep, (ulong)*of_flat_tree); #else printf("## Starting vxWorks at 0x%08lx\n", (ulong)images->ep); #endif boot_jump_vxworks(images); puts("## vxWorks terminated\n"); }
int ft_board_setup(void *blob, bd_t *bd) { u32 baseboard_rev; int nodeoffset; uint8_t enetaddr[6]; char baseboard_name[16]; int err; fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */ /* MAC addr */ if (eth_env_get_enetaddr("ethaddr", enetaddr)) { fdt_find_and_setprop(blob, "/soc/aips-bus@02100000/ethernet@02188000", "local-mac-address", enetaddr, 6, 1); } if (eth_env_get_enetaddr("eth1addr", enetaddr)) { fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", enetaddr, 6, 1); } fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); baseboard_rev = cl_eeprom_get_board_rev(0); err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0); if (err || baseboard_rev == 0) return 0; /* Assume not an early revision SB-FX6m baseboard */ if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) { nodeoffset = fdt_path_offset(blob, USDHC3_PATH); fdt_delprop(blob, nodeoffset, "cd-gpios"); fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd", NULL, 0, 1); fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend", NULL, 0, 1); } return 0; }
void do_fixup_by_path(void *fdt, const char *path, const char *prop, const void *val, int len, int create) { #if defined(DEBUG) int i; debug("Updating property '%s/%s' = ", path, prop); for (i = 0; i < len; i++) debug(" %.2x", *(u8*)(val+i)); debug("\n"); #endif int rc = fdt_find_and_setprop(fdt, path, prop, val, len, create); if (rc) printf("Unable to update property %s:%s, err=%s\n", path, prop, fdt_strerror(rc)); }
int __ft_board_setup(void *blob, bd_t *bd) { int rc; int i; u32 bxcr; u32 ranges[EBC_NUM_BANKS * 4]; u32 *p = ranges; char ebc_path[] = "/plb/opb/ebc"; ft_cpu_setup(blob, bd); /* * Read 4xx EBC bus bridge registers to get mappings of the * peripheral banks into the OPB/PLB address space */ for (i = 0; i < EBC_NUM_BANKS; i++) { mtdcr(EBC0_CFGADDR, EBC_BXCR(i)); bxcr = mfdcr(EBC0_CFGDATA); if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) { *p++ = i; *p++ = 0; *p++ = bxcr & EBC_BXCR_BAS_MASK; *p++ = EBC_BXCR_BANK_SIZE(bxcr); } } #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE /* Update reg property in all nor flash nodes too */ fdt_fixup_nor_flash_size(blob); #endif /* Some 405 PPC's have EBC as direct PLB child in the dts */ if (fdt_path_offset(blob, ebc_path) < 0) strcpy(ebc_path, "/plb/ebc"); rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges, (p - ranges) * sizeof(u32), 1); if (rc) { printf("Unable to update property EBC mappings, err=%s\n", fdt_strerror(rc)); } return 0; }
void ft_board_setup(void *blob, bd_t *bd) { u32 val[4]; int rc; ft_cpu_setup(blob, bd); /* Fixup NOR mapping */ val[0] = 1; /* chip select number */ val[1] = 0; /* always 0 */ val[2] = gd->bd->bi_flashstart; val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", val, sizeof(val), 1); if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); }
void ft_board_setup(void *blob, bd_t *bd) { int rc; __ft_board_setup(blob, bd); /* * Disable PCI in non-monarch mode. */ if (!is_monarch()) { rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", "disabled", sizeof("disabled"), 1); if (rc) { printf("Unable to update property status in PCI node, " "err=%s\n", fdt_strerror(rc)); } } }