/** * c67x00_ll_write_mem_le16 - write into c67x00 memory * Only data is little endian, addr has cpu endianess. */ void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr, void *data, int len) { u8 *buf = data; /* Sanity check */ if (addr + len > 0xffff) { dev_err(&dev->pdev->dev, "Trying to write beyond writable region!\n"); return; } if (addr & 0x01) { /* unaligned access */ u16 tmp; tmp = hpi_read_word(dev, addr - 1); tmp = (tmp & 0x00ff) | (*buf++ << 8); hpi_write_word(dev, addr - 1, tmp); addr++; len--; } hpi_write_words_le16(dev, addr, (__le16 *)buf, len / 2); buf += len & ~0x01; addr += len & ~0x01; len &= 0x01; if (len) { u16 tmp; tmp = hpi_read_word(dev, addr); tmp = (tmp & 0xff00) | *buf; hpi_write_word(dev, addr, tmp); } }
void c67x00_ll_hpi_reg_init(struct c67x00_device *dev) { int i; hpi_recv_mbox(dev); c67x00_ll_hpi_status(dev); hpi_write_word(dev, HPI_IRQ_ROUTING_REG, 0); for (i = 0; i < C67X00_SIES; i++) { hpi_write_word(dev, SIEMSG_REG(i), 0); hpi_read_word(dev, SIEMSG_REG(i)); } }
static int c67x00_comm_exec_int(struct c67x00_device *dev, u16 nr, struct c67x00_lcp_int_data *data) { int i, rc; mutex_lock(&dev->hpi.lcp.mutex); hpi_write_word(dev, COMM_INT_NUM, nr); for (i = 0; i < COMM_REGS; i++) hpi_write_word(dev, COMM_R(i), data->regs[i]); hpi_send_mbox(dev, COMM_EXEC_INT); rc = ll_recv_msg(dev); mutex_unlock(&dev->hpi.lcp.mutex); return rc; }
u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num) { u16 val; val = hpi_read_word(dev, SIEMSG_REG(sie_num)); /* clear register to allow next message */ hpi_write_word(dev, SIEMSG_REG(sie_num), 0); return val; }
u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num) { u16 val; val = hpi_read_word(dev, SIEMSG_REG(sie_num)); hpi_write_word(dev, SIEMSG_REG(sie_num), 0); return val; }
static short hpi6000_send_host_command(struct hpi_adapter_obj *pao, u16 dsp_index, u32 host_cmd) { struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout = TIMEOUT; /* set command */ do { hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd); /* flush the FIFO */ hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); /* reset the interrupt bit */ iowrite32(0x00040004, pdo->prHPI_control); if (timeout) return 0; else return 1; }
void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr) { hpi_write_word(sie->dev, HUSB_SIE_pCurrentTDPtr(sie->sie_num), addr); }
void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value) { mutex_lock(&dev->hpi.lcp.mutex); hpi_write_word(dev, HUSB_pEOT, value); mutex_unlock(&dev->hpi.lcp.mutex); }
/** * c67x00_ll_usb_clear_status - clear the USB status bits */ void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits) { hpi_write_word(sie->dev, USB_STAT_REG(sie->sie_num), bits); }
static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao, u32 *pos_error_code) { struct hpi_hw_obj *phw = pao->priv; short error; u32 timeout; u32 read = 0; u32 i = 0; u32 data = 0; u32 j = 0; u32 test_addr = 0x80000000; u32 test_data = 0x00000001; u32 dw2040_reset = 0; u32 dsp_index = 0; u32 endian = 0; u32 adapter_info = 0; u32 delay = 0; struct dsp_code dsp_code; u16 boot_load_family = 0; /* NOTE don't use wAdapterType in this routine. It is not setup yet */ switch (pao->pci.pci_dev->subsystem_device) { case 0x5100: case 0x5110: /* ASI5100 revB or higher with C6711D */ case 0x5200: /* ASI5200 PCIe version of ASI5100 */ case 0x6100: case 0x6200: boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200); break; default: return HPI6000_ERROR_UNHANDLED_SUBSYS_ID; } /* reset all DSPs, indicate two DSPs are present * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode */ endian = 0; dw2040_reset = 0x0003000F; iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /* read back register to make sure PCI2040 chip is functioning * note that bits 4..15 are read-only and so should always return zero, * even though we wrote 1 to them */ hpios_delay_micro_seconds(1000); delay = ioread32(phw->dw2040_HPICSR + HPI_RESET); if (delay != dw2040_reset) { HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset, delay); return HPI6000_ERROR_INIT_PCI2040; } /* Indicate that DSP#0,1 is a C6X */ iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH); /* set Bit30 and 29 - which will prevent Target aborts from being * issued upon HPI or GP error */ iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET); /* isolate DSP HAD8 line from PCI2040 so that * Little endian can be set by pullup */ dw2040_reset = dw2040_reset & (~(endian << 3)); iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); phw->ado[0].c_dsp_rev = 'B'; /* revB */ phw->ado[1].c_dsp_rev = 'B'; /* revB */ /*Take both DSPs out of reset, setting HAD8 to the correct Endian */ dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */ iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */ iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /* set HAD8 back to PCI2040, now that DSP set to little endian mode */ dw2040_reset = dw2040_reset & (~0x00000008); iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET); /*delay to allow DSP to get going */ hpios_delay_micro_seconds(100); /* loop through all DSPs, downloading DSP code */ for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) { struct dsp_obj *pdo = &phw->ado[dsp_index]; /* configure DSP so that we download code into the SRAM */ /* set control reg for little endian, HWOB=1 */ iowrite32(0x00010001, pdo->prHPI_control); /* test access to the HPI address register (HPIA) */ test_data = 0x00000001; for (j = 0; j < 32; j++) { iowrite32(test_data, pdo->prHPI_address); data = ioread32(pdo->prHPI_address); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n", test_data, data, dsp_index); return HPI6000_ERROR_INIT_DSPHPI; } test_data = test_data << 1; } /* if C6713 the setup PLL to generate 225MHz from 25MHz. * Since the PLLDIV1 read is sometimes wrong, even on a C6713, * we're going to do this unconditionally */ /* PLLDIV1 should have a value of 8000 after reset */ /* if (HpiReadWord(pdo,0x01B7C118) == 0x8000) */ { /* C6713 datasheet says we cannot program PLL from HPI, * and indeed if we try to set the PLL multiply from the * HPI, the PLL does not seem to lock, * so we enable the PLL and use the default of x 7 */ /* bypass PLL */ hpi_write_word(pdo, 0x01B7C100, 0x0000); hpios_delay_micro_seconds(100); /* ** use default of PLL x7 ** */ /* EMIF = 225/3=75MHz */ hpi_write_word(pdo, 0x01B7C120, 0x8002); hpios_delay_micro_seconds(100); /* peri = 225/2 */ hpi_write_word(pdo, 0x01B7C11C, 0x8001); hpios_delay_micro_seconds(100); /* cpu = 225/1 */ hpi_write_word(pdo, 0x01B7C118, 0x8000); /* ~2ms delay */ hpios_delay_micro_seconds(2000); /* PLL not bypassed */ hpi_write_word(pdo, 0x01B7C100, 0x0001); /* ~2ms delay */ hpios_delay_micro_seconds(2000); } /* test r/w to internal DSP memory * C6711 has L2 cache mapped to 0x0 when reset * * revB - because of bug 3.0.1 last HPI read * (before HPI address issued) must be non-autoinc */ /* test each bit in the 32bit word */ for (i = 0; i < 100; i++) { test_addr = 0x00000000; test_data = 0x00000001; for (j = 0; j < 32; j++) { hpi_write_word(pdo, test_addr + i, test_data); data = hpi_read_word(pdo, test_addr + i); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP mem %x %x %x %x\n", test_addr + i, test_data, data, dsp_index); return HPI6000_ERROR_INIT_DSPINTMEM; } test_data = test_data << 1; } } /* memory map of ASI6200 00000000-0000FFFF 16Kx32 internal program 01800000-019FFFFF Internal peripheral 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz 90000000-9000FFFF CE1 Async peripherals: EMIF config ------------ Global EMIF control 0 - 1 - 2 - 3 CLK2EN = 1 CLKOUT2 enabled 4 CLK1EN = 0 CLKOUT1 disabled 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT 6 - 7 NOHOLD = 1 external HOLD disabled 8 HOLDA = 0 HOLDA output is low 9 HOLD = 0 HOLD input is low 10 ARDY = 1 ARDY input is high 11 BUSREQ = 0 BUSREQ output is low 12,13 Reserved = 1 */ hpi_write_word(pdo, 0x01800000, 0x34A8); /* EMIF CE0 setup - 2Mx32 Sync DRAM 31..28 Wr setup 27..22 Wr strobe 21..20 Wr hold 19..16 Rd setup 15..14 - 13..8 Rd strobe 7..4 MTYPE 0011 Sync DRAM 32bits 3 Wr hold MSB 2..0 Rd hold */ hpi_write_word(pdo, 0x01800008, 0x00000030); /* EMIF SDRAM Extension 31-21 0 20 WR2RD = 0 19-18 WR2DEAC = 1 17 WR2WR = 0 16-15 R2WDQM = 2 14-12 RD2WR = 4 11-10 RD2DEAC = 1 9 RD2RD = 1 8-7 THZP = 10b 6-5 TWR = 2-1 = 01b (tWR = 10ns) 4 TRRD = 0b = 2 ECLK (tRRD = 14ns) 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK) 1 CAS latency = 3 ECLK (for Micron 2M32-7 operating at 100Mhz) */ /* need to use this else DSP code crashes */ hpi_write_word(pdo, 0x01800020, 0x001BDF29); /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 31 - - 30 SDBSZ 1 4 bank 29..28 SDRSZ 00 11 row address pins 27..26 SDCSZ 01 8 column address pins 25 RFEN 1 refersh enabled 24 INIT 1 init SDRAM 23..20 TRCD 0001 19..16 TRP 0001 15..12 TRC 0110 11..0 - - */ /* need to use this else DSP code crashes */ hpi_write_word(pdo, 0x01800018, 0x47117000); /* EMIF SDRAM Refresh Timing */ hpi_write_word(pdo, 0x0180001C, 0x00000410); /*MIF CE1 setup - Async peripherals @100MHz bus speed, each cycle is 10ns, 31..28 Wr setup = 1 27..22 Wr strobe = 3 30ns 21..20 Wr hold = 1 19..16 Rd setup =1 15..14 Ta = 2 13..8 Rd strobe = 3 30ns 7..4 MTYPE 0010 Async 32bits 3 Wr hold MSB =0 2..0 Rd hold = 1 */ { u32 cE1 = (1L << 28) | (3L << 22) | (1L << 20) | (1L << 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L; hpi_write_word(pdo, 0x01800004, cE1); } /* delay a little to allow SDRAM and DSP to "get going" */ hpios_delay_micro_seconds(1000); /* test access to SDRAM */ { test_addr = 0x80000000; test_data = 0x00000001; /* test each bit in the 32bit word */ for (j = 0; j < 32; j++) { hpi_write_word(pdo, test_addr, test_data); data = hpi_read_word(pdo, test_addr); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP dram %x %x %x %x\n", test_addr, test_data, data, dsp_index); return HPI6000_ERROR_INIT_SDRAM1; } test_data = test_data << 1; } /* test every Nth address in the DRAM */ #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */ #define DRAM_INC 1024 test_addr = 0x80000000; test_data = 0x0; for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { hpi_write_word(pdo, test_addr + i, test_data); test_data++; } test_addr = 0x80000000; test_data = 0x0; for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) { data = hpi_read_word(pdo, test_addr + i); if (data != test_data) { HPI_DEBUG_LOG(ERROR, "DSP dram %x %x %x %x\n", test_addr + i, test_data, data, dsp_index); return HPI6000_ERROR_INIT_SDRAM2; } test_data++; } } /* write the DSP code down into the DSPs memory */ error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev, &dsp_code, pos_error_code); if (error) return error; while (1) { u32 length; u32 address; u32 type; u32 *pcode; error = hpi_dsp_code_read_word(&dsp_code, &length); if (error) break; if (length == 0xFFFFFFFF) break; /* end of code */ error = hpi_dsp_code_read_word(&dsp_code, &address); if (error) break; error = hpi_dsp_code_read_word(&dsp_code, &type); if (error) break; error = hpi_dsp_code_read_block(length, &dsp_code, &pcode); if (error) break; error = hpi6000_dsp_block_write32(pao, (u16)dsp_index, address, pcode, length); if (error) break; } if (error) { hpi_dsp_code_close(&dsp_code); return error; } /* verify that code was written correctly */ /* this time through, assume no errors in DSP code file/array */ hpi_dsp_code_rewind(&dsp_code); while (1) { u32 length; u32 address; u32 type; u32 *pcode; hpi_dsp_code_read_word(&dsp_code, &length); if (length == 0xFFFFFFFF) break; /* end of code */ hpi_dsp_code_read_word(&dsp_code, &address); hpi_dsp_code_read_word(&dsp_code, &type); hpi_dsp_code_read_block(length, &dsp_code, &pcode); for (i = 0; i < length; i++) { data = hpi_read_word(pdo, address); if (data != *pcode) { error = HPI6000_ERROR_INIT_VERIFY; HPI_DEBUG_LOG(ERROR, "DSP verify %x %x %x %x\n", address, *pcode, data, dsp_index); break; } pcode++; address += 4; } if (error) break; } hpi_dsp_code_close(&dsp_code); if (error) return error; /* zero out the hostmailbox */ { u32 address = HPI_HIF_ADDR(host_cmd); for (i = 0; i < 4; i++) { hpi_write_word(pdo, address, 0); address += 4; } } /* write the DSP number into the hostmailbox */ /* structure before starting the DSP */ hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index); /* write the DSP adapter Info into the */ /* hostmailbox before starting the DSP */ if (dsp_index > 0) hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info), adapter_info); /* step 3. Start code by sending interrupt */ iowrite32(0x00030003, pdo->prHPI_control); hpios_delay_micro_seconds(10000); /* wait for a non-zero value in hostcmd - * indicating initialization is complete * * Init could take a while if DSP checks SDRAM memory * Was 200000. Increased to 2000000 for ASI8801 so we * don't get 938 errors. */ timeout = 2000000; while (timeout) { do { read = hpi_read_word(pdo, HPI_HIF_ADDR(host_cmd)); } while (--timeout && hpi6000_check_PCI2040_error_flag(pao, H6READ)); if (read) break; /* The following is a workaround for bug #94: * Bluescreen on install and subsequent boots on a * DELL PowerEdge 600SC PC with 1.8GHz P4 and * ServerWorks chipset. Without this delay the system * locks up with a bluescreen (NOT GPF or pagefault). */ else hpios_delay_micro_seconds(10000); } if (timeout == 0) return HPI6000_ERROR_INIT_NOACK; /* read the DSP adapter Info from the */ /* hostmailbox structure after starting the DSP */ if (dsp_index == 0) { /*u32 dwTestData=0; */ u32 mask = 0; adapter_info = hpi_read_word(pdo, HPI_HIF_ADDR(adapter_info)); if (HPI_ADAPTER_FAMILY_ASI (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER (adapter_info)) == HPI_ADAPTER_FAMILY_ASI(0x6200)) /* all 6200 cards have this many DSPs */ phw->num_dsp = 2; /* test that the PLD is programmed */ /* and we can read/write 24bits */ #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */ switch (boot_load_family) { case HPI_ADAPTER_FAMILY_ASI(0x6200): /* ASI6100/6200 has 24bit path to FPGA */ mask = 0xFFFFFF00L; /* ASI5100 uses AX6 code, */ /* but has no PLD r/w register to test */ if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> subsystem_device) == HPI_ADAPTER_FAMILY_ASI(0x5100)) mask = 0x00000000L; /* ASI5200 uses AX6 code, */ /* but has no PLD r/w register to test */ if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev-> subsystem_device) == HPI_ADAPTER_FAMILY_ASI(0x5200)) mask = 0x00000000L; break; case HPI_ADAPTER_FAMILY_ASI(0x8800): /* ASI8800 has 16bit path to FPGA */ mask = 0xFFFF0000L; break; } test_data = 0xAAAAAA00L & mask; /* write to 24 bit Debug register (D31-D8) */ hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); read = hpi_read_word(pdo, PLD_BASE_ADDRESS + 4L) & mask; if (read != test_data) { HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, read); return HPI6000_ERROR_INIT_PLDTEST1; } test_data = 0x55555500L & mask; hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data); read = hpi_read_word(pdo, PLD_BASE_ADDRESS + 4L) & mask; if (read != test_data) { HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data, read); return HPI6000_ERROR_INIT_PLDTEST2; } } } /* for numDSP */ return 0; }
static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao, struct hpi_message *phm) { const u16 dsp_index = 0; struct hpi_hw_obj *phw = pao->priv; struct dsp_obj *pdo = &phw->ado[dsp_index]; u32 timeout; u32 cache_dirty_flag; u16 err; hpios_dsplock_lock(pao); timeout = TIMEOUT; do { cache_dirty_flag = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_is_dirty)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_PARAMS; goto unlock; } if (cache_dirty_flag) { /* read the cached controls */ u32 address; u32 length; timeout = TIMEOUT; if (pdo->control_cache_address_on_dsp == 0) { do { address = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_address)); length = hpi_read_word((struct dsp_obj *)pdo, HPI_HIF_ADDR (control_cache_size_in_bytes)); } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN; goto unlock; } pdo->control_cache_address_on_dsp = address; pdo->control_cache_length_on_dsp = length; } else { address = pdo->control_cache_address_on_dsp; length = pdo->control_cache_length_on_dsp; } if (hpi6000_dsp_block_read32(pao, dsp_index, address, (u32 *)&phw->control_cache[0], length / sizeof(u32))) { err = HPI6000_ERROR_CONTROL_CACHE_READ; goto unlock; } do { hpi_write_word((struct dsp_obj *)pdo, HPI_HIF_ADDR(control_cache_is_dirty), 0); /* flush the FIFO */ hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd)); } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout); if (!timeout) { err = HPI6000_ERROR_CONTROL_CACHE_FLUSH; goto unlock; } } err = 0; unlock: hpios_dsplock_unlock(pao); return err; }