static int
mousebtn_detach(device_t self, int flags)
{
struct mousebtn_softc *sc = device_private(self);
if (sc->sc_intr[0] != NULL)
intr_disestablish(sc->sc_intr[0]);
if (sc->sc_intr[1] != NULL)
intr_disestablish(sc->sc_intr[1]);
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
return 0;
}
static int
imx6_ahcisata_detach(device_t self, int flags)
{
struct imx_ahci_softc *sc;
struct ahci_softc *ahci_sc;
int rv;
sc = device_private(self);
ahci_sc = &sc->sc_ahcisc;
rv = ahci_detach(ahci_sc, flags);
if (rv)
return rv;
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
if (ahci_sc->sc_ahcis) {
bus_space_unmap(ahci_sc->sc_ahcit, ahci_sc->sc_ahcih,
ahci_sc->sc_ahcis);
ahci_sc->sc_ahcis = 0;
ahci_sc->sc_ahcit = 0;
ahci_sc->sc_ahcih = 0;
}
return 0;
}
void
pci_msi_disestablish(void *ih)
{
struct msi_hdl *msih = ih;
pci_conf_write(msih->pc, msih->tag, msih->co + PCI_MSI_CTL, 0);
intr_disestablish(msih->ih);
free(msih, M_DEVBUF);
}
/* Deregister an interrupt handler. */
void
isa_intr_disestablish(isa_chipset_tag_t ic, void *arg)
{
struct intrhand *ih = arg;
if (!LEGAL_IRQ(ih->ih_pin))
panic("intr_disestablish: bogus irq");
intr_disestablish(ih);
}
void
isa_intr_disestablish(isa_chipset_tag_t ic, void *handler)
{
isa_intr_info_t *iinfo_p = (isa_intr_info_t *)handler;
if (iinfo_p->slot < 0)
panic("isa_intr_disestablish: interrupt was not established");
(void) intr_disestablish(iinfo_p->ihand);
iinfo_p->slot = -1;
}
void
pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
{
pci_chipset_tag_t ipc;
for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) {
if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0)
continue;
(*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie);
return;
}
intr_disestablish(cookie);
}
static int
n900prxmty_detach(device_t self, int flags)
{
struct n900prxmty_softc *sc = device_private(self);
if (sc->sc_intr != NULL) {
intr_disestablish(sc->sc_intr);
}
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
pmf_device_deregister(self);
sysmon_task_queue_fini();
return 0;
}
void
_nouveau_mc_dtor(struct nouveau_object *object)
{
struct nouveau_device *device = nv_device(object);
struct nouveau_mc *pmc = (void *)object;
#if defined(__NetBSD__)
if (nv_device_is_pci(device)) {
pci_intr_disestablish(device->pdev->pd_pa.pa_pc, pmc->irq_cookie);
#if defined(__arm__)
} else {
intr_disestablish(pmc->irq_cookie);
#endif
}
#else
free_irq(pmc->irq, pmc);
#endif
if (pmc->use_msi)
pci_disable_msi(device->pdev);
nouveau_subdev_destroy(&pmc->base);
}
void
bcm_dmac_free(struct bcm_dmac_channel *ch)
{
struct bcm_dmac_softc *sc = ch->ch_sc;
uint32_t val;
bcm_dmac_halt(ch);
val = DMAC_READ(sc, DMAC_CS(ch->ch_index));
val |= DMAC_CS_RESET;
val |= DMAC_CS_ABORT;
val &= ~DMAC_CS_ACTIVE;
DMAC_WRITE(sc, DMAC_CS(ch->ch_index), val);
mutex_enter(&sc->sc_lock);
intr_disestablish(ch->ch_ih);
ch->ch_ih = NULL;
ch->ch_callback = NULL;
ch->ch_callbackarg = NULL;
mutex_exit(&sc->sc_lock);
}
int
wdc_obio_detach(device_t self, int flags)
{
struct wdc_obio_softc *sc = device_private(self);
int error;
if ((error = wdcdetach(self, flags)) != 0)
return error;
intr_disestablish(sc->sc_ih);
/* Unmap our i/o space. */
bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot,
sc->sc_wdcdev.regs->cmd_baseioh, WDC_REG_NPORTS << 4);
/* Unmap DMA registers. */
bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot, sc->sc_dmaregh, 0x100);
free(sc->sc_dmacmd, M_DEVBUF);
return 0;
}
static void
bcmemmc_attach_i(device_t self)
{
struct bcmemmc_softc * const sc = device_private(self);
int error;
error = sdhc_host_found(&sc->sc, sc->sc_iot, sc->sc_ioh, sc->sc_ios);
if (error != 0) {
aprint_error_dev(self, "couldn't initialize host, error=%d\n",
error);
goto fail;
}
return;
fail:
/* XXX add bus_dma failure cleanup */
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
}
static void
awin_ahci_attach(device_t parent, device_t self, void *aux)
{
struct awin_ahci_softc * const asc = device_private(self);
struct ahci_softc * const sc = &asc->asc_sc;
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
awin_ahci_enable(aio->aio_core_bst, aio->aio_ccm_bsh);
sc->sc_atac.atac_dev = self;
sc->sc_dmat = aio->aio_dmat;
sc->sc_ahcit = aio->aio_core_bst;
sc->sc_ahcis = loc->loc_size;
sc->sc_ahci_ports = 1;
sc->sc_ahci_quirks = AHCI_QUIRK_BADPMP;
sc->sc_save_init_data = true;
sc->sc_channel_start = awin_ahci_channel_start;
bus_space_subregion(aio->aio_core_bst, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_ahcih);
aprint_naive(": AHCI SATA controller\n");
aprint_normal(": AHCI SATA controller\n");
/*
* Bring up the PHY.
*/
awin_ahci_phy_init(asc);
/*
* If there is a GPIO to turn on power, do it now.
*/
const char *pin_name;
prop_dictionary_t dict = device_properties(self);
if (prop_dictionary_get_cstring_nocopy(dict, "power-gpio", &pin_name)) {
if (awin_gpio_pin_reserve(pin_name, &asc->asc_gpio_pin)) {
awin_gpio_pindata_write(&asc->asc_gpio_pin, 1);
} else {
aprint_error_dev(self,
"failed to reserve GPIO \"%s\"\n", pin_name);
}
}
/*
* Establish the interrupt
*/
asc->asc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
ahci_intr, sc);
if (asc->asc_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
loc->loc_intr);
goto fail;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
ahci_attach(sc);
return;
fail:
if (asc->asc_ih) {
intr_disestablish(asc->asc_ih);
asc->asc_ih = NULL;
}
}
void
pci_intr_disestablish(void *v, void *cookie)
{
intr_disestablish(cookie);
}
void
gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
{
intr_disestablish(cookie);
}
static void
obiosdhc_attach(device_t parent, device_t self, void *aux)
{
struct obiosdhc_softc * const sc = device_private(self);
struct obio_attach_args * const oa = aux;
prop_dictionary_t prop = device_properties(self);
uint32_t clkd, stat;
int error, timo, clksft, n;
bool support8bit = false;
const char *transfer_mode = "PIO";
#ifdef TI_AM335X
size_t i;
#endif
prop_dictionary_get_bool(prop, "8bit", &support8bit);
sc->sc.sc_dmat = oa->obio_dmat;
sc->sc.sc_dev = self;
sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
sc->sc.sc_flags |= SDHC_FLAG_NO_LED_ON;
sc->sc.sc_flags |= SDHC_FLAG_RSP136_CRC;
sc->sc.sc_flags |= SDHC_FLAG_SINGLE_ONLY;
if (support8bit)
sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE;
#ifdef TI_AM335X
sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET;
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
#endif
#if defined(OMAP_3530)
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
#endif
sc->sc.sc_host = sc->sc_hosts;
sc->sc.sc_clkbase = 96000; /* 96MHZ */
if (!prop_dictionary_get_uint32(prop, "clkmask", &sc->sc.sc_clkmsk))
sc->sc.sc_clkmsk = 0x0000ffc0;
sc->sc.sc_vendor_rod = obiosdhc_rod;
sc->sc.sc_vendor_write_protect = obiosdhc_write_protect;
sc->sc.sc_vendor_card_detect = obiosdhc_card_detect;
sc->sc.sc_vendor_bus_clock = obiosdhc_bus_clock;
sc->sc_bst = oa->obio_iot;
clksft = ffs(sc->sc.sc_clkmsk) - 1;
error = bus_space_map(sc->sc_bst, oa->obio_addr, oa->obio_size, 0,
&sc->sc_bsh);
if (error) {
aprint_error_dev(self,
"can't map registers: %d\n", error);
return;
}
bus_space_subregion(sc->sc_bst, sc->sc_bsh, OMAP3_SDMMC_SDHC_OFFSET,
OMAP3_SDMMC_SDHC_SIZE, &sc->sc_sdhc_bsh);
#if NEDMA > 0
if (oa->obio_edmabase != -1) {
cv_init(&sc->sc_edma_cv, "sdhcedma");
sc->sc_edma_fifo = oa->obio_addr +
OMAP3_SDMMC_SDHC_OFFSET + SDHC_DATA;
obiosdhc_edma_init(sc, oa->obio_edmabase);
sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTDMA_DMAEN;
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
sc->sc.sc_vendor_transfer_data_dma = obiosdhc_edma_xfer_data;
transfer_mode = "EDMA";
}
#endif
aprint_naive("\n");
aprint_normal(": SDHC controller (%s)\n", transfer_mode);
#ifdef TI_AM335X
/* XXX Not really AM335X-specific. */
for (i = 0; i < __arraycount(am335x_sdhc); i++)
if ((oa->obio_addr == am335x_sdhc[i].as_base_addr) &&
(oa->obio_intr == am335x_sdhc[i].as_intr)) {
prcm_module_enable(&am335x_sdhc[i].as_module);
break;
}
KASSERT(i < __arraycount(am335x_sdhc));
#endif
/* XXXXXX: Turn-on regulator via I2C. */
/* XXXXXX: And enable ICLOCK/FCLOCK. */
/* MMCHS Soft reset */
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
SYSCONFIG_SOFTRESET);
timo = 3000000; /* XXXX 3 sec. */
while (timo--) {
if (bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSSTATUS) &
SYSSTATUS_RESETDONE)
break;
delay(1);
}
if (timo == 0)
aprint_error_dev(self, "Soft reset timeout\n");
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_SYSCONFIG,
SYSCONFIG_ENAWAKEUP | SYSCONFIG_AUTOIDLE | SYSCONFIG_SIDLEMODE_AUTO |
SYSCONFIG_CLOCKACTIVITY_FCLK | SYSCONFIG_CLOCKACTIVITY_ICLK);
sc->sc_ih = intr_establish(oa->obio_intr, IPL_VM, IST_LEVEL,
sdhc_intr, &sc->sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
oa->obio_intr);
goto fail;
}
error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_sdhc_bsh,
oa->obio_size - OMAP3_SDMMC_SDHC_OFFSET);
if (error != 0) {
aprint_error_dev(self, "couldn't initialize host, error=%d\n",
error);
goto fail;
}
/* Set SDVS 1.8v and DTW 1bit mode */
SDHC_WRITE(sc, SDHC_HOST_CTL,
SDHC_VOLTAGE_1_8V << (SDHC_VOLTAGE_SHIFT + 8));
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_OD);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_INTCLK_ENABLE |
SDHC_SDCLK_ENABLE);
SDHC_WRITE(sc, SDHC_HOST_CTL,
SDHC_READ(sc, SDHC_HOST_CTL) | SDHC_BUS_POWER << 8);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
/*
* 22.6.1.3.1.5 MMCHS Controller INIT Procedure Start
* from 'OMAP35x Applications Processor Technical Reference Manual'.
*
* During the INIT procedure, the MMCHS controller generates 80 clock
* periods. In order to keep the 1ms gap, the MMCHS controller should
* be configured to generate a clock whose frequency is smaller or
* equal to 80 KHz.
*/
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
clkd = CLKD(80);
n = 1;
while (clkd & ~(sc->sc.sc_clkmsk >> clksft)) {
clkd >>= 1;
n <<= 1;
}
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | (clkd << clksft));
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) | CON_INIT);
for (; n > 0; n--) {
SDHC_WRITE(sc, SDHC_TRANSFER_MODE, 0x00000000);
timo = 3000000; /* XXXX 3 sec. */
stat = 0;
while (!(stat & SDHC_COMMAND_COMPLETE)) {
stat = SDHC_READ(sc, SDHC_NINTR_STATUS);
if (--timo == 0)
break;
delay(1);
}
if (timo == 0) {
aprint_error_dev(self, "INIT Procedure timeout\n");
break;
}
SDHC_WRITE(sc, SDHC_NINTR_STATUS, stat);
}
bus_space_write_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON,
bus_space_read_4(sc->sc_bst, sc->sc_bsh, MMCHS_CON) & ~CON_INIT);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~SDHC_SDCLK_ENABLE);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) & ~sc->sc.sc_clkmsk);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | CLKD(150) << clksft);
SDHC_WRITE(sc, SDHC_CLOCK_CTL,
SDHC_READ(sc, SDHC_CLOCK_CTL) | SDHC_SDCLK_ENABLE);
return;
fail:
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
bus_space_unmap(sc->sc_bst, sc->sc_bsh, oa->obio_size);
}
static void
mousebtn_attach(device_t parent, device_t self, void *aux)
{
struct mousebtn_softc *sc = device_private(self);
struct gpio_attach_args *ga = aux;
int caps;
struct wsmousedev_attach_args a;
sc->sc_dev = self;
sc->sc_gpio = ga->ga_gpio;
/* map pins */
sc->sc_map.pm_map = sc->sc_map_pins;
if (gpio_pin_map(sc->sc_gpio, ga->ga_offset, ga->ga_mask,
&sc->sc_map)) {
aprint_error(": couldn't map the pins\n");
return;
}
/* configure left pin */
caps = gpio_pin_caps(sc->sc_gpio, &sc->sc_map, MOUSEBTN_PIN_LEFT);
if (!(caps & GPIO_PIN_INPUT)) {
aprint_error(": pin is unable to read input\n");
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
return;
}
gpio_pin_ctl(sc->sc_gpio, &sc->sc_map, MOUSEBTN_PIN_LEFT,
GPIO_PIN_INPUT);
/* configure right pin */
caps = gpio_pin_caps(sc->sc_gpio, &sc->sc_map, MOUSEBTN_PIN_RIGHT);
if (!(caps & GPIO_PIN_INPUT)) {
aprint_error(": pin is unable to read input\n");
gpio_pin_unmap(sc->sc_gpio, &sc->sc_map);
return;
}
gpio_pin_ctl(sc->sc_gpio, &sc->sc_map, MOUSEBTN_PIN_RIGHT,
GPIO_PIN_INPUT);
/* interrupt settings */
sc->sc_intr[0] = intr_establish(GPIO1_BASE + ga->ga_offset,
IPL_VM, IST_EDGE_BOTH, mousebtn_intr, sc);
if (sc->sc_intr[0] == NULL) {
aprint_error(": couldn't establish interrupt\n");
return;
}
sc->sc_intr[1] = intr_establish(GPIO1_BASE + ga->ga_offset + 1,
IPL_VM, IST_EDGE_BOTH, mousebtn_intr, sc);
if (sc->sc_intr[1] == NULL) {
aprint_error(": couldn't establish interrupt\n");
intr_disestablish(sc->sc_intr[0]);
return;
}
aprint_normal(": NetWalker mouse button\n");
aprint_naive(": NetWalker mouse button\n");
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
callout_init(&sc->sc_c, 0);
a.accessops = &mousebtn_accessops;
a.accesscookie = sc;
sc->sc_buttons = 0;
sc->sc_wsmousedev = config_found(self, &a, wsmousedevprint);
}
void
acpi_md_OsRemoveInterruptHandler(void *cookie)
{
intr_disestablish(cookie);
}
static void
pci_msi_common_disestablish(pci_chipset_tag_t pc, void *cookie)
{
intr_disestablish(cookie);
}
/* ARGSUSED */
static void
bcmemmc_attach(device_t parent, device_t self, void *aux)
{
struct bcmemmc_softc *sc = device_private(self);
prop_dictionary_t dict = device_properties(self);
struct amba_attach_args *aaa = aux;
prop_number_t frequency;
int error;
sc->sc.sc_dev = self;
sc->sc.sc_dmat = aaa->aaa_dmat;
sc->sc.sc_flags = 0;
sc->sc.sc_flags |= SDHC_FLAG_32BIT_ACCESS;
sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS;
sc->sc.sc_flags |= SDHC_FLAG_NO_HS_BIT;
sc->sc.sc_caps = SDHC_VOLTAGE_SUPP_3_3V | SDHC_HIGH_SPEED_SUPP |
(SDHC_MAX_BLK_LEN_1024 << SDHC_MAX_BLK_LEN_SHIFT);
sc->sc.sc_caps2 = SDHC_SDR50_SUPP;
sc->sc.sc_host = sc->sc_hosts;
sc->sc.sc_clkbase = 50000; /* Default to 50MHz */
sc->sc_iot = aaa->aaa_iot;
/* Fetch the EMMC clock frequency from property if set. */
frequency = prop_dictionary_get(dict, "frequency");
if (frequency != NULL) {
sc->sc.sc_clkbase = prop_number_integer_value(frequency) / 1000;
}
error = bus_space_map(sc->sc_iot, aaa->aaa_addr, aaa->aaa_size, 0,
&sc->sc_ioh);
if (error) {
aprint_error_dev(self,
"can't map registers for %s: %d\n", aaa->aaa_name, error);
return;
}
sc->sc_ios = aaa->aaa_size;
sc->sc_physaddr = aaa->aaa_addr;
aprint_naive(": SDHC controller\n");
aprint_normal(": SDHC controller\n");
sc->sc_ih = intr_establish(aaa->aaa_intr, IPL_SDMMC, IST_LEVEL, sdhc_intr,
&sc->sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
aaa->aaa_intr);
goto fail;
}
aprint_normal_dev(self, "interrupting on intr %d\n", aaa->aaa_intr);
#if NBCMDMAC > 0
sc->sc_dmac = bcm_dmac_alloc(BCM_DMAC_TYPE_NORMAL, IPL_SDMMC,
bcmemmc_dma_done, sc);
if (sc->sc_dmac == NULL)
goto done;
sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
sc->sc.sc_flags |= SDHC_FLAG_EXTERNAL_DMA;
sc->sc.sc_caps |= SDHC_DMA_SUPPORT;
sc->sc.sc_vendor_transfer_data_dma = bcmemmc_xfer_data_dma;
sc->sc_state = EMMC_DMA_STATE_IDLE;
cv_init(&sc->sc_cv, "bcmemmcdma");
int rseg;
error = bus_dmamem_alloc(sc->sc.sc_dmat, PAGE_SIZE, PAGE_SIZE,
PAGE_SIZE, sc->sc_segs, 1, &rseg, BUS_DMA_WAITOK);
if (error) {
aprint_error_dev(self, "dmamem_alloc failed (%d)\n", error);
goto fail;
}
error = bus_dmamem_map(sc->sc.sc_dmat, sc->sc_segs, rseg, PAGE_SIZE,
(void **)&sc->sc_cblk, BUS_DMA_WAITOK);
if (error) {
aprint_error_dev(self, "dmamem_map failed (%d)\n", error);
goto fail;
}
KASSERT(sc->sc_cblk != NULL);
memset(sc->sc_cblk, 0, PAGE_SIZE);
error = bus_dmamap_create(sc->sc.sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0,
BUS_DMA_WAITOK, &sc->sc_dmamap);
if (error) {
aprint_error_dev(self, "dmamap_create failed (%d)\n", error);
goto fail;
}
error = bus_dmamap_load(sc->sc.sc_dmat, sc->sc_dmamap, sc->sc_cblk,
PAGE_SIZE, NULL, BUS_DMA_WAITOK|BUS_DMA_WRITE);
if (error) {
aprint_error_dev(self, "dmamap_load failed (%d)\n", error);
goto fail;
}
done:
#endif
config_interrupts(self, bcmemmc_attach_i);
return;
fail:
/* XXX add bus_dma failure cleanup */
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
}
static void
pq3ehci_attach(device_t parent, device_t self, void *aux)
{
struct cpunode_softc * const psc = device_private(parent);
struct pq3ehci_softc * const sc = device_private(self);
struct cpunode_attach_args * const cna = aux;
struct cpunode_locators * const cnl = &cna->cna_locs;
int error;
psc->sc_children |= cna->cna_childmask;
sc->sc.iot = cna->cna_le_memt; /* EHCI registers are little endian */
sc->sc.sc_dev = self;
sc->sc.sc_bus.ub_dmatag = cna->cna_dmat;
sc->sc.sc_bus.ub_hcpriv = sc;
sc->sc.sc_bus.ub_revision = USBREV_2_0;
sc->sc.sc_ncomp = 0;
sc->sc.sc_flags |= EHCIF_ETTF;
sc->sc.sc_vendor_init = pq3ehci_init;
aprint_naive(": USB controller\n");
aprint_normal(": USB controller\n");
error = bus_space_map(sc->sc.iot, cnl->cnl_addr, cnl->cnl_size, 0,
&sc->sc.ioh);
if (error) {
aprint_error_dev(self,
"can't map registers for %s#%u: %d\n",
cnl->cnl_name, cnl->cnl_instance, error);
return;
}
sc->sc.sc_size = cnl->cnl_size;
/*
* We need to tell the USB interface to snoop all off RAM starting
* at 0. Since it can do it by powers of 2, get the highest RAM
* address and roughly round it to the next power of 2 and find
* the number of leading zero bits.
*/
cpu_write_4(cnl->cnl_addr + USB_SNOOP1,
SNOOP_2GB - __builtin_clz(curcpu()->ci_softc->cpu_highmem * 2 - 1));
cpu_write_4(cnl->cnl_addr + USB_CONTROL, USB_EN);
sc->sc_ih = intr_establish(cnl->cnl_intrs[0], IPL_USB, IST_ONCHIP,
ehci_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "failed to establish interrupt %d\n",
cnl->cnl_intrs[0]);
goto fail;
}
aprint_normal_dev(self, "interrupting on irq %d\n",
cnl->cnl_intrs[0]);
/* offs is needed for EOWRITEx */
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
/* Disable interrupts, so we don't get any spurious ones. */
DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
error = ehci_init(&sc->sc);
if (error) {
aprint_error_dev(self, "init failed, error=%d\n", error);
goto fail;
}
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
return;
fail:
if (sc->sc_ih) {
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
if (sc->sc.sc_size) {
bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
sc->sc.sc_size = 0;
}
return;
}
void
genppc_pci_intr_disestablish(void *v, void *cookie)
{
intr_disestablish(cookie);
}
