/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_uint(sdb, "sim_cycles",
"total number of cycles",
&sim_cycle, 0, NULL);
stat_reg_formula(sdb, "sim_cpi",
"cycles per instruction (CPI)",
"sim_cycles / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_cond_branches" /* label for printing */,
"total conditional branches executed" /* description */,
&g_total_cond_branches /* pointer to the counter */,
0 /* initial value for the counter */, NULL);
stat_reg_formula(sdb, "sim_cond_branch_freq",
"relative frequency of conditional branches",
"sim_num_cond_branches / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_uncond_branches",
"total unconditional branches executed",
&g_total_uncond_branches, 0, NULL);
stat_reg_formula(sdb, "sim_uncond_branch_freq",
"relative frequency of unconditional branches",
"sim_num_uncond_branches / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_fp_inst",
"total number of floating-point instructions",
&g_total_fp_inst, 0, NULL);
stat_reg_formula(sdb, "sim_fp_inst_freq",
"relative frequency of fp instructions",
"sim_num_fp_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_store_inst",
"total number of store instructions",
&g_total_store_inst, 0, NULL);
stat_reg_formula(sdb, "sim_store_inst_freq",
"relative frequency of store instructions",
"sim_num_store_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_ld_inst",
"total number of load instructions",
&g_total_ld_inst, 0, NULL);
stat_reg_formula(sdb, "sim_ld_inst_freq",
"relative frequency of load instructions",
"sim_num_ld_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_imm_inst",
"total number of instructions with immediate operands",
&g_total_imm_inst, 0, NULL);
stat_reg_formula(sdb, "sim_imm_inst_freq",
"relative frequency of immediate instructions",
"sim_num_imm_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* ECE552 Assignment 1 - BEGIN CODE */
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1",
"total number of RAW hazards (q1)",
&sim_num_RAW_hazard_q1, sim_num_RAW_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1_1",
"total number of RAW hazards with 1 cycle stall (q1)",
&sim_num_RAW_hazard_q1_1, sim_num_RAW_hazard_q1_1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1_2",
"total number of RAW hazards with 2 cycle stall (q1)",
&sim_num_RAW_hazard_q1_2, sim_num_RAW_hazard_q1_2, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2",
"total number of RAW hazards (q2)",
&sim_num_RAW_hazard_q2, sim_num_RAW_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2_1",
"total number of RAW hazards with 1 cycle stall (q2)",
&sim_num_RAW_hazard_q2_1, sim_num_RAW_hazard_q2_1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2_2",
"total number of RAW hazards with 2 cycle stall (q2)",
&sim_num_RAW_hazard_q2_2, sim_num_RAW_hazard_q2_2, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q1",
"CPI from RAW hazard (q1)",
"1*((sim_num_insn-sim_num_RAW_hazard_q1)/sim_num_insn)+2*(sim_num_RAW_hazard_q1_1/sim_num_insn)+3*(sim_num_RAW_hazard_q1_2/sim_num_insn)", NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q2",
"CPI from RAW hazard (q2)",
"1*((sim_num_insn-sim_num_RAW_hazard_q2)/sim_num_insn)+2*(sim_num_RAW_hazard_q2_1/sim_num_insn)+3*(sim_num_RAW_hazard_q2_2/sim_num_insn)", NULL);
/* ECE552 Assignment 1 - END CODE */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* ECE552 Pre-Assignment - BEGIN CODE*/
stat_reg_counter(sdb, "sim_num_loads",
"total number of load instructions",
&sim_num_loads, sim_num_loads, NULL);
stat_reg_formula(sdb, "sim_load_ratio",
"load instruction fraction",
"sim_num_loads / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_lduh",
"total number of load use hazards",
&sim_num_lduh, sim_num_lduh, NULL);
stat_reg_formula(sdb, "sim_load_use_ratio",
"load use fraction",
"sim_num_lduh / sim_num_insn", NULL);
/* ECE552 Pre-Assignment - END CODE*/
/* ECE552 Assignment 1 - BEGIN CODE */
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1",
"total number of RAW hazards (q1)",
&sim_num_RAW_hazard_q1, sim_num_RAW_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2",
"total number of RAW hazards (q2)",
&sim_num_RAW_hazard_q2, sim_num_RAW_hazard_q2, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q1",
"CPI from RAW hazard (q1)",
"1" /* ECE552 - MUST ADD YOUR FORMULA */, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q2",
"CPI from RAW hazard (q2)",
"1" /* ECE552 - MUST ADD YOUR FORMULA */, NULL);
/* ECE552 Assignment 1 - END CODE */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
#ifndef NO_INSN_COUNT
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
#endif /* !NO_INSN_COUNT */
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
#ifndef NO_INSN_COUNT
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
#endif /* !NO_INSN_COUNT */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* this is a*/
stat_reg_counter(sdb, "sim_num_icache_miss", "total number of instruction cache misses", &g_icache_miss, 0, NULL);
stat_reg_formula(sdb, "sim_icache_miss_rate", "instruction cache miss rate (percentage)", "100*(sim_num_icache_miss / sim_num_insn)", NULL);
stat_reg_counter(sdb, "sim_num_icache_miss_aii", "total number of instruction cache misses aii", &g_icache_miss_aii, 0, NULL);
stat_reg_formula(sdb, "sim_icache_miss_rate_aii", "instruction cache miss rate aii (percentage)", "100*(sim_num_icache_miss_aii / sim_num_insn)", NULL);
/*B*/
stat_reg_counter(sdb, "sim_num_load_total", "total number of load", &g_load_total, 0, NULL);
stat_reg_counter(sdb, "sim_num_load_miss", "total number of load miss", &g_load_miss, 0, NULL);
stat_reg_formula(sdb, "sim_load", "load miss rate (percentage)", "100*(sim_num_load_miss / sim_num_load_total)", NULL);
stat_reg_counter(sdb, "sim_num_store_total", "total number of store", &g_store_total, 0, NULL);
stat_reg_counter(sdb, "sim_num_store_miss", "total number of store miss", &g_store_miss, 0, NULL);
stat_reg_formula(sdb, "sim_store", "store miss rate (percentage)", "100*(sim_num_store_miss / sim_num_store_total)", NULL);
stat_reg_counter(sdb, "sim_writeback", "total number of writeback", &g_writeback, 0, NULL);
stat_reg_formula(sdb, "sim_wb_ratio", "writeback to store ratio", "(sim_writeback / sim_num_store_total)", NULL);
// stat_reg_formula(sdb, "sim_icache_miss_rate_aii", "instruction cache miss rate aii (percentage)", "100*(sim_num_icache_miss_aii / sim_num_insn)", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
/* ECE552 Assignment 2 - STATS COUNTERS/FORMULAS - BEGIN */
stat_reg_counter(sdb, "sim_num_br", "total number of conditional branches", &sim_num_br, sim_num_br, NULL);
stat_reg_counter(sdb, "sim_num_mispred_static", "Static preditor: number of mispredicted branches", &sim_num_mispred_static, sim_num_mispred_static, NULL);
stat_reg_formula(sdb, "sim_br_static_ratio", "Static predictor: branch misprediction rate", "sim_num_mispred_static / sim_num_br", NULL);
stat_reg_counter(sdb, "sim_num_mispred_2bitsat", "2-bit sat. counter preditor: number of mispred. branches", &sim_num_mispred_2bitsat, sim_num_mispred_2bitsat, NULL);
stat_reg_formula(sdb, "sim_br_2bitsat_ratio", "2-bit sat. counter predictor: branch misprediction rate", "sim_num_mispred_2bitsat / sim_num_br", NULL);
stat_reg_counter(sdb, "sim_num_mispred_2level", "Two level preditor: number of mispredicted branches", &sim_num_mispred_2level, sim_num_mispred_2level, NULL);
stat_reg_formula(sdb, "sim_br_2level_ratio", "Two level predictor: branch misprediction rate", "sim_num_mispred_2level / sim_num_br", NULL);
stat_reg_counter(sdb, "sim_num_mispred_openend", "Open-ended preditor: number of mispredicted branches", &sim_num_mispred_openend, sim_num_mispred_openend, NULL);
stat_reg_formula(sdb, "sim_br_openend_ratio", "Open-ended predictor: branch misprediction rate", "sim_num_mispred_openend / sim_num_br", NULL);
/* ECE552 Assignment 2 - STATS COUNTERS/FORMULAS - END */
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb) /* stats database */
{
int i;
/* register baseline stats */
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* register cache stats */
if (cache_il1
&& (cache_il1 != cache_dl1 && cache_il1 != cache_dl2))
cache_reg_stats(cache_il1, sdb);
if (cache_il2
&& (cache_il2 != cache_dl1 && cache_il2 != cache_dl2))
cache_reg_stats(cache_il2, sdb);
if (cache_dl1)
cache_reg_stats(cache_dl1, sdb);
if (cache_dl2)
cache_reg_stats(cache_dl2, sdb);
if (itlb)
cache_reg_stats(itlb, sdb);
if (dtlb)
cache_reg_stats(dtlb, sdb);
for (i=0; i<pcstat_nelt; i++)
{
char buf[512], buf1[512];
struct stat_stat_t *stat;
/* track the named statistical variable by text address */
/* find it... */
stat = stat_find_stat(sdb, pcstat_vars[i]);
if (!stat)
fatal("cannot locate any statistic named `%s'", pcstat_vars[i]);
/* stat must be an integral type */
if (stat->sc != sc_int && stat->sc != sc_uint && stat->sc != sc_counter)
fatal("`-pcstat' statistical variable `%s' is not an integral type",
stat->name);
/* register this stat */
pcstat_stats[i] = stat;
pcstat_lastvals[i] = STATVAL(stat);
/* declare the sparce text distribution */
sprintf(buf, "%s_by_pc", stat->name);
sprintf(buf1, "%s (by text address)", stat->desc);
pcstat_sdists[i] = stat_reg_sdist(sdb, buf, buf1,
/* initial value */0,
/* print fmt */(PF_COUNT|PF_PDF),
/* format */"0x%p %u %.2f",
/* print fn */NULL);
}
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* ECE552 Assignment 1 - BEGIN CODE */
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1",
"total number of RAW hazards (q1)",
&sim_num_RAW_hazard_q1, sim_num_RAW_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_one_cycle_hazard_q1",
"total one cycle hazard q1",
&sim_num_one_cycle_hazard_q1, sim_num_one_cycle_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_two_cycle_hazard_q1",
"total two cycle hazard q1",
&sim_num_two_cycle_hazard_q1, sim_num_two_cycle_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_one_cycle_hazard_q2",
"total one cycle hazard q2",
&sim_num_one_cycle_hazard_q2, sim_num_one_cycle_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_two_cycle_hazard_q2",
"total two cycle hazard q2",
&sim_num_two_cycle_hazard_q2, sim_num_two_cycle_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_one_cycle_hazard_q3",
"total one cycle hazard q3",
&sim_num_one_cycle_hazard_q3, sim_num_one_cycle_hazard_q3, NULL);
stat_reg_counter(sdb, "sim_num_two_cycle_hazard_q3",
"total two cycle hazard q3",
&sim_num_two_cycle_hazard_q3, sim_num_two_cycle_hazard_q3, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2",
"total number of RAW hazards (q2)",
&sim_num_RAW_hazard_q2, sim_num_RAW_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_WAW_hazard_q3",
"total number of WAW hazards (q3)",
&sim_num_WAW_hazard_q3, sim_num_WAW_hazard_q3, NULL);
/* These are structural hazards occuring when two instructions **without** a WAW dependence
try to do the WriteBack in the same cycle. The latest instruction should stall.
*/
stat_reg_counter(sdb, "sim_num_structural_hazard_q3",
"total number of structural hazards (q3)",
&sim_num_structural_hazard_q3, sim_num_structural_hazard_q3, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q1",
"CPI from RAW hazard (q1)",
"1 + (sim_num_one_cycle_hazard_q1/sim_num_insn)+ ((sim_num_two_cycle_hazard_q1/sim_num_insn)*2)", NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q2",
"CPI from RAW hazard (q2)",
"1 + (sim_num_one_cycle_hazard_q2/sim_num_insn) + ((sim_num_two_cycle_hazard_q2/sim_num_insn)*2)", NULL);
/* Include both WAW and structural hazards in your CPI computation */
stat_reg_formula(sdb, "CPI_from_WAW_and_Structural_hazard_q3",
"CPI from WAW and structural hazards (q3)",
"1 + ((sim_num_one_cycle_hazard_q3 + sim_num_structural_hazard_q3)/sim_num_insn) + ((sim_num_two_cycle_hazard_q3/sim_num_insn)*2)", NULL);
/* ECE552 Assignment 1 - END CODE */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
int i;
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
if (prof_ic)
{
/* instruction class profile */
ic_prof = stat_reg_dist(sdb, "sim_inst_class_prof",
"instruction class profile",
/* initial value */0,
/* array size */ic_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */inst_class_str,
/* print fn */NULL);
}
if (prof_inst)
{
int i;
char buf[512];
/* conjure up appropriate instruction description strings */
for (i=0; i < /* skip NA */OP_MAX-1; i++)
{
sprintf(buf, "%-8s %-6s", md_op2name[i+1], md_op2format[i+1]);
inst_str[i] = mystrdup(buf);
}
/* instruction profile */
inst_prof = stat_reg_dist(sdb, "sim_inst_prof",
"instruction profile",
/* initial value */0,
/* array size */ /* skip NA */OP_MAX-1,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */inst_str,
/* print fn */NULL);
}
if (prof_bc)
{
/* instruction branch profile */
bc_prof = stat_reg_dist(sdb, "sim_branch_prof",
"branch instruction profile",
/* initial value */0,
/* array size */bc_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */branch_class_str,
/* print fn */NULL);
}
if (prof_am)
{
/* instruction branch profile */
am_prof = stat_reg_dist(sdb, "sim_addr_mode_prof",
"addressing mode profile",
/* initial value */0,
/* array size */md_amode_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */md_amode_str,
/* print fn */NULL);
}
if (prof_seg)
{
/* instruction branch profile */
seg_prof = stat_reg_dist(sdb, "sim_addr_seg_prof",
"load/store address segment profile",
/* initial value */0,
/* array size */seg_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */addr_seg_str,
/* print fn */NULL);
}
if (prof_tsyms && sym_ntextsyms != 0)
{
int i;
/* load program symbols */
sym_loadsyms(ld_prog_fname, load_locals);
/* conjure up appropriate instruction description strings */
tsym_names = (char **)calloc(sym_ntextsyms, sizeof(char *));
for (i=0; i < sym_ntextsyms; i++)
tsym_names[i] = sym_textsyms[i]->name;
/* text symbol profile */
tsym_prof = stat_reg_dist(sdb, "sim_text_sym_prof",
"text symbol profile",
/* initial value */0,
/* array size */sym_ntextsyms,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */tsym_names,
/* print fn */NULL);
}
if (prof_dsyms && sym_ndatasyms != 0)
{
int i;
/* load program symbols */
sym_loadsyms(ld_prog_fname, load_locals);
/* conjure up appropriate instruction description strings */
dsym_names = (char **)calloc(sym_ndatasyms, sizeof(char *));
for (i=0; i < sym_ndatasyms; i++)
dsym_names[i] = sym_datasyms[i]->name;
/* data symbol profile */
dsym_prof = stat_reg_dist(sdb, "sim_data_sym_prof",
"data symbol profile",
/* initial value */0,
/* array size */sym_ndatasyms,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */dsym_names,
/* print fn */NULL);
}
if (prof_taddr)
{
/* text address profile (sparse profile), NOTE: a dense print format
is used, its more difficult to read, but the profiles are *much*
smaller, I've assumed that the profiles are read by programs, at
least for your sake I hope this is the case!! */
taddr_prof = stat_reg_sdist(sdb, "sim_text_addr_prof",
"text address profile",
/* initial value */0,
/* print format */(PF_COUNT|PF_PDF),
/* format */"0x%p %u %.2f",
/* print fn */NULL);
}
for (i=0; i<pcstat_nelt; i++)
{
char buf[512], buf1[512];
struct stat_stat_t *stat;
/* track the named statistical variable by text address */
/* find it... */
stat = stat_find_stat(sdb, pcstat_vars[i]);
if (!stat)
fatal("cannot locate any statistic named `%s'", pcstat_vars[i]);
/* stat must be an integral type */
if (stat->sc != sc_int && stat->sc != sc_uint && stat->sc != sc_counter)
fatal("`-pcstat' statistical variable `%s' is not an integral type",
stat->name);
/* register this stat */
pcstat_stats[i] = stat;
pcstat_lastvals[i] = STATVAL(stat);
/* declare the sparce text distribution */
sprintf(buf, "%s_by_pc", stat->name);
sprintf(buf1, "%s (by text address)", stat->desc);
pcstat_sdists[i] = stat_reg_sdist(sdb, buf, buf1,
/* initial value */0,
/* print format */(PF_COUNT|PF_PDF),
/* format */"0x%p %u %.2f",
/* print fn */NULL);
}
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}