示例#1
0
文件: pm.c 项目: kzlin129/tt-gpl
/*
 * Let's power down on idle, but only if we are really
 * idle, because once we start down the path of
 * going idle we continue to do idle even if we get
 * a clock tick interrupt . .
 */
void omap_pm_idle(void)
{
	int (*func_ptr)(void) = 0;
	unsigned int mask32 = 0;

	/*
	 * If the DSP is being used let's just idle the CPU, the overhead
	 * to wake up from Big Sleep is big, milliseconds versus micro
	 * seconds for wait for interrupt.
	 */

	local_irq_disable();
	local_fiq_disable();
	if (need_resched()) {
		local_fiq_enable();
		local_irq_enable();
		return;
	}
	mask32 = omap_readl(ARM_SYSST);

	/*
	 * Since an interrupt may set up a timer, we don't want to
	 * reprogram the hardware timer with interrupts enabled.
	 * Re-enable interrupts only after returning from idle.
	 */
	timer_dyn_reprogram();

	if ((mask32 & DSP_IDLE) == 0) {
		__asm__ volatile ("mcr	p15, 0, r0, c7, c0, 4");
	} else {
示例#2
0
static int tegra114_idle_power_down(struct cpuidle_device *dev,
				    struct cpuidle_driver *drv,
				    int index)
{
	local_fiq_disable();

	tegra_set_cpu_in_lp2();
	cpu_pm_enter();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);

	call_firmware_op(prepare_idle);

	/* Do suspend by ourselves if the firmware does not implement it */
	if (call_firmware_op(do_idle) == -ENOSYS)
		cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);

	cpu_pm_exit();
	tegra_clear_cpu_in_lp2();

	local_fiq_enable();

	return index;
}
示例#3
0
static inline void pnx4008_standby(void)
{
	void (*pnx4008_cpu_standby_ptr) (void);

	local_irq_disable();
	local_fiq_disable();

	clk_disable(pll4_clk);

	/*saving portion of SRAM to be used by suspend function. */
	memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);

	/*make sure SRAM copy gets physically written into SDRAM.
	   SDRAM will be placed into self-refresh during power down */
	pnx4008_cache_clean_invalidate();

	/*copy suspend function into SRAM */
	memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);

	/*do suspend */
	pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
	pnx4008_cpu_standby_ptr();

	/*restoring portion of SRAM that was used by suspend function */
	memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);

	clk_enable(pll4_clk);

	local_fiq_enable();
	local_irq_enable();
}
static void ux500_restart(char mode, const char *cmd)
{
	unsigned short reset_code;
	unsigned short preset_code;

	local_irq_disable();
	local_fiq_disable();

	preset_code = reboot_reason_get_preset();

	if (preset_code != SW_RESET_CRASH)
		prcmu_system_reset(preset_code);
	else {
		reset_code = reboot_reason_code(cmd);
		prcmu_system_reset(reset_code);
	}

	mdelay(1000);

	/*
	 * On 5500, the PRCMU firmware waits for up to 2 seconds for the modem
	 * to respond.
	 */
	if (cpu_is_u5500())
		mdelay(2000);

	printk(KERN_ERR "Reboot via PRCMU failed -- System halted\n");
	while (1)
		;
}
/*
 * mt_irq_mask_all: disable all interrupts
 * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
 * Return 0 for success; return negative values for failure.
 * (This is ONLY used for the idle current measurement by the factory mode.)
 */
int mt_irq_mask_all(struct mtk_irq_mask *mask)
{
    unsigned long flags;

    if (mask) {
#if defined(CONFIG_FIQ_GLUE)
        local_fiq_disable();
#endif
        spin_lock_irqsave(&irq_lock, flags);

        mask->mask0 = readl(GIC_ICDISER0);
        mask->mask1 = readl(GIC_ICDISER1);
        mask->mask2 = readl(GIC_ICDISER2);
        mask->mask3 = readl(GIC_ICDISER3);
        mask->mask4 = readl(GIC_ICDISER4);

        writel(0xFFFFFFFF, GIC_ICDICER0);
        writel(0xFFFFFFFF, GIC_ICDICER1);
        writel(0xFFFFFFFF, GIC_ICDICER2);
        writel(0xFFFFFFFF, GIC_ICDICER3);
        mt65xx_reg_sync_writel(0xFFFFFFFF, GIC_ICDICER4);

        spin_unlock_irqrestore(&irq_lock, flags);
#if defined(CONFIG_FIQ_GLUE)
        local_fiq_enable();
#endif

        mask->header = IRQ_MASK_HEADER;
        mask->footer = IRQ_MASK_FOOTER;

        return 0;
    } else {
        return -1;
    }
}
示例#6
0
static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,
				      struct cpuidle_driver *drv,
				      int index)
{
	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
	bool entered_lp2 = false;
	bool last_cpu;

	local_fiq_disable();

	last_cpu = tegra_set_cpu_in_lp2(cpu);
	cpu_pm_enter();

	if (cpu == 0) {
		if (last_cpu)
			entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
								     index);
		else
			cpu_do_idle();
	} else {
		entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
	}

	cpu_pm_exit();
	tegra_clear_cpu_in_lp2(cpu);

	local_fiq_enable();

	smp_rmb();

	return (entered_lp2) ? index : 0;
}
示例#7
0
static int tegra_idle_enter_clock_gating(struct cpuidle_device *dev,
	struct cpuidle_driver *drv, int index)
{
	ktime_t enter, exit;
	s64 us;

	/* cpu_idle calls us with IRQs disabled */

	local_fiq_disable();

	enter = ktime_get();

	cpu_do_idle();

	exit = ktime_sub(ktime_get(), enter);
	us = ktime_to_us(exit);

	local_fiq_enable();

	/* cpu_idle expects us to return with IRQs enabled */
	local_irq_enable();

	dev->last_residency = us;
	return index;
}
示例#8
0
static void gta02_fiq_kick(void)
{
	unsigned long flags;
	u32 tcon;

	/* we have to take care about FIQ because this modification is
	 * non-atomic, FIQ could come in after the read and before the
	 * writeback and its changes to the register would be lost
	 * (platform INTMSK mod code is taken care of already)
	 */
	local_save_flags(flags);
	local_fiq_disable();
	/* allow FIQs to resume */
	__raw_writel(__raw_readl(S3C2410_INTMSK) &
		     ~(1 << (gta02_fiq_irq - S3C2410_CPUIRQ_OFFSET)),
		     S3C2410_INTMSK);
	tcon = __raw_readl(S3C2410_TCON) & ~S3C2410_TCON_T3START;
	/* fake the timer to a count of 1 */
	__raw_writel(1, S3C2410_TCNTB(gta02_fiq_timer_index));
	__raw_writel(tcon | S3C2410_TCON_T3MANUALUPD, S3C2410_TCON);
	__raw_writel(tcon | S3C2410_TCON_T3MANUALUPD | S3C2410_TCON_T3START,
		     S3C2410_TCON);
	__raw_writel(tcon | S3C2410_TCON_T3START, S3C2410_TCON);
	local_irq_restore(flags);
}
示例#9
0
void ux500_restart(enum reboot_mode mode, const char *cmd)
{
	local_irq_disable();
	local_fiq_disable();

	prcmu_system_reset(0);
}
示例#10
0
static inline void pnx4008_suspend(void)
{
	void (*pnx4008_cpu_suspend_ptr) (void);

	local_irq_disable();
	local_fiq_disable();

	clk_disable(pll4_clk);

	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
	__raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));

	/*saving portion of SRAM to be used by suspend function. */
	memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);

	/*make sure SRAM copy gets physically written into SDRAM.
	   SDRAM will be placed into self-refresh during power down */
	flush_cache_all();

	/*copy suspend function into SRAM */
	memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);

	/*do suspend */
	pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
	pnx4008_cpu_suspend_ptr();

	/*restoring portion of SRAM that was used by suspend function */
	memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);

	clk_enable(pll4_clk);

	local_fiq_enable();
	local_irq_enable();
}
static void msm_pm_restart(char str, const char *cmd)
{
        unsigned size;
        samsung_vendor1_id *smem_vendor1 = \
                (samsung_vendor1_id *)smem_get_entry(SMEM_ID_VENDOR1, &size);

        if (smem_vendor1) {
                smem_vendor1->silent_reset = 0xAEAEAEAE;
                smem_vendor1->reboot_reason = restart_reason;
        smem_vendor1->AP_reserved[0] = 0;
        } else {
                printk(KERN_EMERG "smem_flag is NULL\n");
        }

        pr_debug("The reset reason is %x\n", restart_reason);

        /* Disable interrupts */
        local_irq_disable();
        local_fiq_disable();

        /*
         * Take out a flat memory mapping  and will
         * insert a 1:1 mapping in place of
         * the user-mode pages to ensure predictable results
         * This function takes care of flushing the caches
         * and flushing the TLB.
         */
        setup_mm_for_reboot();

        msm_proc_comm(PCOM_RESET_CHIP, &restart_reason, 0);

        for (;;)
                ;
}
示例#12
0
/* Architecture-specific restart for Kaen and other boards, where a GPIO line
 * is used to reset CPU and TPM together.
 *
 * Most of this function mimicks arm_machine_restart in process.c, except that
 * that function turns off caching and then flushes the cache one more time,
 * and we do not.  This is certainly less clean but unlikely to matter as the
 * additional dirty cache lines do not contain critical data.
 *
 * On boards that don't implement the reset hardware we fall back to the old
 * method.
 */
static void gpio_machine_restart(char mode, const char *cmd)
{
	tegra_pm_flush_console();

	/* Disable interrupts first */
	local_irq_disable();
	local_fiq_disable();

	/* We must flush the L2 cache for preserved / kcrashmem */
	outer_flush_all();

	/* Clean and invalidate caches */
	flush_cache_all();

	/* Reboot by resetting CPU and TPM via GPIO */
	gpio_set_value(TEGRA_GPIO_RESET, 0);

	/*
	 * printk should still work with interrupts disabled, but since we've
	 * already flushed this isn't guaranteed to actually make it out.  We'll
	 * print it anyway just in case.
	 */
	printk(KERN_INFO "restart: trying legacy reboot\n");
	legacy_arm_pm_restart(mode, cmd);
}
示例#13
0
static void gta02_fiq_disable(void)
{
	__raw_writel(0, S3C2410_INTMOD);
	local_fiq_disable();
	gta02_fiq_irq = 0; /* no active source interrupt now either */

}
示例#14
0
/*
 * mt_irq_mask_restore: restore all interrupts 
 * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
 * Return 0 for success; return negative values for failure.
 * (This is ONLY used for the idle current measurement by the factory mode.)
 */
int mt_irq_mask_restore(struct mtk_irq_mask *mask)
{
    unsigned long flags;

    if (!mask) {
        return -1;
    }
    if (mask->header != IRQ_MASK_HEADER) {
        return -1;
    }
    if (mask->footer != IRQ_MASK_FOOTER) {
        return -1;
    }

#if defined(CONFIG_FIQ_GLUE)
    local_fiq_disable();
#endif
    spin_lock_irqsave(&irq_lock, flags);

    writel(mask->mask0, GIC_ICDISER0);
    writel(mask->mask1, GIC_ICDISER1);
    writel(mask->mask2, GIC_ICDISER2);
    writel(mask->mask3, GIC_ICDISER3);
    mt65xx_reg_sync_writel(mask->mask4, GIC_ICDISER4);

    spin_unlock_irqrestore(&irq_lock, flags);
#if defined(CONFIG_FIQ_GLUE)
    local_fiq_enable();
#endif

    return 0;
}
示例#15
0
static void sc8825_machine_restart(char mode, const char *cmd)
{

	/* Flush the console to make sure all the relevant messages make it
	 * out to the console drivers */
	mdelay(500);

	/* Disable interrupts first */
	local_irq_disable();
	local_fiq_disable();

	/*
	 * FIXME: Do not turn off cache before ldrex/strex!
	 */

	/*
	 * Now call the architecture specific reboot code.
	 */
	arch_reset(mode, cmd);

	/*
	 * Whoops - the architecture was unable to reboot.
	 * Tell the user!
	 */
	mdelay(1000);
	printk("Reboot failed -- System halted\n");
	while (1);
}
示例#16
0
/*
 * Let's power down on idle, but only if we are really
 * idle, because once we start down the path of
 * going idle we continue to do idle even if we get
 * a clock tick interrupt . .
 */
void omap_pm_idle(void)
{
	int (*func_ptr)(void) = 0;
	unsigned int mask32 = 0;

	/*
	 * If the DSP is being used let's just idle the CPU, the overhead
	 * to wake up from Big Sleep is big, milliseconds versus micro
	 * seconds for wait for interrupt.
	 */

	local_irq_disable();
	local_fiq_disable();
	if (need_resched()) {
		local_fiq_enable();
		local_irq_enable();
		return;
	}
	mask32 = omap_readl(ARM_SYSST);

	if (vst_setup()) {
		local_fiq_enable();
		local_irq_enable();
		return;
	}

#if defined(CONFIG_OMAP_32K_TIMER) && defined(CONFIG_NO_IDLE_HZ)
	/* Override timer to use VST for the next cycle */
	omap_32k_timer_next_vst_interrupt();
#endif

	if ((mask32 & DSP_IDLE) == 0) {
		__asm__ volatile ("mcr	p15, 0, r0, c7, c0, 4");
	} else {
int rhea_force_sleep(suspend_state_t state)
{
	struct kona_idle_state s;
	int i;

	memset(&s, 0, sizeof(s));
	s.state = get_force_sleep_state();

	/* No more scheduling out */
	local_irq_disable();
	local_fiq_disable();

	force_sleep = 1;

	while (1) {
		for (i = 0; i < PWR_MGR_NUM_EVENTS; i++) {
			int test = 0;

			test |= (i == SOFTWARE_0_EVENT) ? 1 : 0;
			test |= (i == SOFTWARE_2_EVENT) ? 1 : 0;
			test |= (i == VREQ_NONZERO_PI_MODEM_EVENT) ? 1 : 0;

			if (test == 0)
				pwr_mgr_event_trg_enable(i, 0);
		}
		disable_all_interrupts();

		enter_idle_state(&s);
	}
}
示例#18
0
static int omap2_pm_suspend(void)
{
	int processor_type = 0;

	/* REVISIT: 0x21 or 0x26? */
	if (cpu_is_omap2420())
		processor_type = 0x21;

	if (!processor_type)
		return -ENOTSUPP;

	local_irq_disable();
	local_fiq_disable();

	omap2_pm_save_registers();

	/* Disable interrupts except for the wake events */
	INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
	INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
	INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;

	pmdomain_set_autoidle();

	/* Clear old wake-up events */
	PM_WKST1_CORE = 0;
	PM_WKST2_CORE = 0;
	PM_WKST_WKUP = 0;

	/* Enable wake-up events */
	PM_WKEN1_CORE = (1 << 22) | (1 << 21);	/* UART1 & 2 */
	PM_WKEN2_CORE = (1 << 2);		/* UART3 */
	PM_WKEN_WKUP = (1 << 2) | (1 << 0);	/* GPIO & GPT1 */

	/* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
	 * in the SRAM suspend code */
	CM_FCLKEN1_CORE = 0;
	CM_FCLKEN2_CORE = 0;
	CM_ICLKEN1_CORE = 0;
	CM_ICLKEN3_CORE = 0;
	CM_ICLKEN4_CORE = 0;

	omap2_pm_debug("Status before suspend");

	/* Must wait for serial buffers to clear */
	mdelay(200);

	/* Jump to SRAM suspend code
	 * REVISIT: When is this SDRC_DLLB_CTRL?
	 */
	omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);

	/* Back from sleep */
	omap2_pm_restore_registers();

	local_fiq_enable();
	local_irq_enable();

	return 0;
}
示例#19
0
static void zeus_poweroff(void)
{
	/* int n_usbic_state; */

	printk("\nZEUS BOARD GOING TO SHUTDOWN!!!\n");

#if defined(CONFIG_USB_ANDROID)
	android_usb_set_connected(0);
#endif
        tl2796_lcd_poweroff();
	/* get_real_usbic_state(); */
	//gpio_direction_output(GPIO_MSM_RST,0);
	//gpio_direction_output(GPIO_FONE_ACTIVE, 0);
	// if (GPIO_TA_CONNECTED_N is LOW)
//#if (CONFIG_ARCHER_REV < ARCHER_REV13)
//	if ( get_real_usbic_state() )
         if ( sec_switch_get_cable_status() != CABLE_TYPE_NONE ) //me add
//#else
//	if ( !gpio_get_value( OMAP_GPIO_TA_NCONNECTED ) || gpio_get_value( OMAP_GPIO_IF_CON_SENSE ) )
//#endif
	{
		printk("Warmreset by TA or USB or Jtag\n\n");

		preempt_disable();
		local_irq_disable();
		local_fiq_disable();

#ifdef CONFIG_ARCHER_KOR_DEBUG
		omap_writel(0x54455352, OMAP343X_CTRL_BASE + 0x9C4); // set to normal reset
#endif
#if 1

		/* using watchdog reset */
		omap_watchdog_reset();
		/* machine_restart("ta_inserted"); */
#else
		/* using core_dpll_warmreset with global reset */
		//omap3_configure_core_dpll_warmreset();
		machine_restart("ta_inserted");
#endif

		while(1);
	}
	else
	{
		printk("Power Off !\n\n");
		while(1)
		{
			gpio_direction_output(GPIO_PS_HOLD, 0);

			if (0 /*is_powerbutton_pressed*/)
				printk("Power button is pressed\n\n");
			else
				twl4030_poweroff();
		}
	}

	return;
}
示例#20
0
void notrace save_processor_state(void)
{
	WARN_ON(num_online_cpus() != 1);
	local_fiq_disable();
#ifdef CONFIG_MTK_HIBERNATION
	mtk_save_processor_state();
#endif
}
示例#21
0
/*
 * Let's power down on idle, but only if we are really
 * idle, because once we start down the path of
 * going idle we continue to do idle even if we get
 * a clock tick interrupt . .
 */
void omap_pm_idle(void)
{
    extern __u32 arm_idlect1_mask;
    __u32 use_idlect1 = arm_idlect1_mask;
    int do_sleep = 0;

    local_irq_disable();
    local_fiq_disable();
    if (need_resched()) {
        local_fiq_enable();
        local_irq_enable();
        return;
    }

#ifdef CONFIG_OMAP_MPU_TIMER
#warning Enable 32kHz OS timer in order to allow sleep states in idle
    use_idlect1 = use_idlect1 & ~(1 << 9);
#else

    while (enable_dyn_sleep) {

#ifdef CONFIG_CBUS_TAHVO_USB
        extern int vbus_active;
        /* Clock requirements? */
        if (vbus_active)
            break;
#endif
        do_sleep = 1;
        break;
    }

#endif

#ifdef CONFIG_OMAP_DM_TIMER
    use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
#endif

    if (omap_dma_running())
        use_idlect1 &= ~(1 << 6);

    /* We should be able to remove the do_sleep variable and multiple
     * tests above as soon as drivers, timer and DMA code have been fixed.
     * Even the sleep block count should become obsolete. */
    if ((use_idlect1 != ~0) || !do_sleep) {

        __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
        if (cpu_is_omap15xx())
            use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
        else
            use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
        omap_writel(use_idlect1, ARM_IDLECT1);
        __asm__ volatile ("mcr	p15, 0, r0, c7, c0, 4");
        omap_writel(saved_idlect1, ARM_IDLECT1);

        local_fiq_enable();
        local_irq_enable();
        return;
    }
示例#22
0
void omap1_pm_idle(void)
{
	extern __u32 arm_idlect1_mask;
	__u32 use_idlect1 = arm_idlect1_mask;
	int do_sleep = 0;

	local_irq_disable();
	local_fiq_disable();
	if (need_resched()) {
		local_fiq_enable();
		local_irq_enable();
		return;
	}

#ifdef CONFIG_OMAP_MPU_TIMER
#warning Enable 32kHz OS timer in order to allow sleep states in idle
	use_idlect1 = use_idlect1 & ~(1 << 9);
#else

	while (enable_dyn_sleep) {

#ifdef CONFIG_CBUS_TAHVO_USB
		extern int vbus_active;
		
		if (vbus_active)
			break;
#endif
		do_sleep = 1;
		break;
	}

#endif

#ifdef CONFIG_OMAP_DM_TIMER
	use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
#endif

	if (omap_dma_running())
		use_idlect1 &= ~(1 << 6);

	
	if ((use_idlect1 != ~0) || !do_sleep) {

		__u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
		if (cpu_is_omap15xx())
			use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
		else
			use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
		omap_writel(use_idlect1, ARM_IDLECT1);
		__asm__ volatile ("mcr	p15, 0, r0, c7, c0, 4");
		omap_writel(saved_idlect1, ARM_IDLECT1);

		local_fiq_enable();
		local_irq_enable();
		return;
	}
示例#23
0
文件: pm.c 项目: ffxx68/EVBSP-Kernel
void emxx_pm_idle(void)
{
	local_irq_disable();
	local_fiq_disable();
	if (need_resched()) {
		local_fiq_enable();
		local_irq_enable();
		return;
	}

	pm_idle_count++;

	if (sleep_while_idle_enable && !suspend_disable) {
#ifdef CONFIG_SMP
		if ((0 == hard_smp_processor_id()) &&
			!(inl(SMU_CLKSTOPSIG_ST) & PWSTATE_PD_NE1)) {
			/* cpu1 wfi */
			emxx_close_clockgate(EMXX_CLK_TI1);
#endif
			if (emxx_can_sleep()) {
				emxx_sleep_while_idle = 1;
				if (0 == emxx_pm_suspend(PM_SUSPEND_STANDBY)) {
					emxx_add_neigh_timer();
					emxx_add_timer_writeback();
					emxx_add_workqueue_timer();

					emxx_sleep_while_idle = 0;
					sleep_while_idle_count++;
#ifdef CONFIG_SMP
					emxx_open_clockgate(EMXX_CLK_TI1);
#endif
					set_need_resched();

					local_fiq_enable();
					local_irq_enable();

					return;
				}
				emxx_add_neigh_timer();
				emxx_add_timer_writeback();
				emxx_add_workqueue_timer();

				emxx_sleep_while_idle = 0;
			}
#ifdef CONFIG_SMP
			emxx_open_clockgate(EMXX_CLK_TI1);
		}
#endif
	}

	arch_idle();

	local_fiq_enable();
	local_irq_enable();
}
示例#24
0
/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @state: The target state to be programmed
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
                            struct cpuidle_state *state)
{
    struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
    struct timespec ts_preidle, ts_postidle, ts_idle;
    u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
    u32 saved_mpu_state;

    current_cx_state = *cx;

    /* Used to keep track of the total time in idle */
    getnstimeofday(&ts_preidle);

    local_irq_disable();
    local_fiq_disable();

    if (!enable_off_mode) {
        if (mpu_state < PWRDM_POWER_RET)
            mpu_state = PWRDM_POWER_RET;
        if (core_state < PWRDM_POWER_RET)
            core_state = PWRDM_POWER_RET;
    }

    if (omap_irq_pending() || need_resched())
        goto return_sleep_time;

    saved_mpu_state = pwrdm_read_next_pwrst(mpu_pd);
    pwrdm_set_next_pwrst(mpu_pd, mpu_state);
    pwrdm_set_next_pwrst(core_pd, core_state);

    if (cx->type == OMAP3_STATE_C1) {
        pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
        pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
    }

    /* Execute ARM wfi */
    omap_sram_idle();

    if (cx->type == OMAP3_STATE_C1) {
        pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
        pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
    }

    pwrdm_set_next_pwrst(mpu_pd, saved_mpu_state);

return_sleep_time:
    getnstimeofday(&ts_postidle);
    ts_idle = timespec_sub(ts_postidle, ts_preidle);

    local_irq_enable();
    local_fiq_enable();

    return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
}
示例#25
0
static void magus_pm_idle(void)
{
	int do_sleep;
	void (*magus_idle_loop_suspend_ptr) (void);

	local_irq_disable();
	local_fiq_disable();
	if (need_resched()) {
		local_fiq_enable();
		local_irq_enable();
		return;
	}

	/*
	 * Since an interrupt may set up a timer, we don't want to
	 * reprogram the hardware timer with interrupts enabled.
	 * Re-enable interrupts only after returning from idle.
	 */
	timer_dyn_reprogram();
	
	do_sleep = 0;
	while (enable_dyn_sleep) {
		do_sleep = 1;
		break;
	}
	if(do_sleep){   
	    
		stat_idle_times ++;
		/*saving portion of SRAM to be used by suspend function. */
	    memcpy(saved_sram, (void *)SRAM_VA, magus_idle_loop_suspend_sz);

	    /*make sure SRAM copy gets physically written into SDRAM.
        SDRAM will be placed into self-refresh during power down */
	    flush_cache_all();

	    /*copy suspend function into SRAM */
	    memcpy((void *)SRAM_VA, magus_idle_loop_suspend, magus_idle_loop_suspend_sz);

	    /*do suspend */
	    magus_idle_loop_suspend_ptr = (void *)SRAM_VA;
	    magus_idle_loop_suspend_ptr();
		//omap2_sram_idle();

	    /*restoring portion of SRAM that was used by suspend function */
 	    memcpy((void *)SRAM_VA, saved_sram, magus_idle_loop_suspend_sz);


		local_fiq_enable();
		local_irq_enable();
		return;
	}	
	local_fiq_enable();
	local_irq_enable();
}
static void sec_reboot(char str, const char *cmd)
{
	local_irq_disable();
	local_fiq_disable();

	pr_emerg("%s (%d, %s)\n", __func__, str, cmd ? cmd : "(null)");

	writel(0x12345678,SPRD_INFORM2);	/* Don't enter lpm mode */

	if (!cmd) {
		writel(REBOOT_MODE_PREFIX | REBOOT_MODE_NONE, SPRD_INFORM3);
	} else {
		unsigned long value;
		if (!strcmp(cmd, "fota"))
			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_ARM11_FOTA,
			       SPRD_INFORM3);
		else if (!strcmp(cmd, "recovery"))
			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_RECOVERY,
			       SPRD_INFORM3);
		else if (!strcmp(cmd, "download"))
			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_DOWNLOAD,
			       SPRD_INFORM3);
		else if (!strcmp(cmd, "upload"))
			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_UPLOAD,
			       SPRD_INFORM3);
#if defined(CONFIG_RTC_CHN_ALARM_BOOT)
		else if (!strcmp(cmd, "alarmboot"))
			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_ALARM_BOOT,
			       SPRD_INFORM3);
#endif
		else if (!strncmp(cmd, "debug", 5)
			 && !kstrtoul(cmd + 5, 0, &value))
			writel(REBOOT_SET_PREFIX | REBOOT_SET_DEBUG | value,
			       SPRD_INFORM3);
		else if (!strncmp(cmd, "swsel", 5)
			 && !kstrtoul(cmd + 5, 0, &value))
			writel(REBOOT_SET_PREFIX | REBOOT_SET_SWSEL | value,
			       SPRD_INFORM3);
		else if (!strncmp(cmd, "sud", 3)
			 && !kstrtoul(cmd + 3, 0, &value))
			writel(REBOOT_SET_PREFIX | REBOOT_SET_SUD | value,
			       SPRD_INFORM3);
		else
			writel(REBOOT_MODE_PREFIX | REBOOT_MODE_NONE,
			       SPRD_INFORM3);
	}

	flush_cache_all();
	outer_flush_all();
	arch_reset(0, cmd);

	pr_emerg("%s: waiting for reboot\n", __func__);
	while (1);
}
void machine_kexec(struct kimage *image)
{
	unsigned long page_list;
	unsigned long reboot_code_buffer_phys;
	void *reboot_code_buffer;

	arch_kexec();

	page_list = image->head & PAGE_MASK;

	/* we need both effective and real address here */
	reboot_code_buffer_phys =
	    page_to_pfn(image->control_code_page) << PAGE_SHIFT;
	reboot_code_buffer = page_address(image->control_code_page);

	/* Prepare parameters for reboot_code_buffer*/
	mem_text_write_kernel_word(&kexec_start_address, image->start);
	mem_text_write_kernel_word(&kexec_indirection_page, page_list);
	mem_text_write_kernel_word(&kexec_mach_type, machine_arch_type);
	mem_text_write_kernel_word(&kexec_boot_atags, image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET);

#ifdef CONFIG_KEXEC_HARDBOOT
	mem_text_write_kernel_word(&kexec_hardboot, image->hardboot);
#endif

	/* copy our kernel relocation code to the control code page */
	memcpy(reboot_code_buffer,
	       relocate_new_kernel, relocate_new_kernel_size);


	flush_icache_range((unsigned long) reboot_code_buffer,
			   (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
	printk(KERN_INFO "Bye!\n");

	if (kexec_reinit)
		kexec_reinit();
	local_irq_disable();
	local_fiq_disable();
	setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
#ifdef CONFIG_KEXEC_HARDBOOT
	if (image->hardboot && kexec_hardboot_hook)
		/* Run any final machine-specific shutdown code. */
		kexec_hardboot_hook();
#endif
	flush_cache_all();
	outer_flush_all();
	outer_disable();
	cpu_proc_fin();
	outer_inv_all();
	flush_cache_all();
	__virt_to_phys(cpu_reset)(reboot_code_buffer_phys);
}
示例#28
0
int meson_enter_idle_simple(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
			int index)
{
	local_fiq_disable();
//	printk("enter wfi.\n");
	cpu_do_idle();
//	printk("exit wfi.\n");

	local_fiq_enable();

	return index;
}
示例#29
0
static void msm_pm_restart(char str, const char *cmd)
{
	int rc;
	unsigned size;

#if defined(CONFIG_MACH_ARUBASLIM_OPEN)
	unsigned int freq = 600000;

	rc = acpuclk_set_rate(0, freq, SETRATE_CPUFREQ);
	if (rc) {
		printk(KERN_ERR "%s(): failed to restore clock rate(%lu)\n",
			__func__, freq);
	}
	pr_info("%s: Current ACPU frequency %ld\n", __func__, acpuclk_get_rate(0));
#endif

	samsung_vendor1_id *smem_vendor1 = \
		(samsung_vendor1_id *)smem_get_entry(SMEM_ID_VENDOR1, &size);

	if (smem_vendor1) {
		smem_vendor1->silent_reset = 0xAEAEAEAE;
		smem_vendor1->reboot_reason = restart_reason;
        smem_vendor1->AP_reserved[0] = 0;
	} else {
		printk(KERN_EMERG "smem_flag is NULL\n");
	}

	pr_debug("The reset reason is %x\n", restart_reason);

	rc = ncp6335d_restart_config();
	if (rc)
		pr_err("Unable to configure NCP6335D for restart\n");

	/* Disable interrupts */
	local_irq_disable();
	local_fiq_disable();

	/*
	 * Take out a flat memory mapping  and will
	 * insert a 1:1 mapping in place of
	 * the user-mode pages to ensure predictable results
	 * This function takes care of flushing the caches
	 * and flushing the TLB.
	 */
	setup_mm_for_reboot();

	msm_proc_comm(PCOM_RESET_CHIP, &restart_reason, 0);

	for (;;)
		;
}
示例#30
0
static void msm_panic_restart(char mode, const char *cmd)
{
	arm_machine_flush_console();
	local_irq_disable();
	local_fiq_disable();
	flush_cache_all();
	cpu_proc_fin();
	flush_cache_all();
	msm_restart(mode, cmd);
	mdelay(1000);
	printk(KERN_ERR "Reboot failed -- System halted\n");
	while (1)
		;
}