static int nrf24_init(void) { /* CE and CSN are outputs */ pinMode(ce_pin, OUTPUT); pinMode(csn_pin, OUTPUT); nrf24_ce(0); nrf24_csn(1); nrf24_delay(); /* 2ms interval, 15 retries (16 total) */ nrf24_write_reg(SETUP_RETR, 0x7f); if (nrf24_read_reg(SETUP_RETR) != 0x7f) return 1; /* There may be no nRF24 connected */ /* Maximum Tx power, 250kbps data rate */ nrf24_write_reg(RF_SETUP, (1 << RF_PWR_LOW) | (1 << RF_PWR_HIGH) | (1 << RF_DR_LOW)); /* Dynamic payload length for TX & RX (pipes 0 and 1) */ nrf24_write_reg(DYNPD, 0x03); nrf24_write_reg(FEATURE, 1 << EN_DPL); /* Reset status bits */ nrf24_write_reg(STATUS, (1 << RX_DR) | (1 << TX_DS) | (1 << MAX_RT)); /* Set some RF channel number */ nrf24_write_reg(RF_CH, 42); /* 3-byte addresses */ nrf24_write_reg(SETUP_AW, 0x01); /* Enable ACKing on both pipe 0 & 1 for TX & RX ACK support */ nrf24_write_reg(EN_AA, 0x03); return 0; }
void nrf24_print_fifo_status() { uint8_t fifo_status = nrf24_read_reg(FIFO_STATUS); PRINT_REG(FIFO_STATUS); PRINT_REG_BIT("RX_EMPTY", fifo_status, RX_EMPTY); PRINT_REG_BIT("RX_FULL", fifo_status, RX_FULL); PRINT_REG_BIT("TX_EMPTY", fifo_status, TX_EMPTY); PRINT_REG_BIT("TX_FULL", fifo_status, TX_FULL_FIFO); }
void nrf24_print_status() { uint8_t status = nrf24_read_reg(STATUS); PRINT_REG(STATUS); PRINT_REG_BIT("TX_FULL", status, TX_FULL_STATUS); PRINT_REG_BIT("MAX_RT", status, MAX_RT); PRINT_REG_BIT("TX_DS", status, TX_DS); PRINT_REG_BIT("RX_DR", status, RX_DR); }
static uint8_t nrf24_rx_fifo_data(void) { return !(nrf24_read_reg(FIFO_STATUS) & (1 << RX_EMPTY)); }