示例#1
0
void omap4_prminst_global_cold_sw_reset(void)
{
	u32 v;
	s16 dev_inst = cpu_is_omap44xx() ? OMAP4430_PRM_DEVICE_INST :
					   OMAP54XX_PRM_DEVICE_INST;

	/* If bootloader/PPA has'nt cleared, ensure it is cleared */
	omap4_prminst_write_inst_reg(OMAP4430_GLOBAL_COLD_RST_MASK,
				     OMAP4430_PRM_PARTITION,
				     dev_inst,
				     OMAP4_RM_RSTST);

	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
					dev_inst,
					OMAP4_RM_RSTCTRL);
	v |= OMAP4430_RST_GLOBAL_COLD_SW_MASK;
	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
				     dev_inst,
				     OMAP4_RM_RSTCTRL);

	/* OCP barrier */
	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
					dev_inst,
					OMAP4_RM_RSTCTRL);

	/*
	 * Upon writing the PRM_RSTCTRL.RST_GLOBAL_COLD_SW to '1',
	 * PRCM takes 2-3 32KHz clock cycles to assert cold reset
	 * inside OMAP - approx 91.6uSec. Wait double that time.
	 */
	udelay(184);
}
示例#2
0
void omap4_prminst_global_warm_sw_reset(void)
{
    u32 v;
    s16 dev_inst;

    if (cpu_is_omap44xx())
        dev_inst = OMAP4430_PRM_DEVICE_INST;
    else if (soc_is_omap54xx())
        dev_inst = OMAP54XX_PRM_DEVICE_INST;
    else if (soc_is_dra7xx())
        dev_inst = DRA7XX_PRM_DEVICE_INST;
    else if (soc_is_am43xx())
        dev_inst = AM43XX_PRM_DEVICE_INST;
    else
        return;

    v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
                                    OMAP4_PRM_RSTCTRL_OFFSET);
    v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
    omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
                                 dev_inst,
                                 OMAP4_PRM_RSTCTRL_OFFSET);

    /* OCP barrier */
    v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
                                    dev_inst,
                                    OMAP4_PRM_RSTCTRL_OFFSET);
}
示例#3
0
/* Helper functions for MPUSS OSWR */
static inline void mpuss_clear_prev_logic_pwrst(void)
{
	u32 reg;

	reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
	omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
		OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
}
示例#4
0
/* Read-modify-write a register in PRM. Caller must lock */
u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
                                    u16 idx)
{
    u32 v;

    v = omap4_prminst_read_inst_reg(part, inst, idx);
    v &= ~mask;
    v |= bits;
    omap4_prminst_write_inst_reg(v, part, inst, idx);

    return v;
}
static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{
	omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
					OMAP4430_LASTPOWERSTATEENTERED_MASK,
					pwrdm->prcm_partition,
					pwrdm->prcm_offs, OMAP4_PM_PWSTST);

	if (pwrdm->context_offs)
		omap4_prminst_write_inst_reg(OMAP4430_LOSTCONTEXT_DFF_MASK |
					     OMAP4430_LOSTCONTEXT_RFF_MASK,
					     pwrdm->prcm_partition,
					     pwrdm->prcm_offs,
					     pwrdm->context_offs);

	return 0;
}
/**
 * omap4_device_set_next_state_off - setup device off state
 * @enable: true if off-mode should be enabled
 *
 * When Device OFF is enabled, Device is allowed to perform
 * transition to off mode as soon as all power domains in MPU, IVA
 * and CORE voltage are in OFF or OSWR state (open switch retention)
 */
static void omap4_device_set_next_state_off(bool enable)
{
	u8 val = enable ? 0x1 : 0x0;
	u16 offset, inst, partition;

	if (cpu_is_omap44xx()) {
		partition = OMAP4430_PRM_PARTITION;
		offset = OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET;
		inst = OMAP4430_PRM_DEVICE_INST;
	} else {
		return;
	}

	omap4_prminst_write_inst_reg(val << OMAP4430_DEVICE_OFF_ENABLE_SHIFT,
				     partition,
				     inst, offset);
}
示例#7
0
void omap4_prminst_global_warm_sw_reset(void)
{
    u32 v;

    v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
                                    OMAP4430_PRM_DEVICE_INST,
                                    OMAP4_PRM_RSTCTRL_OFFSET);
    v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
    omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
                                 OMAP4430_PRM_DEVICE_INST,
                                 OMAP4_PRM_RSTCTRL_OFFSET);

    /* OCP barrier */
    v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
                                    OMAP4430_PRM_DEVICE_INST,
                                    OMAP4_PRM_RSTCTRL_OFFSET);
}
示例#8
0
void omap4_prminst_global_warm_sw_reset(void)
{
	u32 v;
	s32 inst = omap4_prmst_get_prm_dev_inst();

	if (inst == PRM_INSTANCE_UNKNOWN)
		return;

	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, inst,
					OMAP4_PRM_RSTCTRL_OFFSET);
	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
				 inst, OMAP4_PRM_RSTCTRL_OFFSET);

	/* OCP barrier */
	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
				    inst, OMAP4_PRM_RSTCTRL_OFFSET);
}
示例#9
0
void omap4_prminst_global_warm_sw_reset(void)
{
	u32 v;
	s16 dev_inst = cpu_is_omap44xx() ? OMAP4430_PRM_DEVICE_INST :
					   OMAP54XX_PRM_DEVICE_INST;

	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
				    dev_inst,
				    OMAP4_PRM_RSTCTRL_OFFSET);
	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
				 dev_inst,
				 OMAP4_PRM_RSTCTRL_OFFSET);

	/* OCP barrier */
	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
				    dev_inst,
				    OMAP4_PRM_RSTCTRL_OFFSET);
}
示例#10
0
static int __init resetreason_init(void)
{
	int i;
	u32 reasons =
		omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
					    OMAP4430_PRM_DEVICE_INST,
					    OMAP4_PRM_RSTST_OFFSET);

	memset(resetreason, 0, RESET_REASON_SIZE);

	for (i = 0; i < ARRAY_SIZE(resetreason_flags); i++)
		if (reasons & resetreason_flags[i].mask)
			strlcat(resetreason, resetreason_flags[i].str,
				sizeof(resetreason));

	strlcat(resetreason, "Reset", sizeof(resetreason));

	pr_info("Last OMAP reset reason was %s (PRM_RSTST=0x%x)\n", resetreason, reasons);

	omap4_prminst_write_inst_reg(reasons, OMAP4430_PRM_PARTITION,
				     OMAP4430_PRM_DEVICE_INST, OMAP4_PRM_RSTST_OFFSET);

	return 0;
}
示例#11
0
static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
{
	omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
}