PUBLIC int ak4531_init(u16_t base, u16_t status_reg, u16_t bit,
u16_t poll) {
int i;
base_address = base;
status_register = status_reg;
status_bit = bit;
poll_address = poll;
for (i=0; i<100; i++) {
pci_inb(poll_address);
}
if(ak4531_write(RESET_AND_POWER_DOWN, PD|RST) < 0) return -1;
for (i=0; i<100; i++) {
pci_inb(poll_address);
}
ak4531_write(AD_INPUT_SELECT, 0x00);
for (i = MASTER_VOLUME_LCH ; i <= MIC_AMP_GAIN; i++) {
if (ak4531_write(i, mixer_values[i]) < 0) return -1;
}
return 0;
}
DMPAPI(void*) pci_Find(unsigned short vid, unsigned short did) {
unsigned long pciid = ((unsigned long)did << 16) + (unsigned long)vid;
unsigned long tmpid, pciaddr;
unsigned char tmpht;
int bus, dev, fun;
if (pciid == 0xffffffffUL) return NULL;
for (bus=0; bus<256; bus++)
for (dev=0; dev<32; dev++)
for (fun=0; fun<8; fun++)
{
pciaddr = PCI_GET_CF8(bus, dev, fun);
io_DisableINT();
tmpid = pci_indw(pciaddr);
io_RestoreINT();
if (tmpid == pciid) return pci_Alloc((unsigned char)bus, (unsigned char)dev, (unsigned char)fun);
if (fun == 0)
{
if (tmpid == 0xffffffffUL) break; // invalid PCI device (note: shouldn't do this optimization for Vortex86DX2's internal PCI devices)
io_DisableINT();
tmpht = pci_inb(pciaddr + 0x0eL);
io_RestoreINT();
if ((tmpht & 0x80) == 0) break; // single-function PCI device
}
} // end for (fun=...
return NULL;
}
DMPAPI(void*) pci_Find(unsigned short vid, unsigned short did) { // don't use this function in the init of io system
unsigned long pciid = ((unsigned long)did << 16) + (unsigned long)vid;
unsigned long tmpid, pciaddr;
int bus, dev, fun;
if (pciid == 0xffffffffUL) return NULL;
for (bus=0; bus<256; bus++)
for (dev=0; dev<32; dev++)
for (fun=0; fun<8; fun++)
{
pciaddr = PCI_GET_CF8(bus, dev, fun);
tmpid = pci_indw(pciaddr);
if (tmpid == pciid) return pci_Alloc((unsigned char)bus, (unsigned char)dev, (unsigned char)fun);
if (fun == 0)
{
if (tmpid == 0xffffffffUL) // invalid PCI device
{
// NOTE: shouldn't do this optimization for Vortex86DX2/DX3/EX's internal PCI devices (where fun0 may be shutdown but fun1 is still enabled)
if ((vx86_CpuID() == CPU_VORTEX86DX2) || (vx86_CpuID() == CPU_VORTEX86DX3) || (vx86_CpuID() == CPU_VORTEX86EX)) { /* do nothing ... */ } else break;
}
if ((pci_inb(pciaddr + 0x0eL) & 0x80) == 0) break; // single-function PCI device
}
} // end for (fun=...
return NULL;
}
static void write_sid(unsigned char reg, unsigned char data)
{
unsigned char cmd;
cmd = reg & 0x1f; // Write command & address
if (sid_NTSC) {
cmd |= 0x40; // Make sure its correct frequency
}
// Write data to the SID
pci_outb(data, CWbase + CW_SID_DAT);
pci_outb(cmd, CWbase + CW_SID_CMD);
// Waste 1ms
pci_inb(CWbase + CW_SID_DAT);
pci_inb(CWbase + CW_SID_DAT);
}
static unsigned char read_sid(unsigned char reg)
{
unsigned char cmd;
cmd = (reg & 0x1f) | 0x20; // Read command & address
if (sid_NTSC) {
cmd |= 0x40; // Make sure its correct frequency
}
// Write command to the SID
pci_outb(cmd, CWbase + CW_SID_CMD);
// Waste 1ms
pci_inb(CWbase + CW_SID_DAT);
pci_inb(CWbase + CW_SID_DAT);
return pci_inb(CWbase + CW_SID_DAT);
}
DMPAPI(unsigned char) pci_In8(void* handle, unsigned char offset) {
PCI_BASE_t* base = (PCI_BASE_t*)handle;
unsigned char tmp;
io_DisableINT();
tmp = pci_inb(base->addr + (unsigned long)offset);
io_RestoreINT();
return tmp;
}
/*
* Very important functionality for the JavaEngine1 computer:
* make screen border black (usign special IGA registers)
*/
static void iga_blank_border(struct fb_info_iga *info)
{
int i;
#if 0
/*
* PROM does this for us, so keep this code as a reminder
* about required read from 0x3DA and writing of 0x20 in the end.
*/
(void) pci_inb(info, 0x3DA); /* required for every access */
pci_outb(info, IGA_IDX_VGA_OVERSCAN, IGA_ATTR_CTL);
(void) pci_inb(info, IGA_ATTR_CTL+1);
pci_outb(info, 0x38, IGA_ATTR_CTL);
pci_outb(info, 0x20, IGA_ATTR_CTL); /* re-enable visual */
#endif
/*
* This does not work as it was designed because the overscan
* color is looked up in the palette. Therefore, under X11
* overscan changes color.
*/
for (i=0; i < 3; i++)
iga_outb(info, 0, IGA_EXT_CNTRL, IGA_IDX_OVERSCAN_COLOR + i);
}
static int AC97_write (const DEV_STRUCT * pCC, u16_t wAddr, u16_t wData)
{
u32_t dtemp, i;
u16_t wBaseAddr = pCC->base;
/* wait for WIP bit (Write In Progress) to go away */
/* remember, register CODEC_READ (0x14)
is a pseudo read-write register */
if (WaitBitd (wBaseAddr + CODEC_READ, 30, 0, WIP_TIMEOUT)){
printf("AC97_ERR_WIP_TIMEOUT\n");
return (AC97_ERR_WIP_TIMEOUT);
}
if (SRC_UNSYNCED != SrcSyncState)
{
/* enable SRC state data in SRC mux */
if (WaitBitd (wBaseAddr + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
/* todo: why are we writing an undefined register? */
dtemp = pci_inl(wBaseAddr + SAMPLE_RATE_CONV);
pci_outl(wBaseAddr + SAMPLE_RATE_CONV, (dtemp & SRC_CTLMASK) |
0x00010000UL);
/* wait for a SAFE time to write addr/data and then do it */
/*_disable(); */
for( i = 0; i < 0x1000UL; ++i )
if( (pci_inl(wBaseAddr + SAMPLE_RATE_CONV) & 0x00070000UL) ==
SrcSyncState )
break;
if (i >= 0x1000UL) {
/* _enable(); */
return (AC97_ERR_SRC_SYNC_TIMEOUT);
}
}
/* A test for 5880 - prime the PCI data bus */
{
u32_t dat = ((u32_t) wAddr << 16) | wData;
char page = pci_inb(wBaseAddr + MEM_PAGE);
pci_outl (wBaseAddr + MEM_PAGE, dat);
/* write addr and data */
pci_outl(wBaseAddr + CODEC_READ, dat);
pci_outb(wBaseAddr + MEM_PAGE, page); /* restore page reg */
}
if (SRC_UNSYNCED != SrcSyncState)
{
/* _enable(); */
/* restore SRC reg */
if (WaitBitd (wBaseAddr + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
pci_outl(wBaseAddr + SAMPLE_RATE_CONV, dtemp & 0xfff8ffffUL);
}
return 0;
}
static int AC97_read (const DEV_STRUCT * pCC, u16_t wAddr, u16_t *data)
{
u32_t dtemp, i;
u16_t base = pCC->base;
/* wait for WIP to go away */
if (WaitBitd (base + CODEC_READ, 30, 0, WIP_TIMEOUT))
return (AC97_ERR_WIP_TIMEOUT);
if (SRC_UNSYNCED != SrcSyncState)
{
/* enable SRC state data in SRC mux */
if (WaitBitd (base + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
dtemp = pci_inl(base + SAMPLE_RATE_CONV);
pci_outl(base + SAMPLE_RATE_CONV, (dtemp & SRC_CTLMASK) |
0x00010000UL);
/* wait for a SAFE time to write a read request and then do it */
/* todo: how do we solve the lock() problem? */
/* _disable(); */
for( i = 0; i < 0x1000UL; ++i )
if( (pci_inl(base + SAMPLE_RATE_CONV) & 0x00070000UL) ==
SrcSyncState )
break;
if (i >= 0x1000UL) {
/*_enable();*/
return (AC97_ERR_SRC_SYNC_TIMEOUT);
}
}
/* A test for 5880 - prime the PCI data bus */
{
/* set bit 23, this means read in stead of write. */
u32_t dat = ((u32_t) wAddr << 16) | (1UL << 23);
char page = pci_inb(base + MEM_PAGE);
/* todo: why are we putting data in the mem page register??? */
pci_outl(base + MEM_PAGE, dat);
/* write addr w/data=0 and assert read request */
pci_outl(base + CODEC_READ, dat);
pci_outb(base + MEM_PAGE, page); /* restore page reg */
}
if (SRC_UNSYNCED != SrcSyncState)
{
/*_enable();*/
/* restore SRC reg */
if (WaitBitd (base + SAMPLE_RATE_CONV, SRC_BUSY_BIT, 0, 1000))
return (AC97_ERR_SRC_NOT_BUSY_TIMEOUT);
pci_outl(base + SAMPLE_RATE_CONV, dtemp & 0xfff8ffffUL);
}
/* now wait for the stinkin' data (DRDY = data ready) */
if (WaitBitd (base + CODEC_READ, 31, 1, DRDY_TIMEOUT))
return (AC97_ERR_DATA_TIMEOUT);
dtemp = pci_inl(base + CODEC_READ);
if (data)
*data = (u16_t) dtemp;
return 0;
}
UBYTE ahi_pci_inb(ULONG addr, APTR dev)
{
return pci_inb(addr);
}
DMPAPI(unsigned char) pci_In8(void* handle, unsigned char offset) {
PCI_BASE_t* base = (PCI_BASE_t*)handle;
return pci_inb(base->addr + (unsigned long)offset);
}
static unsigned int driver_match(unsigned int id)
{
return pci_inb(id, PCI_CONFIG_CLASS) == PCI_CLASS_DISPLAY && pci_inb(id, PCI_CONFIG_SUBCLASS) == PCI_CLASS_DISPLAY_VGA && pci_inb(id, PCI_CONFIG_INTERFACE) == 0x00;
}
static inline unsigned int iga_inb(struct fb_info_iga *info,
unsigned int reg, unsigned int idx )
{
pci_outb(info, idx, reg);
return pci_inb(info, reg + 1);
}