static int gpu_pm_qos_command(struct exynos_context *platform, gpu_pmqos_state state) { #ifdef CONFIG_BUS_DEVFREQ switch (state) { case GPU_CONTROL_PM_QOS_INIT: pm_qos_add_request(&exynos5_g3d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0); pm_qos_add_request(&exynos5_g3d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0); pm_qos_add_request(&exynos5_g3d_cpu_qos, PM_QOS_KFC_FREQ_MIN, 0); break; case GPU_CONTROL_PM_QOS_DEINIT: pm_qos_remove_request(&exynos5_g3d_mif_qos); pm_qos_remove_request(&exynos5_g3d_int_qos); pm_qos_remove_request(&exynos5_g3d_cpu_qos); break; case GPU_CONTROL_PM_QOS_SET: if (platform->step < 0) return -1; pm_qos_update_request(&exynos5_g3d_mif_qos, platform->table[platform->step].mem_freq); pm_qos_update_request(&exynos5_g3d_int_qos, platform->table[platform->step].int_freq); pm_qos_update_request(&exynos5_g3d_cpu_qos, platform->table[platform->step].cpu_freq); break; case GPU_CONTROL_PM_QOS_RESET: pm_qos_update_request(&exynos5_g3d_mif_qos, 0); pm_qos_update_request(&exynos5_g3d_int_qos, 0); pm_qos_update_request(&exynos5_g3d_cpu_qos, 0); default: break; } #endif /* CONFIG_BUS_DEVFREQ */ return 0; }
int proactive_pm_qos_command(struct exynos_context *platform, gpu_pmqos_state state) { DVFS_ASSERT(platform); if (!platform->devfreq_status) return 0; switch (state) { case GPU_CONTROL_PM_QOS_INIT: pm_qos_add_request(&proactive_mif_min_qos, PM_QOS_BUS_THROUGHPUT, 0); pm_qos_add_request(&proactive_apollo_min_qos, PM_QOS_CLUSTER0_FREQ_MIN, 0); pm_qos_add_request(&proactive_atlas_min_qos, PM_QOS_CLUSTER1_FREQ_MIN, 0); if (!platform->pmqos_int_disable) pm_qos_add_request(&proactive_int_min_qos, PM_QOS_DEVICE_THROUGHPUT, 0); break; case GPU_CONTROL_PM_QOS_DEINIT: pm_qos_remove_request(&proactive_mif_min_qos); pm_qos_remove_request(&proactive_apollo_min_qos); pm_qos_remove_request(&proactive_atlas_min_qos); if (!platform->pmqos_int_disable) pm_qos_remove_request(&proactive_int_min_qos); break; case GPU_CONTROL_PM_QOS_RESET: pm_qos_update_request(&proactive_mif_min_qos, 0); pm_qos_update_request(&proactive_apollo_min_qos, 0); pm_qos_update_request(&proactive_atlas_min_qos, 0); default: break; } return 0; }
static void gpio_key_set_dvfs_lock(struct gpio_button_data *bdata, uint32_t on) { mutex_lock(&bdata->key_dvfs_lock); if (on == 0) { if (bdata->key_dvfs_lock_status) { schedule_delayed_work(&bdata->key_work_dvfs_off, msecs_to_jiffies(TOUCH_BOOSTER_OFF_TIME)); } } else if (on == 1) { cancel_delayed_work(&bdata->key_work_dvfs_off); if (!bdata->key_dvfs_lock_status) { pm_qos_add_request(&bdata->key_cpu_qos, PM_QOS_CPU_FREQ_MIN, 600000); /* CPU KFC 1.2GHz */ pm_qos_add_request(&bdata->key_mif_qos, PM_QOS_BUS_THROUGHPUT, 800000); /* MIF 800MHz */ pm_qos_add_request(&bdata->key_int_qos, PM_QOS_DEVICE_THROUGHPUT, 200000); /* INT 200MHz */ schedule_delayed_work(&bdata->key_work_dvfs_chg, msecs_to_jiffies(TOUCH_BOOSTER_CHG_TIME)); bdata->key_dvfs_lock_status = true; printk(KERN_DEBUG "[key] DVFS On\n"); } } else if (on == 2) { if (bdata->key_dvfs_lock_status) { cancel_delayed_work(&bdata->key_work_dvfs_off); cancel_delayed_work(&bdata->key_work_dvfs_chg); schedule_work(&bdata->key_work_dvfs_off.work); } } mutex_unlock(&bdata->key_dvfs_lock); }
static void rmnet_usb_freq_request(void) { pr_info("%s\n", __func__); if ( rmnet_usb_wq == NULL ) { rmnet_usb_wq = create_singlethread_workqueue("rmnet_usb_freq"); pr_info("%s: create_singlethread_workqueue=[0x%p]\n", __func__, rmnet_usb_wq); } if ( rmnet_usb_freq_enable_work_init == 0 ) { INIT_DELAYED_WORK(&rmnet_usb_freq_enable_work, rmnet_usb_freq_enable_work_func); pr_info("%s: INIT_WORK: rmnet_usb_freq_enable_work\n", __func__); rmnet_usb_freq_enable_work_init = 1; } if ( rmnet_usb_freq_disable_work_init == 0 ) { INIT_DELAYED_WORK(&rmnet_usb_freq_disable_work, rmnet_usb_freq_disable_work_func); rmnet_usb_freq_disable_work_init = 1; } if ( rmnet_usb_req_freq_active == 0 ) { pr_info("%s: pm_qos_add_request: freq", __func__); pm_qos_add_request(&rmnet_usb_req_freq, PM_QOS_CPU_FREQ_MIN, (s32)PM_QOS_CPU_FREQ_MIN_DEFAULT_VALUE); rmnet_usb_req_freq_active = 1; } if ( rmnet_usb_req_cpus_active == 0 ) { pr_info("%s: pm_qos_add_request: cpus", __func__); pm_qos_add_request(&rmnet_usb_req_cpus, PM_QOS_MIN_ONLINE_CPUS, (s32)PM_QOS_MIN_ONLINE_CPUS_DEFAULT_VALUE); rmnet_usb_req_cpus_active = 1; } }
/* acipc_init is used to register interrupt call-back function */ int acipc_init(u32 lpm_qos) { wakeup_source_init(&acipc_wakeup, "acipc_wakeup"); /* we do not check any return value */ acipc_event_bind(ACIPC_MODEM_DDR_UPDATE_REQ, acipc_cb_event_notify, ACIPC_CB_NORMAL, NULL); acipc_event_bind(ACIPC_IPM, acipc_cb_block_cpuidle_axi, ACIPC_CB_NORMAL, NULL); pm_qos_cpuidle_block_axi = lpm_qos; pm_qos_add_request(&cp_block_cpuidle_axi, PM_QOS_CPUIDLE_BLOCK, PM_QOS_CPUIDLE_BLOCK_DEFAULT_VALUE); #ifdef CONFIG_DDR_DEVFREQ pm_qos_add_request(&modem_ddr_cons, PM_QOS_DDR_DEVFREQ_MIN, PM_QOS_DEFAULT_VALUE); INIT_WORK(&acipc_modem_ddr_freq_update, acipc_modem_ddr_freq_update_handler); acipc_wq = alloc_workqueue("ACIPC_WQ", WQ_HIGHPRI, 0); #endif return 0; }
void fimg2d_pm_qos_add(struct fimg2d_control *ctrl) { #if defined(CONFIG_ARM_EXYNOS_IKS_CPUFREQ) || \ defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) || \ defined(CONFIG_FIMG2D_USE_BUS_DEVFREQ) struct fimg2d_platdata *pdata; #ifdef CONFIG_OF pdata = ctrl->pdata; #else pdata = to_fimg2d_plat(ctrl->dev); #endif #endif #if defined CONFIG_ARM_EXYNOS_IKS_CPUFREQ pm_qos_add_request(&ctrl->exynos5_g2d_cpu_qos, PM_QOS_CPU_FREQ_MIN, 0); #elif defined CONFIG_ARM_EXYNOS_MP_CPUFREQ pm_qos_add_request(&ctrl->exynos5_g2d_cpu_qos, PM_QOS_CPU_FREQ_MIN, 0); pm_qos_add_request(&ctrl->exynos5_g2d_kfc_qos, PM_QOS_KFC_FREQ_MIN, 0); #endif #ifdef CONFIG_FIMG2D_USE_BUS_DEVFREQ pm_qos_add_request(&ctrl->exynos5_g2d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0); pm_qos_add_request(&ctrl->exynos5_g2d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0); #endif }
void fimg2d_pm_qos_add_bus(struct fimg2d_control *ctrl) { pm_qos_add_request(&ctrl->exynos5_g2d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0); pm_qos_add_request(&ctrl->exynos5_g2d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0); }
static int __init modem_kfc_qos_init(void) { pm_qos_add_request(&dl_kfc_num_qos, PM_QOS_KFC_NUM_MIN, 0); pm_qos_add_request(&dl_kfc_freq_qos, PM_QOS_KFC_FREQ_MIN, 0); return 0; }
int pwrctrl_dfs_init(void) { void __iomem *reg_addr; struct acpufreqinfo *p_freqinfo; reg_addr = (void __iomem *)HISI_VA_ADDRESS(SOC_PERI_SCTRL_SC_RESERVED8_ADDR(SOC_PERI_SCTRL_BASE_ADDR)); g_dfs_data_addr = ioremap(ACPU_DFS_FREQ_ADDR, ACPU_DFS_FREQ_ADDR_SIZE); p_freqinfo = (struct acpufreqinfo *)g_dfs_data_addr; p_freqinfo->dfs_flag = 0; p_freqinfo->dfs_acpu_freq = 0; p_freqinfo->dfs_temp_freq = 0; g_stPwcSwitch = (ST_PWC_SWITCH_STRU *)(reg_addr); dt_insmod_buslow(); dt_insmod_bus_dfs(); if(!dt_insmod_dvfs()){g_adfs_module = 1;} wake_lock_init(&acpu_freq_lock,WAKE_LOCK_SUSPEND,"acpu_freq_lock"); ddr_min_req.pm_qos_class = 0; ddr_max_req.pm_qos_class = 0; pm_qos_add_request(&ddr_min_req, DFS_QOS_ID_DDR_MINFREQ, QOS_DDR_MIN_DEFAULT_VALUE + 2); pm_qos_add_request(&ddr_max_req, DFS_QOS_ID_DDR_MAXFREQ, QOS_DDR_MAX_DEFAULT_VALUE - 2); return RET_OK; }
static int __init tegra_auto_hotplug_debug_init(void) { if (!tegra3_cpu_lock) return -ENOENT; hp_debugfs_root = debugfs_create_dir("tegra_hotplug", NULL); if (!hp_debugfs_root) return -ENOMEM; pm_qos_add_request(&min_cpu_req, PM_QOS_MIN_ONLINE_CPUS, PM_QOS_DEFAULT_VALUE); pm_qos_add_request(&max_cpu_req, PM_QOS_MAX_ONLINE_CPUS, PM_QOS_DEFAULT_VALUE); if (!debugfs_create_file( "min_cpus", S_IRUGO, hp_debugfs_root, NULL, &min_cpus_fops)) goto err_out; if (!debugfs_create_file( "max_cpus", S_IRUGO, hp_debugfs_root, NULL, &max_cpus_fops)) goto err_out; if (!debugfs_create_file( "stats", S_IRUGO, hp_debugfs_root, NULL, &hp_stats_fops)) goto err_out; return 0; err_out: debugfs_remove_recursive(hp_debugfs_root); pm_qos_remove_request(&min_cpu_req); pm_qos_remove_request(&max_cpu_req); return -ENOMEM; }
static int exynos5_devfreq_isp_qos_init(void) { pm_qos_add_request(&exynos5_isp_qos, PM_QOS_CAM_THROUGHPUT, exynos5433_qos_isp.default_qos); pm_qos_add_request(&min_isp_thermal_qos, PM_QOS_CAM_THROUGHPUT, exynos5433_qos_isp.default_qos); pm_qos_add_request(&boot_isp_qos, PM_QOS_CAM_THROUGHPUT, exynos5433_qos_isp.default_qos); return 0; }
static int __init exynos7_devfreq_disp_qos_init(void) { pm_qos_add_request(&exynos7_disp_qos, PM_QOS_DISPLAY_THROUGHPUT, exynos7420_qos_disp.default_qos); pm_qos_add_request(&min_disp_thermal_qos, PM_QOS_DISPLAY_THROUGHPUT, exynos7420_qos_disp.default_qos); pm_qos_add_request(&boot_disp_qos, PM_QOS_DISPLAY_THROUGHPUT, exynos7420_qos_disp.default_qos); pm_qos_update_request_timeout(&exynos7_disp_qos, exynos7_devfreq_disp_profile.initial_freq, 40000 * 1000); return 0; }
static int gpu_pm_qos_command(struct exynos_context *platform, gpu_pmqos_state state) { #ifdef CONFIG_BUS_DEVFREQ switch (state) { case GPU_CONTROL_PM_QOS_INIT: pm_qos_add_request(&exynos5_g3d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0); pm_qos_add_request(&exynos5_g3d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0); pm_qos_add_request(&exynos5_g3d_cpu_kfc_min_qos, PM_QOS_KFC_FREQ_MIN, 0); pm_qos_add_request(&exynos5_g3d_cpu_egl_max_qos, PM_QOS_CPU_FREQ_MAX, PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE); #if SLSI_INTEGRATION #if defined(SET_MINLOCK) pm_qos_add_request(&exynos5_g3d_cpu_egl_min_qos, PM_QOS_CPU_FREQ_MIN, 0); platform->custom_cpu_max_lock = 0; #endif #endif break; case GPU_CONTROL_PM_QOS_DEINIT: pm_qos_remove_request(&exynos5_g3d_mif_qos); pm_qos_remove_request(&exynos5_g3d_int_qos); pm_qos_remove_request(&exynos5_g3d_cpu_kfc_min_qos); pm_qos_remove_request(&exynos5_g3d_cpu_egl_max_qos); #if SLSI_INTEGRATION #if defined(SET_MINLOCK) pm_qos_remove_request(&exynos5_g3d_cpu_egl_min_qos); #endif #endif break; case GPU_CONTROL_PM_QOS_SET: if (platform->step < 0) return -1; pm_qos_update_request(&exynos5_g3d_mif_qos, platform->table[platform->step].mem_freq); pm_qos_update_request(&exynos5_g3d_int_qos, platform->table[platform->step].int_freq); pm_qos_update_request(&exynos5_g3d_cpu_kfc_min_qos, platform->table[platform->step].cpu_freq); #if SLSI_INTEGRATION #if defined(SET_MINLOCK) if (platform->custom_cpu_max_lock) pm_qos_update_request(&exynos5_g3d_cpu_egl_max_qos, platform->custom_cpu_max_lock); else #endif #endif pm_qos_update_request(&exynos5_g3d_cpu_egl_max_qos, platform->table[platform->step].cpu_max_freq); break; case GPU_CONTROL_PM_QOS_RESET: pm_qos_update_request(&exynos5_g3d_mif_qos, 0); pm_qos_update_request(&exynos5_g3d_int_qos, 0); pm_qos_update_request(&exynos5_g3d_cpu_kfc_min_qos, 0); pm_qos_update_request(&exynos5_g3d_cpu_egl_max_qos, PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE); default: break; } #endif /* CONFIG_BUS_DEVFREQ */ return 0; }
static int __init exynos5_devfreq_int_qos_init(void) { pm_qos_add_request(&exynos5_int_qos, PM_QOS_DEVICE_THROUGHPUT, exynos5433_qos_int.default_qos); pm_qos_add_request(&min_int_thermal_qos, PM_QOS_DEVICE_THROUGHPUT, exynos5433_qos_int.default_qos); pm_qos_add_request(&boot_int_qos, PM_QOS_DEVICE_THROUGHPUT, exynos5433_qos_int.default_qos); pm_qos_add_request(&exynos5_int_bts_qos, PM_QOS_DEVICE_THROUGHPUT, exynos5433_qos_int.default_qos); pm_qos_update_request_timeout(&exynos5_int_qos, exynos5_devfreq_int_profile.initial_freq, 40000 * 1000); return 0; }
static int simple_dip_probe(struct platform_device *dev) { int ret = 0; wake_lock_init(&dip_wakelock, WAKE_LOCK_SUSPEND, "dip_wakeups"); dip_info = kzalloc(sizeof(struct dip_info), GFP_KERNEL); if (!dip_info) return -ENOMEM; dip_info->misc_dev.minor = MISCDEV_MINOR; dip_info->misc_dev.name = DRV_NAME; dip_info->misc_dev.fops = &simple_dip_fops; dip_info->comp_info_array.comp_info = comp_info_temp; dip_info->cpu = clk_get(NULL, CLK_CPU); if (IS_ERR(dip_info->cpu)) { pr_err("cannot get clk(cpu)\n"); goto err_free_dip; } dip_info->cpu_min_qos.name = "dip_cpu_min"; pm_qos_add_request(&dip_info->cpu_min_qos, PM_QOS_CPUFREQ_MIN, PM_QOS_DEFAULT_VALUE); dip_info->cpu_max_qos.name = "dip_cpu_max"; pm_qos_add_request(&dip_info->cpu_max_qos, PM_QOS_CPUFREQ_MAX, INT_MAX); dip_info->ddr = clk_get(NULL, CLK_DDR); if (IS_ERR(dip_info->ddr)) { pr_err("cannot get clk(ddr)\n"); goto err_free_dip; } dip_info->ddr_min_qos.name = "dip_ddr_min"; pm_qos_add_request(&dip_info->ddr_min_qos, PM_QOS_DDR_DEVFREQ_MIN, PM_QOS_DEFAULT_VALUE); dip_info->ddr_max_qos.name = "dip_ddr_max"; pm_qos_add_request(&dip_info->ddr_max_qos, PM_QOS_DDR_DEVFREQ_MAX, INT_MAX); /* register misc device */ ret = misc_register(&dip_info->misc_dev); if (ret < 0) { dev_err(&dev->dev, "misc_register() for minor %d failed\n", MISCDEV_MINOR); goto err_free_dip; } platform_set_drvdata(dev, dip_info); return 0; err_free_dip: platform_set_drvdata(dev, NULL); kfree(dip_info); return ret; }
/** * sr_class1p5_init() - class 1p5 init * @voltdm: sr voltage domain * @voltdm_cdata: voltage domain specific private class data * allocated by class init with work item data * freed by deinit. * @class_priv_data: private data for the class (unused) * * we do class specific initialization like creating sysfs/debugfs entries * needed, spawning of a kthread if needed etc. */ static int sr_class1p5_init(struct voltagedomain *voltdm, void **voltdm_cdata, void *class_priv_data) { struct sr_class1p5_work_data *work_data; if (IS_ERR_OR_NULL(voltdm) || IS_ERR_OR_NULL(voltdm_cdata)) { pr_err("%s: bad parameters!\n", __func__); return -EINVAL; } if (!IS_ERR_OR_NULL(*voltdm_cdata)) { pr_err("%s: ooopps.. class already initialized for %s! bug??\n", __func__, voltdm->name); return -EINVAL; } /* setup our work params */ work_data = kzalloc(sizeof(struct sr_class1p5_work_data), GFP_KERNEL); if (!work_data) { pr_err("%s: no memory to allocate work data on domain %s\n", __func__, voltdm->name); return -ENOMEM; } work_data->voltdm = voltdm; INIT_DELAYED_WORK_DEFERRABLE(&work_data->work, sr_class1p5_calib_work); *voltdm_cdata = (void *)work_data; pm_qos_add_request(&work_data->qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); return 0; }
static int omap_mcpdm_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai); struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req; int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE; int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK; int latency = mcpdm->latency[stream2]; /* Prevent omap hardware from hitting off between FIFO fills */ if (!latency || mcpdm->latency[stream1] < latency) latency = mcpdm->latency[stream1]; if (pm_qos_request_active(pm_qos_req)) pm_qos_update_request(pm_qos_req, latency); else if (latency) pm_qos_add_request(pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency); if (!omap_mcpdm_active(mcpdm)) { omap_mcpdm_start(mcpdm); omap_mcpdm_reg_dump(mcpdm); } else if (mcpdm->restart) { omap_mcpdm_stop(mcpdm); omap_mcpdm_start(mcpdm); mcpdm->restart = false; omap_mcpdm_reg_dump(mcpdm); } return 0; }
/* Wrappers for obsolete legacy kernel hack (busfreq_lock/lock_free) */ int exynos4_busfreq_lock(unsigned int nId, enum busfreq_level_request lvl) { s32 qos_value; if (WARN(nId >= DVFS_LOCK_ID_END, "incorrect nId.")) return -EINVAL; if (WARN(lvl >= BUS_LEVEL_END, "incorrect level.")) return -EINVAL; switch (lvl) { case BUS_L0: qos_value = 400000; break; case BUS_L1: qos_value = 267000; break; case BUS_L2: qos_value = 133000; break; default: qos_value = 0; } if (qos_wrapper[nId].pm_qos_class == 0) { pm_qos_add_request(&qos_wrapper[nId], PM_QOS_BUS_QOS, qos_value); } else { pm_qos_update_request(&qos_wrapper[nId], qos_value); } return 0; }
static int msm_v4l2_open(struct file *filp) { struct video_device *vdev = video_devdata(filp); struct msm_video_device *vid_dev = container_of(vdev, struct msm_video_device, vdev); struct msm_vidc_core *core = video_drvdata(filp); struct msm_vidc_inst *vidc_inst; trace_msm_v4l2_vidc_open_start("msm_v4l2_open start"); vidc_inst = msm_vidc_open(core->id, vid_dev->type); if (!vidc_inst) { dprintk(VIDC_ERR, "Failed to create video instance, core: %d, type = %d\n", core->id, vid_dev->type); return -ENOMEM; } #ifdef CONFIG_LGE_UNDERRUN dprintk(VIDC_ERR, "msm_vidc: pm_qos_add_request, 1000uSec\n"); pm_qos_add_request(&msm_v4l2_vidc_pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1000); #endif clear_bit(V4L2_FL_USES_V4L2_FH, &vdev->flags); filp->private_data = &(vidc_inst->event_handler); trace_msm_v4l2_vidc_open_end("msm_v4l2_open end"); return 0; }
static int msm_v4l2_open(struct file *filp) { struct video_device *vdev = video_devdata(filp); struct msm_video_device *vid_dev = container_of(vdev, struct msm_video_device, vdev); struct msm_vidc_core *core = video_drvdata(filp); struct msm_vidc_inst *vidc_inst; vidc_inst = msm_vidc_open(core->id, vid_dev->type); if (!vidc_inst) { dprintk(VIDC_ERR, "Failed to create video instance, core: %d, type = %d\n", core->id, vid_dev->type); return -ENOMEM; } if (!pm_qos_request_active(&vidc_inst->pm_qos)) { dprintk(VIDC_DBG, "pm_qos_add with latency 332usec\n"); pm_qos_add_request(&vidc_inst->pm_qos, PM_QOS_CPU_DMA_LATENCY, 332); } clear_bit(V4L2_FL_USES_V4L2_FH, &vdev->flags); filp->private_data = &(vidc_inst->event_handler); return 0; }
static int __init tovis_qvga_probe(struct platform_device *pdev) { int ret; int readport; if (pdev->id == 0) { tovis_qvga_panel_pdata = pdev->dev.platform_data; return 0; } msm_fb_add_device(pdev); ret = device_create_file(&pdev->dev, &dev_attr_lcd_onoff); if (ret) { printk("tovis_qvga_probe device_creat_file failed!!!\n"); } gpio_tlmm_config(GPIO_CFG(GPIO_LCD_TID, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE); readport = gpio_get_value(GPIO_LCD_TID); printk("Read GPIO LCD port %d \n", readport); #ifndef CONFIG_ARCH_MSM7X27A tovis_pm_qos_req = pm_qos_add_request(PM_QOS_SYSTEM_BUS_FREQ, PM_QOS_DEFAULT_VALUE); #endif return 0; }
static inline void pm_qos_update_max(int frequency) { if (pm_qos_request_active(&max_cpu_qos_hotplug)) pm_qos_update_request(&max_cpu_qos_hotplug, frequency); else pm_qos_add_request(&max_cpu_qos_hotplug, PM_QOS_CPU_FREQ_MAX, frequency); }
static int __init cpufreq_pmqos_init(void) { int rc; rc = sysfs_create_group(cpufreq_global_kobject, &pmqos_attr_group); if (rc) { pr_err("%s create sysfs error rc=%d\n", __FUNCTION__, rc); return rc; } bimc_wq = alloc_workqueue("bimc_wq", WQ_HIGHPRI, 0); if (!bimc_wq) { printk(KERN_ERR "Failed to create bimc_wq workqueue\n"); return -EFAULT; } INIT_DELAYED_WORK(&bimc_fastboot_work, bimc_boot_completed); /* mif max freq for fast booting */ if (!pm_qos_request_active(&bimc_min_qos)) { pm_qos_add_request(&bimc_min_qos , PM_QOS_BIMC_FREQ_MIN, BIMC_BOOT_VALUE); } else pm_qos_update_request(&bimc_min_qos, BIMC_BOOT_VALUE); msm_set_pmqos_bimc_min_freq(); queue_delayed_work(bimc_wq, &bimc_fastboot_work , (BIMC_BOOTING_TIME)*HZ); return rc; }
int i2c_dw_probe_lock_support(struct dw_i2c_dev *dev) { acpi_status status; unsigned long long shared_host = 0; acpi_handle handle; if (!dev || !dev->dev) return 0; handle = ACPI_HANDLE(dev->dev); if (!handle) return 0; status = acpi_evaluate_integer(handle, "_SEM", NULL, &shared_host); if (ACPI_FAILURE(status)) return 0; if (!shared_host) return 0; if (!iosf_mbi_available()) return -EPROBE_DEFER; dev_info(dev->dev, "I2C bus managed by PUNIT\n"); dev->acquire_lock = baytrail_i2c_acquire; dev->release_lock = baytrail_i2c_release; dev->pm_disabled = true; pm_qos_add_request(&dev->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); return 0; }
static void usb_load(struct work_struct *work) { int cpu; unsigned int num_irqs = 0; static unsigned int old_num_irqs = UINT_MAX; for_each_online_cpu(cpu) num_irqs += kstat_irqs_cpu(IRQ_DB8500_USBOTG, cpu); if ((num_irqs > old_num_irqs) && (num_irqs - old_num_irqs) > USB_LIMIT) { prcmu_qos_update_requirement(PRCMU_QOS_ARM_OPP, "usb", 125); if (!usb_pm_qos_is_latency_0) { usb_pm_qos_latency = pm_qos_add_request(PM_QOS_CPU_DMA_LATENCY, 0); usb_pm_qos_is_latency_0 = true; } } else { prcmu_qos_update_requirement(PRCMU_QOS_ARM_OPP, "usb", 25); if (usb_pm_qos_is_latency_0) { pm_qos_remove_request(usb_pm_qos_latency); usb_pm_qos_is_latency_0 = false; } } old_num_irqs = num_irqs; schedule_delayed_work_on(0, &work_usb_workaround, msecs_to_jiffies(USB_PROBE_DELAY)); }
static int __init snd_omap_mcbsp_init(void) { #ifdef C_OPP_PATCH pm_qos_add_request(&pm_qos_handle, PM_QOS_CPU_DMA_LATENCY, CLEAR_MPU_CORE_CONSTRAINT); #endif return platform_driver_register(&asoc_mcbsp_driver); }
static int __init snddev_icodec_init(void) { s32 rc; struct snddev_icodec_drv_state *icodec_drv = &snddev_icodec_drv; rc = platform_driver_register(&snddev_icodec_driver); if (IS_ERR_VALUE(rc)) { pr_err("%s: platform_driver_register for snddev icodec failed\n", __func__); goto error_snddev_icodec_driver; } rc = platform_driver_register(&msm_cdcclk_ctl_driver); if (IS_ERR_VALUE(rc)) { pr_err("%s: platform_driver_register for msm snddev failed\n", __func__); goto error_msm_cdcclk_ctl_driver; } rc = platform_driver_register(&msm_icodec_gpio_driver); if (IS_ERR_VALUE(rc)) { pr_err("%s: platform_driver_register for msm snddev gpio failed\n", __func__); goto error_msm_icodec_gpio_driver; } mutex_init(&icodec_drv->rx_lock); mutex_init(&icodec_drv->lb_lock); mutex_init(&icodec_drv->tx_lock); icodec_drv->rx_active = 0; icodec_drv->tx_active = 0; icodec_drv->snddev_vreg = vreg_init(); pm_qos_add_request(&icodec_drv->tx_pm_qos_req, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); pm_qos_add_request(&icodec_drv->rx_pm_qos_req, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); return 0; error_msm_icodec_gpio_driver: platform_driver_unregister(&msm_cdcclk_ctl_driver); error_msm_cdcclk_ctl_driver: platform_driver_unregister(&snddev_icodec_driver); error_snddev_icodec_driver: return -ENODEV; }
static void wlan_load(struct work_struct *work) { int cpu; unsigned int num_irqs = 0; static unsigned int old_num_irqs = UINT_MAX; for_each_online_cpu(cpu) num_irqs += kstat_irqs_cpu(IRQ_DB8500_SDMMC1, cpu); if ((num_irqs > old_num_irqs) && (num_irqs - old_num_irqs) > wlan_limit) { if (wlan_arm_khz) prcmu_qos_update_requirement(PRCMU_QOS_ARM_KHZ, "wlan", wlan_arm_khz); prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP, "wlan", PRCMU_QOS_MAX_VALUE); prcmu_qos_update_requirement(PRCMU_QOS_DDR_OPP, "wlan", PRCMU_QOS_MAX_VALUE); if (!wlan_pm_qos_is_latency_0) { /* * The wake up latency is set to 0 to prevent * the system from going to sleep. This improves * the wlan throughput in DMA mode. * The wake up latency from sleep adds ~5% overhead * for TX in some cases. * This change doesn't increase performance for wlan * PIO since the CPU usage prevents sleep in this mode. */ pm_qos_add_request(&wlan_pm_qos_latency, PM_QOS_CPU_DMA_LATENCY, 0); wlan_pm_qos_is_latency_0 = true; } } else { prcmu_qos_update_requirement(PRCMU_QOS_ARM_KHZ, "wlan", PRCMU_QOS_DEFAULT_VALUE); prcmu_qos_update_requirement(PRCMU_QOS_APE_OPP, "wlan", PRCMU_QOS_DEFAULT_VALUE); prcmu_qos_update_requirement(PRCMU_QOS_DDR_OPP, "wlan", PRCMU_QOS_DEFAULT_VALUE); if (wlan_pm_qos_is_latency_0) { pm_qos_remove_request(&wlan_pm_qos_latency); wlan_pm_qos_is_latency_0 = false; } } old_num_irqs = num_irqs; schedule_delayed_work_on(0, &work_wlan_workaround, msecs_to_jiffies(wlan_probe_delay)); }
void fimg2d_pm_qos_add(struct fimg2d_control *ctrl) { struct fimg2d_platdata *pdata = to_fimg2d_plat(ctrl->dev); #ifdef CONFIG_ARM_EXYNOS_IKS_CPUFREQ if (pdata->cpu_min) pm_qos_add_request(&ctrl->exynos5_g2d_cpu_qos, PM_QOS_CPU_FREQ_MIN, 0); #endif #ifdef CONFIG_FIMG2D_USE_BUS_DEVFREQ if (pdata->mif_min) pm_qos_add_request(&ctrl->exynos5_g2d_mif_qos, PM_QOS_BUS_THROUGHPUT, 0); if (pdata->int_min) pm_qos_add_request(&ctrl->exynos5_g2d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0); #endif }
static int __init pm_init(void) { int error = pm_start_workqueue(); #ifdef CONFIG_PERFLOCK #ifdef CONFIG_SHSYS_CUST_PERFLOCK #ifdef CONFIG_SHSYS_CUST_USER_PERFLOCK int i; static char perflock_name[PERF_LOCK_INVALID][25]; static char limitlock_name[PERF_LOCK_INVALID][26]; #endif #else int i; char buf[38]; #endif #endif if (error) return error; hibernate_image_size_init(); hibernate_reserved_size_init(); touch_evt_timer_val = ktime_set(2, 0); hrtimer_init(&tc_ev_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); tc_ev_timer.function = &tc_ev_stop; tc_ev_processed = 1; #ifdef CONFIG_PERFLOCK #ifdef CONFIG_SHSYS_CUST_PERFLOCK #ifdef CONFIG_SHSYS_CUST_USER_PERFLOCK pm_qos_add_request(&user_perf_lock_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); for (i = 0; i < PERF_LOCK_INVALID; i++) { snprintf(perflock_name[i], 24, "User Perflock level(%d)", i); perflock_name[i][24] = '\0'; perf_lock_init(&user_perf_lock[i], i, perflock_name[i]); snprintf(limitlock_name[i], 25, "User Limitlock level(%d)", i); limitlock_name[i][25] = '\0'; limit_lock_init(&user_limit_lock[i], i, limitlock_name[i]); } #endif #else perf_lock_init(&user_perf_lock, PERF_LOCK_HIGHEST, "User Perflock"); for (i = 0; i < CEILING_LEVEL_INVALID; i++) { snprintf(buf, 37, "User cpufreq_ceiling lock level(%d)", i); buf[37] = '\0'; perf_lock_init_v2(&user_cpufreq_ceiling[i], i, buf); } #endif #endif power_kobj = kobject_create_and_add("power", NULL); if (!power_kobj) return -ENOMEM; error = sysfs_create_group(power_kobj, &attr_group); if (error) return error; return pm_autosleep_init(); }