static void i386_linux_dr_set (ptid_t ptid, int regnum, unsigned long value) { int tid; tid = ptid_get_lwp (ptid); if (tid == 0) tid = ptid_get_pid (ptid); errno = 0; ptrace (PTRACE_POKEUSER, tid, offsetof (struct user, u_debugreg[regnum]), value); if (errno != 0) perror_with_name (_("Couldn't write debug register")); }
static LONGEST get_core_siginfo (bfd *abfd, gdb_byte *readbuf, ULONGEST offset, LONGEST len) { asection *section; long pid; char *section_name; const char *name = ".note.linuxcore.siginfo"; if (ptid_get_lwp (inferior_ptid)) section_name = xstrprintf ("%s/%ld", name, ptid_get_lwp (inferior_ptid)); else section_name = xstrdup (name); section = bfd_get_section_by_name (abfd, section_name); xfree (section_name); if (section == NULL) return -1; if (!bfd_get_section_contents (abfd, section, readbuf, offset, len)) return -1; return len; }
static void fetch_xtregs (struct regcache *regcache, int regnum) { int tid = ptid_get_lwp (inferior_ptid); const xtensa_regtable_t *ptr; char xtregs [XTENSA_ELF_XTREG_SIZE]; if (ptrace (PTRACE_GETXTREGS, tid, 0, (long)&xtregs) < 0) perror_with_name (_("Couldn't get extended registers")); for (ptr = xtensa_regmap_table; ptr->name; ptr++) if (regnum == ptr->gdb_regnum || regnum == -1) regcache_raw_supply (regcache, ptr->gdb_regnum, xtregs + ptr->ptrace_offset); }
static void shnbsd_store_inferior_registers (struct target_ops *ops, struct regcache *regcache, int regno) { if (regno == -1 || GETREGS_SUPPLIES (get_regcache_arch (regcache), regno)) { struct reg inferior_registers; if (ptrace (PT_GETREGS, ptid_get_pid (inferior_ptid), (PTRACE_TYPE_ARG3) &inferior_registers, ptid_get_lwp (inferior_ptid)) == -1) perror_with_name (_("Couldn't get registers")); sh_corefile_collect_regset (&sh_corefile_gregset, regcache, regno, (char *) &inferior_registers, SHNBSD_SIZEOF_GREGS); if (ptrace (PT_SETREGS, ptid_get_pid (inferior_ptid), (PTRACE_TYPE_ARG3) &inferior_registers, ptid_get_lwp (inferior_ptid)) == -1) perror_with_name (_("Couldn't set registers")); if (regno != -1) return; } }
static void fetch_gregs (struct regcache *regcache, int regnum) { int tid = ptid_get_lwp (inferior_ptid); const gdb_gregset_t regs; int areg; if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) { perror_with_name (_("Couldn't get registers")); return; } supply_gregset_reg (regcache, ®s, regnum); }
static int find_one_thread (ptid_t ptid) { td_thrhandle_t th; td_thrinfo_t ti; td_err_e err; struct thread_info *inferior; struct lwp_info *lwp; struct thread_db *thread_db = current_process ()->priv->thread_db; int lwpid = ptid_get_lwp (ptid); inferior = (struct thread_info *) find_inferior_id (&all_threads, ptid); lwp = get_thread_lwp (inferior); if (lwp->thread_known) return 1; /* Get information about this thread. */ err = thread_db->td_ta_map_lwp2thr_p (thread_db->thread_agent, lwpid, &th); if (err != TD_OK) error ("Cannot get thread handle for LWP %d: %s", lwpid, thread_db_err_str (err)); err = thread_db->td_thr_get_info_p (&th, &ti); if (err != TD_OK) error ("Cannot get thread info for LWP %d: %s", lwpid, thread_db_err_str (err)); if (debug_threads) debug_printf ("Found thread %ld (LWP %d)\n", (unsigned long) ti.ti_tid, ti.ti_lid); if (lwpid != ti.ti_lid) { warning ("PID mismatch! Expected %ld, got %ld", (long) lwpid, (long) ti.ti_lid); return 0; } /* If the new thread ID is zero, a final thread ID will be available later. Do not enable thread debugging yet. */ if (ti.ti_tid == 0) return 0; lwp->thread_known = 1; lwp->th = th; return 1; }
static void store_regs (const struct regcache *regcache) { int ret, regno, tid; elf_gregset_t regs; /* Get the thread id for the ptrace call. */ tid = ptid_get_lwp (inferior_ptid); /* Fetch the general registers. */ if (have_ptrace_getregset == TRIBOOL_TRUE) { struct iovec iov; iov.iov_base = ®s; iov.iov_len = sizeof (regs); ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov); } else ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); if (ret < 0) { warning (_("Unable to fetch general registers.")); return; } aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, arm_apcs_32); if (have_ptrace_getregset == TRIBOOL_TRUE) { struct iovec iov; iov.iov_base = ®s; iov.iov_len = sizeof (regs); ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iov); } else ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); if (ret < 0) { warning (_("Unable to store general registers.")); return; } }
static void mips64_linux_regsets_store_registers (int regno) { int is_fp; int tid; if (regno >= mips_regnum (current_gdbarch)->fp0 && regno <= mips_regnum (current_gdbarch)->fp0 + 32) is_fp = 1; else if (regno == mips_regnum (current_gdbarch)->fp_control_status) is_fp = 1; else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) is_fp = 1; else is_fp = 0; tid = ptid_get_lwp (inferior_ptid); if (tid == 0) tid = ptid_get_pid (inferior_ptid); if (regno == -1 || !is_fp) { mips64_elf_gregset_t regs; if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) perror_with_name (_("Couldn't get registers")); mips64_fill_gregset (®s, regno); if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) perror_with_name (_("Couldn't set registers")); } if (regno == -1 || is_fp) { mips64_elf_fpregset_t fp_regs; if (ptrace (PTRACE_GETFPREGS, tid, 0L, (PTRACE_TYPE_ARG3) &fp_regs) == -1) perror_with_name (_("Couldn't get FP registers")); mips64_fill_fpregset (&fp_regs, regno); if (ptrace (PTRACE_SETFPREGS, tid, 0L, (PTRACE_TYPE_ARG3) &fp_regs) == -1) perror_with_name (_("Couldn't set FP registers")); } }
static void store_vfp_regs (const struct regcache *regcache) { gdb_byte regbuf[VFP_REGS_SIZE]; int ret, regno, tid; struct gdbarch *gdbarch = get_regcache_arch (regcache); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); /* Get the thread id for the ptrace call. */ tid = ptid_get_lwp (inferior_ptid); if (have_ptrace_getregset == TRIBOOL_TRUE) { struct iovec iov; iov.iov_base = regbuf; iov.iov_len = VFP_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); } else ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); if (ret < 0) { warning (_("Unable to fetch VFP registers (for update).")); return; } aarch32_vfp_regcache_collect (regcache, regbuf, tdep->vfp_register_count); if (have_ptrace_getregset == TRIBOOL_TRUE) { struct iovec iov; iov.iov_base = regbuf; iov.iov_len = VFP_REGS_SIZE; ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); } else ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); if (ret < 0) { warning (_("Unable to store VFP registers.")); return; } }
static void fetch_inferior_registers (struct target_ops *ops, struct regcache *regcache, int regnum) { elf_gregset_t regs; int tid; tid = ptid_get_lwp (inferior_ptid); if (tid == 0) tid = ptid_get_pid (inferior_ptid); if (ptrace (PTRACE_GETREGS, tid, 0, (PTRACE_TYPE_ARG3) ®s) < 0) perror_with_name (_("Couldn't get registers")); supply_gregset (regcache, (const elf_gregset_t *)®s); }
static void store_regs (const struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); struct reg inferior_registers; int ret; int regno; for (regno = ARM_A1_REGNUM; regno < ARM_SP_REGNUM; regno++) regcache_raw_collect (regcache, regno, (char *) &inferior_registers.r[regno]); regcache_raw_collect (regcache, ARM_SP_REGNUM, (char *) &inferior_registers.r_sp); regcache_raw_collect (regcache, ARM_LR_REGNUM, (char *) &inferior_registers.r_lr); if (arm_apcs_32) { regcache_raw_collect (regcache, ARM_PC_REGNUM, (char *) &inferior_registers.r_pc); regcache_raw_collect (regcache, ARM_PS_REGNUM, (char *) &inferior_registers.r_cpsr); } else { unsigned pc_val; unsigned psr_val; regcache_raw_collect (regcache, ARM_PC_REGNUM, (char *) &pc_val); regcache_raw_collect (regcache, ARM_PS_REGNUM, (char *) &psr_val); pc_val = gdbarch_addr_bits_remove (gdbarch, pc_val); psr_val ^= gdbarch_addr_bits_remove (gdbarch, psr_val); inferior_registers.r_pc = pc_val | psr_val; } ret = ptrace (PT_SETREGS, ptid_get_pid (inferior_ptid), (PTRACE_TYPE_ARG3) &inferior_registers, ptid_get_lwp(inferior_ptid)); if (ret < 0) warning (_("unable to store general registers")); }
static char * fbsd_pid_to_str (struct target_ops *ops, ptid_t ptid) { lwpid_t lwp; lwp = ptid_get_lwp (ptid); if (lwp != 0) { static char buf[64]; int pid = ptid_get_pid (ptid); xsnprintf (buf, sizeof buf, "LWP %d of process %d", lwp, pid); return buf; } return normal_pid_to_str (ptid); }
static void fetch_fp_regs (struct regcache *regcache) { struct fpreg inferior_fp_registers; int ret; int regno; ret = ptrace (PT_GETFPREGS, ptid_get_pid (inferior_ptid), (PTRACE_TYPE_ARG3) &inferior_fp_registers, ptid_get_lwp(inferior_ptid)); if (ret < 0) { warning (_("unable to fetch floating-point registers")); return; } arm_supply_vfpregset (regcache, &inferior_fp_registers); }
static int fbsd_thread_alive (struct target_ops *ops, ptid_t ptid) { if (ptid_lwp_p (ptid)) { struct ptrace_lwpinfo pl; if (ptrace (PT_LWPINFO, ptid_get_lwp (ptid), (caddr_t) &pl, sizeof pl) == -1) return 0; #ifdef PL_FLAG_EXITED if (pl.pl_flags & PL_FLAG_EXITED) return 0; #endif } return 1; }
static unsigned long amd64_linux_dr_get (ptid_t ptid, int regnum) { int tid; unsigned long value; tid = ptid_get_lwp (ptid); if (tid == 0) tid = ptid_get_pid (ptid); errno = 0; value = ptrace (PTRACE_PEEKUSER, tid, offsetof (struct user, u_debugreg[regnum]), 0); if (errno != 0) perror_with_name (_("Couldn't read debug register")); return value; }
/* Store register REGNO back into the child process. If REGNO is -1, do this for all registers (including the floating point and SSE registers). */ static void m68k_linux_store_inferior_registers (struct target_ops *ops, struct regcache *regcache, int regno) { int tid; /* Use the old method of poking around in `struct user' if the SETREGS request isn't available. */ if (! have_ptrace_getregs) { old_store_inferior_registers (regcache, regno); return; } /* GNU/Linux LWP ID's are process ID's. */ tid = ptid_get_lwp (inferior_ptid); if (tid == 0) tid = ptid_get_pid (inferior_ptid); /* Not a threaded program. */ /* Use the PTRACE_SETFPREGS requests whenever possible, since it transfers more registers in one system call. But remember that store_fpregs can fail, and return zero. */ if (regno == -1) { store_regs (regcache, tid, regno); store_fpregs (regcache, tid, regno); return; } if (getregs_supplies (regno)) { store_regs (regcache, tid, regno); return; } if (getfpregs_supplies (regno)) { store_fpregs (regcache, tid, regno); return; } internal_error (__FILE__, __LINE__, _("Got request to store bad register number %d."), regno); }
static void store_inferior_registers (struct target_ops *ops, struct regcache *regcache, int regnum) { elf_gregset_t regs; int tid; tid = ptid_get_lwp (inferior_ptid); if (tid == 0) tid = ptid_get_pid (inferior_ptid); if (ptrace (PTRACE_GETREGS, tid, 0, (PTRACE_TYPE_ARG3) ®s) < 0) perror_with_name (_("Couldn't get registers")); fill_gregset (regcache, ®s, regnum); if (ptrace (PTRACE_SETREGS, tid, 0, (PTRACE_TYPE_ARG3) ®s) < 0) perror_with_name (_("Couldn't write registers")); }
static void inf_ptrace_fetch_register (struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = get_regcache_arch (regcache); CORE_ADDR addr; size_t size; PTRACE_TYPE_RET *buf; int pid, i; /* This isn't really an address, but ptrace thinks of it as one. */ addr = inf_ptrace_register_u_offset (gdbarch, regnum, 0); if (addr == (CORE_ADDR)-1 || gdbarch_cannot_fetch_register (gdbarch, regnum)) { regcache_raw_supply (regcache, regnum, NULL); return; } /* Cater for systems like GNU/Linux, that implement threads as separate processes. */ pid = ptid_get_lwp (inferior_ptid); if (pid == 0) pid = ptid_get_pid (inferior_ptid); size = register_size (gdbarch, regnum); gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); buf = alloca (size); /* Read the register contents from the inferior a chunk at a time. */ for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) { errno = 0; buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)(uintptr_t)addr, 0); if (errno != 0) error (_("Couldn't read register %s (#%d): %s."), gdbarch_register_name (gdbarch, regnum), regnum, safe_strerror (errno)); addr += sizeof (PTRACE_TYPE_RET); } regcache_raw_supply (regcache, regnum, buf); }
static void store_wmmx_regs (const struct regcache *regcache) { char regbuf[IWMMXT_REGS_SIZE]; int ret, regno, tid; /* Get the thread id for the ptrace call. */ tid = ptid_get_lwp (inferior_ptid); ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); if (ret < 0) { warning (_("Unable to fetch WMMX registers.")); return; } for (regno = 0; regno < 16; regno++) if (REG_VALID == regcache_register_status (regcache, regno + ARM_WR0_REGNUM)) regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, ®buf[regno * 8]); for (regno = 0; regno < 2; regno++) if (REG_VALID == regcache_register_status (regcache, regno + ARM_WCSSF_REGNUM)) regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, ®buf[16 * 8 + regno * 4]); for (regno = 0; regno < 4; regno++) if (REG_VALID == regcache_register_status (regcache, regno + ARM_WCGR0_REGNUM)) regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, ®buf[16 * 8 + 2 * 4 + regno * 4]); ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); if (ret < 0) { warning (_("Unable to store WMMX registers.")); return; } }
static const char * fbsd_thread_name (struct target_ops *self, struct thread_info *thr) { struct ptrace_lwpinfo pl; struct kinfo_proc kp; int pid = ptid_get_pid (thr->ptid); long lwp = ptid_get_lwp (thr->ptid); static char buf[sizeof pl.pl_tdname + 1]; /* Note that ptrace_lwpinfo returns the process command in pl_tdname if a name has not been set explicitly. Return a NULL name in that case. */ fbsd_fetch_kinfo_proc (pid, &kp); if (ptrace (PT_LWPINFO, lwp, (caddr_t) &pl, sizeof pl) == -1) perror_with_name (("ptrace")); if (strcmp (kp.ki_comm, pl.pl_tdname) == 0) return NULL; xsnprintf (buf, sizeof buf, "%s", pl.pl_tdname); return buf; }
static void store_gregs (struct regcache *regcache, int regnum) { int tid = ptid_get_lwp (inferior_ptid); gdb_gregset_t regs; int areg; if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) { perror_with_name (_("Couldn't get registers")); return; } fill_gregset (regcache, ®s, regnum); if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0) { perror_with_name (_("Couldn't write registers")); return; } }
static void ia64_linux_store_register (const struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = get_regcache_arch (regcache); CORE_ADDR addr; size_t size; PTRACE_TYPE_RET *buf; int pid, i; if (ia64_cannot_store_register (gdbarch, regnum)) return; /* Cater for systems like GNU/Linux, that implement threads as separate processes. */ pid = ptid_get_lwp (inferior_ptid); if (pid == 0) pid = ptid_get_pid (inferior_ptid); /* This isn't really an address, but ptrace thinks of it as one. */ addr = ia64_register_addr (gdbarch, regnum); size = register_size (gdbarch, regnum); gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); buf = alloca (size); /* Write the register contents into the inferior a chunk at a time. */ regcache_raw_collect (regcache, regnum, buf); for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) { errno = 0; ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); if (errno != 0) error (_("Couldn't write register %s (#%d): %s."), gdbarch_register_name (gdbarch, regnum), regnum, safe_strerror (errno)); addr += sizeof (PTRACE_TYPE_RET); } }
static void ia64_hpux_fetch_rnat_register (struct regcache *regcache) { CORE_ADDR addr; gdb_byte buf[8]; int status; /* The value of RNAT is stored at bsp|0x1f8, and must be read using TT_LWP_RDRSEBS. */ regcache_raw_read_unsigned (regcache, IA64_BSP_REGNUM, &addr); addr |= 0x1f8; status = ttrace (TT_LWP_RDRSEBS, ptid_get_pid (inferior_ptid), ptid_get_lwp (inferior_ptid), addr, sizeof (buf), (uintptr_t) buf); if (status < 0) error (_("failed to read RNAT register at %s"), paddress (get_regcache_arch(regcache), addr)); regcache_raw_supply (regcache, IA64_RNAT_REGNUM, buf); }
static void store_fp_regs (const struct regcache *regcache) { struct fpreg inferior_fp_registers; int ret; int regno; for (regno = 0; regno <= 15; regno++) regcache_raw_collect (regcache, regno + ARM_D0_REGNUM, (char *) inferior_fp_registers.fpr_vfp.vfp_regs + 8 * regno); regcache_raw_collect (regcache, ARM_FPSCR_REGNUM, (char *) &inferior_fp_registers.fpr_vfp.vfp_fpscr); ret = ptrace (PT_SETFPREGS, ptid_get_pid (inferior_ptid), (PTRACE_TYPE_ARG3) &inferior_fp_registers, ptid_get_lwp(inferior_ptid)); if (ret < 0) warning (_("unable to store floating-point registers")); }
static int mips_linux_read_watch_registers (int force) { int tid; if (force || watch_readback_valid == 0) { tid = ptid_get_lwp (inferior_ptid); if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1) { watch_readback_valid = -1; return 0; } switch (watch_readback.style) { case pt_watch_style_mips32: if (watch_readback.mips32.num_valid == 0) { watch_readback_valid = -1; return 0; } break; case pt_watch_style_mips64: if (watch_readback.mips64.num_valid == 0) { watch_readback_valid = -1; return 0; } break; default: watch_readback_valid = -1; return 0; } /* Watch registers appear to be usable. */ watch_readback_valid = 1; } return (watch_readback_valid == 1) ? 1 : 0; }
static void store_register (const struct regcache *regcache, int regno) { struct gdbarch *gdbarch = get_regcache_arch (regcache); int tid; int val; if (gdbarch_cannot_store_register (gdbarch, regno)) return; /* GNU/Linux LWP ID's are process ID's. */ tid = ptid_get_lwp (inferior_ptid); if (tid == 0) tid = ptid_get_pid (inferior_ptid); /* Not a threaded program. */ errno = 0; regcache_raw_collect (regcache, regno, &val); ptrace (PTRACE_POKEUSER, tid, hppa_linux_register_addr (regno, 0), val); if (errno != 0) error (_("Couldn't write register %s (#%d): %s."), gdbarch_register_name (gdbarch, regno), regno, safe_strerror (errno)); }
static void inf_ptrace_store_register (int regnum) { CORE_ADDR addr; size_t size; PTRACE_TYPE_RET *buf; int pid, i; if (CANNOT_STORE_REGISTER (regnum)) return; /* Cater for systems like GNU/Linux, that implement threads as separate processes. */ pid = ptid_get_lwp (inferior_ptid); if (pid == 0) pid = ptid_get_pid (inferior_ptid); /* This isn't really an address, but ptrace thinks of it as one. */ addr = inf_ptrace_register_u_offset (regnum); size = register_size (current_gdbarch, regnum); gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); buf = alloca (size); /* Write the register contents into the inferior a chunk at a time. */ regcache_raw_collect (current_regcache, regnum, buf); for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) { errno = 0; ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); if (errno != 0) error (_("Couldn't write register %s (#%d): %s."), REGISTER_NAME (regnum), regnum, safe_strerror (errno)); addr += sizeof (PTRACE_TYPE_RET); } }
static int ia64_hpux_write_memory_bs (const gdb_byte *buf, CORE_ADDR addr, int len) { gdb_byte tmp_buf[8]; CORE_ADDR tmp_addr = addr & ~0x7; while (tmp_addr < addr + len) { int status; int lo = 0; int hi = 7; if (tmp_addr < addr || tmp_addr + sizeof (tmp_buf) > addr + len) /* Part of the 8byte region pointed by tmp_addr needs to be preserved. So read it in before we copy the data that needs to be changed. */ if (!ia64_hpux_read_memory_bs (tmp_buf, tmp_addr, sizeof (tmp_buf))) return 0; if (tmp_addr < addr) lo = addr - tmp_addr; if (tmp_addr + sizeof (tmp_buf) > addr + len) hi = addr - tmp_addr + len - 1; memcpy (tmp_buf + lo, buf + tmp_addr - addr + lo, hi - lo + 1); status = ttrace (TT_LWP_WRRSEBS, ptid_get_pid (inferior_ptid), ptid_get_lwp (inferior_ptid), tmp_addr, sizeof (tmp_buf), (uintptr_t) tmp_buf); if (status < 0) return 0; tmp_addr += sizeof (tmp_buf); } return 1; }
void aarch64_linux_prepare_to_resume (struct lwp_info *lwp) { struct arch_lwp_info *info = lwp_arch_private_info (lwp); /* NULL means this is the main thread still going through the shell, or, no watchpoint has been set yet. In that case, there's nothing to do. */ if (info == NULL) return; if (DR_HAS_CHANGED (info->dr_changed_bp) || DR_HAS_CHANGED (info->dr_changed_wp)) { ptid_t ptid = ptid_of_lwp (lwp); int tid = ptid_get_lwp (ptid); struct aarch64_debug_reg_state *state = aarch64_get_debug_reg_state (ptid_get_pid (ptid)); if (show_debug_regs) debug_printf ("prepare_to_resume thread %d\n", tid); /* Watchpoints. */ if (DR_HAS_CHANGED (info->dr_changed_wp)) { aarch64_linux_set_debug_regs (state, tid, 1); DR_CLEAR_CHANGED (info->dr_changed_wp); } /* Breakpoints. */ if (DR_HAS_CHANGED (info->dr_changed_bp)) { aarch64_linux_set_debug_regs (state, tid, 0); DR_CLEAR_CHANGED (info->dr_changed_bp); } } }
static void fetch_fpregs (struct regcache *regcache) { int ret, regno, tid; gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; /* Get the thread id for the ptrace call. */ tid = ptid_get_lwp (inferior_ptid); /* Read the floating point state. */ if (have_ptrace_getregset == TRIBOOL_TRUE) { struct iovec iov; iov.iov_base = &fp; iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); } else ret = ptrace (PT_GETFPREGS, tid, 0, fp); if (ret < 0) { warning (_("Unable to fetch the floating point registers.")); return; } /* Fetch fpsr. */ regcache_raw_supply (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); /* Fetch the floating point registers. */ for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) supply_nwfpe_register (regcache, regno, fp); }