void check_SI5324C(void) { // checks read against programmed values u8 rdbuf[6]; i2c_dev_init_entry_t* pentry = &SI5324C_init_record[0]; xil_printf("Checking Programming for CLKC SI5324\r\n"); while (pentry->regaddr != ENDOFTBL) { if (!read_i2c_reg(XPAR_IIC_CLK_BASEADDR, SI5324C_I2C_ADDR, (u8) pentry->regaddr, &rdbuf[0])) { xil_printf("?Read Failure at I2C Device Address 0x%08x, reg address 0x%08x", SI5324A_I2C_ADDR, (u8) pentry->regaddr); return; } if ((rdbuf[0] != pentry->regval) && (pentry->regaddr != 136)) { xil_printf("Verify Mismatch: Reg=%d Exp=0x%02x Act=0x%02x\r\n", pentry->regaddr, pentry->regval, rdbuf[0]); return; } pentry++; } xil_printf("...all registers verified!\r\n"); }
static int dt3155_init_board(struct dt3155_priv *pd) { struct pci_dev *pdev = pd->pdev; int i; u8 tmp = 0; pci_set_master(pdev); /* dt3155 needs it */ /* resetting the adapter */ iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); mmiowb(); msleep(20); /* initializing adapter registers */ iowrite32(FIFO_EN | SRST, pd->regs + CSR1); mmiowb(); iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); iowrite32(0x00000020, pd->regs + FIFO_TRIGER); iowrite32(0x00000103, pd->regs + XFER_MODE); iowrite32(0, pd->regs + RETRY_WAIT_CNT); iowrite32(0, pd->regs + INT_CSR); iowrite32(1, pd->regs + EVEN_FLD_MASK); iowrite32(1, pd->regs + ODD_FLD_MASK); iowrite32(0, pd->regs + MASK_LENGTH); iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); mmiowb(); /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ read_i2c_reg(pd->regs, DT_ID, &tmp); if (tmp != DT3155_ID) return -ENODEV; /* initialize AD LUT */ write_i2c_reg(pd->regs, AD_ADDR, 0); for (i = 0; i < 256; i++) write_i2c_reg(pd->regs, AD_LUT, i); /* initialize ADC references */ /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); write_i2c_reg(pd->regs, AD_CMD, 34); write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); write_i2c_reg(pd->regs, AD_CMD, 0); /* initialize PM LUT */ write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); for (i = 0; i < 256; i++) { write_i2c_reg(pd->regs, PM_LUT_ADDR, i); write_i2c_reg(pd->regs, PM_LUT_DATA, i); } write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); for (i = 0; i < 256; i++) { write_i2c_reg(pd->regs, PM_LUT_ADDR, i); write_i2c_reg(pd->regs, PM_LUT_DATA, i); } write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ /* select channel 1 for input and set sync level */ write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); /* disable all irqs, clear all irq flags */ iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); return 0; }