void __init plat_irq_setup(void) { register_intc_controller(&intc_desc); register_intc_controller(&intc_desc_dma8); register_intc_controller(&intc_desc_tmu34); register_intc_controller(&intc_desc_pci); }
void __init plat_irq_setup_pins(int mode) { int ret = 0; switch (mode) { case IRQ_MODE_IRQ: ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name); ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name); ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name); ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name); if (unlikely(ret)) { pr_err("Failed to set IRQ mode\n"); return; } register_intc_controller(&intc_desc_irq); break; case IRQ_MODE_IRL3210: ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name); ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name); ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name); ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name); if (unlikely(ret)) { pr_err("Failed to set IRL mode\n"); return; } register_intc_controller(&intc_desc_irl); break; default: BUG(); } }
void __init sh73a0_init_irq(void) { void __iomem *gic_dist_base = IOMEM(0xf0001000); void __iomem *gic_cpu_base = IOMEM(0xf0000100); void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); gic_init(0, 29, gic_dist_base, gic_cpu_base); gic_arch_extn.irq_set_wake = sh73a0_set_wake; register_intc_controller(&intcs_desc); register_intc_controller(&intc_pint0_desc); register_intc_controller(&intc_pint1_desc); /* demux using INTEVTSA */ sh73a0_intcs_cascade.name = "INTCS cascade"; sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; sh73a0_intcs_cascade.dev_id = intevtsa; setup_irq(gic_spi(50), &sh73a0_intcs_cascade); /* PINT pins are sanely tied to the GIC as SPI */ sh73a0_pint0_cascade.name = "PINT0 cascade"; sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; setup_irq(gic_spi(33), &sh73a0_pint0_cascade); sh73a0_pint1_cascade.name = "PINT1 cascade"; sh73a0_pint1_cascade.handler = sh73a0_pint1_demux; setup_irq(gic_spi(34), &sh73a0_pint1_cascade); }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ: /* select IRQ mode for IRL3-0 + IRL7-4 */ ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); register_intc_controller(&intc_irq_desc); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ ctrl_outl(0x40000000, INTC_INTMSKCLR1); ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ ctrl_outl(0x80000000, INTC_INTMSKCLR1); ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ ctrl_outl(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl7654_desc); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ ctrl_outl(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_irl3210_desc); break; default: BUG(); } }
void __init sh7372_init_irq(void) { void __iomem *intevtsa; int n; intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); intevtsa = intcs_ffd2 + 0x100; intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intca_irq_pins_lo_desc); register_intc_controller(&intca_irq_pins_hi_desc); register_intc_controller(&intcs_desc); /* setup dummy cascade chip for INTCS */ n = evt2irq(0xf80); irq_alloc_desc_at(n, numa_node_id()); irq_set_chip_and_handler_name(n, &dummy_irq_chip, handle_level_irq, "level"); set_irq_flags(n, IRQF_VALID); /* yuck */ /* demux using INTEVTSA */ irq_set_handler_data(n, (void *)intevtsa); irq_set_chained_handler(n, intcs_demux); /* unmask INTCS in INTAMASK */ iowrite16(0, intcs_ffd2 + 0x104); }
void __init plat_irq_setup(void) { /* * same vectors for SH7750, SH7750S and SH7091 except for IRLM, * see below.. */ register_intc_controller(&intc_desc); register_intc_controller(&intc_desc_dma4); }
void __init sh7372_init_irq(void) { void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ set_irq_data(evt2irq(0xf80), (void *)intevtsa); set_irq_chained_handler(evt2irq(0xf80), intcs_demux); }
void __init sh7377_init_irq(void) { void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ: register_intc_controller(&intc_desc_irq); break; case IRQ_MODE_IRL3210: register_intc_controller(&intc_desc_irl); break; default: BUG(); } }
void __init sh7372_init_irq(void) { void __iomem *intevtsa; intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); intevtsa = intcs_ffd2 + 0x100; intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); register_intc_controller(&intca_desc); register_intc_controller(&intca_irq_pins_desc); register_intc_controller(&intcs_desc); irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); irq_set_chained_handler(evt2irq(0xf80), intcs_demux); }
/* * Initialize IRQ setting */ void __init init_rts7751r2d_IRQ(void) { struct intc_desc *d; switch (ctrl_inw(PA_VERREG) & 0xf0) { #ifdef CONFIG_RTS7751R2D_PLUS case 0x10: printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n"); d = &intc_desc_r2d_plus; memcpy(irl2irq, irl2irq_r2d_plus, R2D_NR_IRL); break; #endif #ifdef CONFIG_RTS7751R2D_1 case 0x00: /* according to manual */ case 0x30: /* in reality */ printk(KERN_INFO "Using R2D-1 interrupt controller.\n"); d = &intc_desc_r2d_1; memcpy(irl2irq, irl2irq_r2d_1, R2D_NR_IRL); break; #endif default: printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n", ctrl_inw(PA_VERREG)); return; } register_intc_controller(d); #ifdef CONFIG_MFD_SM501 setup_voyagergx_irq(); #endif }
void __init plat_irq_setup(void) { reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq)); reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl)); register_intc_controller(&intc_desc); }
/* * Initialize IRQ setting */ void __init init_se7721_IRQ(void) { /* PPCR */ ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118); register_intc_controller(&intc_desc); intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0); }
void __init plat_irq_setup_pins(int mode) { if (mode == IRQ_MODE_IRQ) { register_intc_controller(&intc_desc_irq); return; } BUG(); }
void __init plat_irq_setup_pins(int mode) { if (mode == IRQ_MODE_IRQ) { ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); register_intc_controller(&intc_desc_irq0123); return; } BUG(); }
void __init plat_irq_setup_pins(int mode) { if (mode == IRQ_MODE_IRQ) { __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); register_intc_controller(&intc_desc_irq0123); return; } BUG(); }
void __init plat_irq_setup(void) { register_intc_controller(&intc_desc); #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) plat_irq_setup_sh3(); #endif }
unsigned char * __init highlander_plat_irq_setup(void) { if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) { printk(KERN_INFO "Using r7780mp interrupt controller.\n"); register_intc_controller(&intc_desc); return irl2irq; } return NULL; }
unsigned char * __init highlander_init_irq_r7780rp(void) { if (ctrl_inw(0xa5000600)) { printk(KERN_INFO "Using r7780rp interrupt controller.\n"); register_intc_controller(&intc_desc); return irl2irq; } return NULL; }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); register_intc_controller(&intc_desc_irlm); break; default: BUG(); } }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ: __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); register_intc_controller(&intc_desc_irq); break; default: BUG(); } }
void __init plat_irq_setup(void) { /* disable IRQ7-0 */ ctrl_outl(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ ctrl_outl(0xc0000000, INTC_INTMSK1); ctrl_outl(0xfffefffe, INTC_INTMSK2); register_intc_controller(&intc_desc); }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ: ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); register_intc_controller(&intc_desc_irq); break; default: BUG(); } }
void __init plat_irq_setup(void) { void *intc2_base; register_intc_controller(&stih415_intc_desc); intc2_base = ioremap(0xfde00000, 0x100); /* Enable the INTC2 */ writel(7, intc2_base + 0x00); /* INTPRI00 */ writel(1, intc2_base + 0x60); /* INTMSKCLR00 */ }
void __init plat_irq_setup_pins(int mode) { if (mode == IRQ_MODE_IRQ) { #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ defined(CONFIG_CPU_SUBTYPE_SH7707) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); register_intc_controller(&intc_desc_irq); return; #endif } BUG(); }
void __init plat_irq_setup(void) { __raw_writel(0xff000000, INTC_INTMSK0); __raw_writel(0xc0000000, INTC_INTMSK1); __raw_writel(0xfffefffe, INTC_INTMSK2); __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); register_intc_controller(&sh7786_intc_desc); }
void __init plat_irq_setup(void) { /* disable IRQ3-0 + IRQ7-4 */ __raw_writel(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ __raw_writel(0xc0000000, INTC_INTMSK1); __raw_writel(0xfffefffe, INTC_INTMSK2); /* select IRL mode for IRL3-0 + IRL7-4 */ __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); register_intc_controller(&intc_desc); }
void __init plat_irq_setup(void) { /* disable IRQ3-0 + IRQ7-4 */ ctrl_outl(0xff000000, INTC_INTMSK0); /* disable IRL3-0 + IRL7-4 */ ctrl_outl(0xc0000000, INTC_INTMSK1); ctrl_outl(0xfffefffe, INTC_INTMSK2); /* select IRL mode for IRL3-0 + IRL7-4 */ ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); register_intc_controller(&intc_desc); }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ7654: __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); register_intc_controller(&intc_desc_irq4567); break; case IRQ_MODE_IRQ3210: __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); register_intc_controller(&intc_desc_irq0123); break; case IRQ_MODE_IRL7654: __raw_writel(0x40000000, INTC_INTMSKCLR1); __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: __raw_writel(0x80000000, INTC_INTMSKCLR1); __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl4567); break; case IRQ_MODE_IRL3210_MASK: __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl0123); break; default: BUG(); } }
void __init plat_irq_setup_pins(int mode) { switch (mode) { case IRQ_MODE_IRQ7654: /* select IRQ mode for IRL7-4 */ __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); register_intc_controller(&intc_desc_irq4567); break; case IRQ_MODE_IRQ3210: /* select IRQ mode for IRL3-0 */ __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); register_intc_controller(&intc_desc_irq0123); break; case IRQ_MODE_IRL7654: /* enable IRL7-4 but don't provide any masking */ __raw_writel(0x40000000, INTC_INTMSKCLR1); __raw_writel(0x0000fffe, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL3210: /* enable IRL0-3 but don't provide any masking */ __raw_writel(0x80000000, INTC_INTMSKCLR1); __raw_writel(0xfffe0000, INTC_INTMSKCLR2); break; case IRQ_MODE_IRL7654_MASK: /* enable IRL7-4 and mask using cpu intc controller */ __raw_writel(0x40000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl4567); break; case IRQ_MODE_IRL3210_MASK: /* enable IRL0-3 and mask using cpu intc controller */ __raw_writel(0x80000000, INTC_INTMSKCLR1); register_intc_controller(&intc_desc_irl0123); break; default: BUG(); } }