static void __init h1940_map_io(void) { s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); s3c24xx_set_board(&h1940_board); }
void __init smdk2410_map_io(void) { s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); s3c24xx_set_board(&smdk2410_board); }
static void __init rx3715_map_io(void) { s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); s3c24xx_set_board(&rx3715_board); }
void __init bit2440_map_io(void) { u32 val;//yu s3c24xx_init_io(bit2440_iodesc, ARRAY_SIZE(bit2440_iodesc)); #ifdef CONFIG_S3C2440_INCLK12 s3c24xx_init_clocks(12000000); #else s3c24xx_init_clocks(16934400); #endif //Add by yu val = readl(S3C2410_GPHCON); //printk("old gphcon = %x\n\n\n", val); val &= ~(0xfff << 4); val |= (0xaaa << 4); writel(val, S3C2410_GPHCON);//inialize RxD2 and TxD2 val = readl(S3C2410_GPHUP); val |= 0x3f << 2; writel(val, S3C2410_GPHUP); val = readl(S3C2410_GPHUP); //printk("new gphup = %x\n", val); /////////////////////////// s3c24xx_init_uarts(bit2440_uartcfgs, ARRAY_SIZE(bit2440_uartcfgs)); s3c24xx_set_board(&bit2440_board); s3c_device_nand.dev.platform_data = &bit_nand_info; }
static void __init smdk2416_map_io(void) { s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); s3c24xx_set_board(&smdk2416_board); }
static void __init anubis_map_io(void) { /* initialise the clocks */ s3c24xx_dclk0.parent = NULL; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; s3c24xx_clkout1.parent = &s3c24xx_dclk1; s3c24xx_uclk.parent = &s3c24xx_clkout1; s3c_device_nand.dev.platform_data = &anubis_nand_info; s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); s3c24xx_set_board(&anubis_board); /* ensure that the GPIO is setup */ s3c2410_gpio_setpin(S3C2410_GPA0, 1); }
void __init otom11_map_io(void) { s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); s3c24xx_set_board(&otom11_board); }
static void __init nexcoder_map_io(void) { s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); s3c24xx_set_board(&nexcoder_board); nexcoder_sensorboard_init(); }
static void __init rx3715_map_io(void) { s3c_device_nand.dev.platform_data = &rx3715_nand_info; s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); s3c24xx_set_board(&rx3715_board); }
static void __init htchermes_map_io(void) { s3c_device_nand.dev.platform_data = &htchermes_nand_info; s3c24xx_init_io(htchermes_iodesc, ARRAY_SIZE(htchermes_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(htchermes_uartcfgs, ARRAY_SIZE(htchermes_uartcfgs)); s3c24xx_set_board(&htchermes_board); }
static void __init falinuxs3c2440_map_io(void) { s3c24xx_init_io(falinuxs3c2440_iodesc, ARRAY_SIZE(falinuxs3c2440_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(falinuxs3c2440_uartcfgs, ARRAY_SIZE(falinuxs3c2440_uartcfgs)); s3c24xx_set_board(&falinuxs3c2440_board); set_s3c2410ts_info(&falinux_s24xx_ts_cfg); }
void __init bast_map_io(void) { /* initialise the clocks */ s3c24xx_dclk0.parent = NULL; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; s3c24xx_clkout1.parent = &s3c24xx_dclk1; s3c24xx_uclk.parent = &s3c24xx_clkout1; s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c2410_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); s3c24xx_set_board(&bast_board); usb_simtec_init(); }
void __init bast_map_io(void) { /* initialise the clocks */ s3c24xx_dclk0.parent = NULL; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; s3c24xx_dclk1.rate = 24*1000*1000; s3c24xx_clkout0.parent = &s3c24xx_dclk0; s3c24xx_clkout1.parent = &s3c24xx_dclk1; s3c24xx_uclk.parent = &s3c24xx_clkout1; s3c_device_nand.dev.platform_data = &bast_nand_info; s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); s3c24xx_set_board(&bast_board); usb_simtec_init(); }
static void __init vr1000_map_io(void) { /* initialise clock sources */ s3c24xx_dclk0.parent = NULL; s3c24xx_dclk0.rate = 12*1000*1000; s3c24xx_dclk1.parent = NULL; s3c24xx_dclk1.rate = 3692307; s3c24xx_clkout0.parent = &s3c24xx_dclk0; s3c24xx_clkout1.parent = &s3c24xx_dclk1; s3c24xx_uclk.parent = &s3c24xx_clkout1; pm_power_off = vr1000_power_off; s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); s3c24xx_set_board(&vr1000_board); usb_simtec_init(); }