void sb_Late_Post(void)
{
AMDSBCFG sb_early_cfg;
u8 data;
printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbLatePost(&sb_early_cfg);
//Set ACPI SCI IRQ to 0x9.
data = CONFIG_ACPI_SCI_IRQ;
outb(0x10, 0xC00);
outb(data, 0xC01);
outb(0x90, 0xC00);
outb(data, 0xC01);
if (data > 0x7) {
data = inb(0x4D1);
data |= (1 << (CONFIG_ACPI_SCI_IRQ - 8));
outb(data, 0x4D1);
} else {
data = inb(0x4D0);
data |= (1 << (CONFIG_ACPI_SCI_IRQ));
outb(data, 0x4D0);
}
printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n");
}
/**
* @brief South Bridge CIMx romstage entry,
* wrapper of sbPowerOnInit entry point.
*/
void sb_before_pci_init(void)
{
AMDSBCFG sb_early_cfg;
printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() take minitues to find the image.
sbBeforePciInit(&sb_early_cfg);
printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n");
}
void sb_After_Pci_Init(void)
{
#if !CONFIG_BOARD_AMD_DINAR
AMDSBCFG sb_early_cfg;
printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
sb900_cimx_config(&sb_early_cfg);
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
//AmdSbDispatcher(&sb_early_cfg);
//TODO
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
// VerifyImage() will fail, LocateImage() takes minutes to find the image.
sbAfterPciInit(&sb_early_cfg);
printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
#endif
}
/**
* @brief SB Cimx entry point sbBeforePciInit wrapper
*/
static void sb900_enable(device_t dev)
{
u8 gpp_port = 0;
struct southbridge_amd_cimx_sb900_config *sb_chip =
(struct southbridge_amd_cimx_sb900_config *)(dev->chip_info);
sb900_cimx_config(sb_config);
printk(BIOS_DEBUG, "sb900_enable() ");
/* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
//- commonInitEarlyBoot(sb_config);
//- commonInitEarlyPost(sb_config);
switch (dev->path.pci.devfn) {
case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */
//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
break;
case (0x11 << 3) | 0: /* 0:11.0 SATA */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataController = ENABLED;
if (1 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
else if (0 == sb_chip->boot_switch_sata_ide)
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
} else {
sb_config->SATAMODE.SataMode.SataController = DISABLED;
}
//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break;
case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */
if (dev->enabled) {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
} else {
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
}
//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
break;
case (0x14 << 3) | 2: /* 0:14:2 HDA */
if (dev->enabled) {
if (AZALIA_DISABLE == sb_config->AzaliaController) {
sb_config->AzaliaController = AZALIA_AUTO;
}
printk(BIOS_DEBUG, "hda enabled\n");
} else {
sb_config->AzaliaController = AZALIA_DISABLE;
printk(BIOS_DEBUG, "hda disabled\n");
}
//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
break;
case (0x14 << 3) | 3: /* 0:14:3 LPC */
break;
case (0x14 << 3) | 4: /* 0:14:4 PCI */
break;
case (0x14 << 3) | 6: /* 0:14:6 GEC */
if (dev->enabled) {
sb_config->GecConfig = 0;
printk(BIOS_DEBUG, "gec enabled\n");
} else {
sb_config->GecConfig = 1;
printk(BIOS_DEBUG, "gec disabled\n");
}
//- gecInitBeforePciEnum(sb_config); // Init GEC
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
gpp_port = (dev->path.pci.devfn) & 0x03;
if (dev->enabled) {
sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
} else {
sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
}
/*
* GPP_CFGMODE_X4000: PortA Lanes[3:0]
* GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
* GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
* GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
*/
if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
sb_config->GppLinkConfig = sb_chip->gpp_configuration;
}
//- sbPcieGppEarlyInit(sb_config);
break;
default:
break;
}
/* Special setting ABCFG registers before PCI emulation. */
//- abSpecialSetBeforePciEnum(sb_config);
//- usbDesertPll(sb_config);
//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
//AmdSbDispatcher(sb_config);
}