int
sc_main( int, char*[] )
{
sc_set_time_resolution( 1, SC_NS );
sc_set_time_resolution( 10, SC_FS );
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution(10.0, SC_NS); // setting the time resolution
// like in SystemC
sca_tdf::sca_signal<double> sig_sine ; // instantiating an sdf-signal
// instantiating TDF-modules works exactly like with SC-modules
// except you need to set the TDF sample period at one port of one
// module of the cluster with set_timestep(). If you forget it, you get a
// run-time error "...at least one sample period must be assigned
// per cluster..."
// a sample period of 100 ns is fine in this case
sine x("sine", 50, 1000);
drain y("drain");
x.out(sig_sine);
y.in(sig_sine);
sca_util::sca_trace_file* tr = sca_util::sca_create_vcd_trace_file("tr");
sca_trace(tr, sig_sine, "sine");
sc_core::sc_start(2, sc_core::SC_MS);
return 0;
}
/**
* main
*/
int sc_main(int argc, char* argv[]) {
sc_set_time_resolution(1, SC_PS);
sc_clock clock("clk", 1, SC_NS);
// Shift reg is declared but not implemented
sc_signal<int> shiftreg_in;
sc_signal<int> shiftreg_out;
sc_trace_file *tf = sc_create_vcd_trace_file("wave");
sc_write_comment(tf, "Simulation of Shift Reg at Elaboration Time Resolution");
sc_trace(tf, clock, "Clock");
sc_trace(tf, shiftreg_in, "shiftreg_in");
sc_trace(tf, shiftreg_out, "shiftreg_out");
sc_start(30, SC_NS);
sc_close_vcd_trace_file(tf);
system("pause");
return 0;
}
void anoc_init_simu() {
// Resolution time ( time stamp ) in nano second;
#ifdef NC_SYSTEMC
sc_set_time_resolution( 1, SC_NS );
#endif
// transaction generation
#ifdef TLM_TRANS_RECORD
tlm_transrecord_database::enable_global_transaction_recording();
if (tlm_transrecord_database::is_global_transaction_recording_enabled()) {
tlm_transrecord_database::open_database(DATA_BASE_NAME, SC_NS);
}
#endif // TLM_TRANS_RECORD
// open & create trace file
#ifdef TRACE_VCD
if (VCD_Record==true) {
pt_trace_file = sc_create_vcd_trace_file(VCD_FILE_NAME); // will automatically add .vcd extension
((vcd_trace_file *)pt_trace_file)->sc_set_vcd_time_unit(TIMESCALE);
}
#endif // TRACE_VCD
// Clean Stop SystemC
signal(SIGINT,anoc_close_simu); // CTRL-C
}
void test_miniuart()
{
sc_set_time_resolution(1, SC_NS);
sc_signal<bool> sys_clk, reset, int_rx, int_tx, txd_rxd;
sc_signal_resolved ce, rd, wr;
sc_signal_rv<2> addr;
sc_signal_rv<8> data_in;
sc_signal_rv<8> data_out;
MiniUart MiniUart_inst("MiniUart");
MiniUart_inst.sys_clk(sys_clk);
MiniUart_inst.reset(reset);
MiniUart_inst.ce(ce);
MiniUart_inst.rd(rd);
MiniUart_inst.wr(wr);
MiniUart_inst.addr(addr);
MiniUart_inst.data_in(data_in);
MiniUart_inst.data_out(data_out);
MiniUart_inst.int_rx(int_rx);
MiniUart_inst.int_tx(int_tx);
MiniUart_inst.rxd(txd_rxd);
MiniUart_inst.txd(txd_rxd);
RTL_TestBench RTL_TestBench_inst("RTL_TestBench");
RTL_TestBench_inst.sys_clk(sys_clk);
RTL_TestBench_inst.reset(reset);
RTL_TestBench_inst.ce(ce);
RTL_TestBench_inst.rd(rd);
RTL_TestBench_inst.wr(wr);
RTL_TestBench_inst.addr(addr);
RTL_TestBench_inst.data_in(data_out);
RTL_TestBench_inst.data_out(data_in);
RTL_TestBench_inst.int_rx(int_rx);
RTL_TestBench_inst.int_tx(int_tx);
sc_trace_file *tf = sc_create_vcd_trace_file("wave_miniuart");
sc_write_comment(tf, "Simulation of Mini Uart");
((vcd_trace_file*)tf)->set_time_unit(1,SC_NS); // 10exp(-9) = 1 ns
sc_trace(tf,sys_clk, "sys_clk");
sc_trace(tf,reset,"reset");
sc_trace(tf,ce,"ce");
sc_trace(tf,rd,"rd");
sc_trace(tf,wr,"wr");
sc_trace(tf,addr,"addr");
sc_trace(tf,data_in,"data_in");
sc_trace(tf,data_out,"data_out");
sc_trace(tf,int_rx,"int_rx");
sc_trace(tf,int_tx,"int_tx");
sc_trace(tf,txd_rxd,"txd_rxd");
sc_start(8, SC_MS);
sc_close_vcd_trace_file(tf);
}
int
sc_main( int, char*[] )
{
sc_set_time_resolution( 10, SC_NS );
cout << sc_get_time_resolution() << endl;
cout << sc_get_default_time_unit() << endl;
return 0;
}
int sc_main( int argc, char* argv[])
{
// create constants
const double TIME_RESOLUTION = 1.0;
const double TOTAL_SIMULATION_TIME = 500.0;
const double CLOCK_PERIOD = 2.0;
// set time parameters
sc_set_time_resolution( TIME_RESOLUTION , SC_NS );
sc_time simulation_time(TOTAL_SIMULATION_TIME,SC_NS);
sc_time clock_time(CLOCK_PERIOD,SC_NS);
// generate clock
sc_clock clock("clock",clock_time);
// create connecting signals from stimulus-->dut
sc_signal< XY_DATA_TYPE > x_stim,y_stim;
sc_signal< XY_DATA_TYPE> x_out,y_out;
sc_signal< Z_DATA_TYPE > z_stim;
sc_signal< Z_DATA_TYPE > z_out;
sc_signal< Z_DATA_TYPE > theta_stim;
sc_signal< RESET_TYPE> reset_stim;
// create stimulus signal object
Stimulus stim("stimulus", TOTAL_SIMULATION_TIME);
stim.reset(reset_stim);
stim.clock(clock);
stim.x_in(x_out);
stim.y_in(y_out);
stim.z_in(z_out);
stim.x_out(x_stim);
stim.y_out(y_stim);
stim.z_out(z_stim);
// create cordic_stage object ( DUT )
CordicStage< XY_DATA_TYPE, Z_DATA_TYPE, RESET_TYPE> cs("cordic_stage", stim.SHIFT);
cs.xin(x_stim);
cs.yin(y_stim);
cs.zin(z_stim);
cs.reset(reset_stim);
cs.xout(x_out);
cs.yout(y_out);
cs.zout(z_out);
cs.clock(clock);
// begin simulation
sc_start( simulation_time );
return 0;
}
int sc_main(int argc, char *argv[]) {
sc_set_time_resolution(1.0, SC_NS);
sc_clock clk("clock", 20.84, SC_NS);
sc_signal<bool> rst;
sc_signal<bool> data_out_wr, oe_wr;
sc_signal<sc_uint<8>> data_out, oe, data_in;
sc_signal_rv<8> pins;
gpio i_gpio("GPIO");
test_gpio i_test("TEST");
i_gpio.clk(clk);
i_gpio.rst(rst);
i_test.clk(clk);
i_test.rst(rst);
i_test.data_out(data_out);
i_test.data_out_wr(data_out_wr);
i_test.oe(oe);
i_test.oe_wr(oe_wr);
i_test.data_in(data_in);
i_test.pin(pins);
i_gpio.data_out(data_out);
i_gpio.data_out_wr(data_out_wr);
i_gpio.oe(oe);
i_gpio.oe_wr(oe_wr);
i_gpio.data_in(data_in);
i_gpio.pin(pins);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_GPIO");
sc_trace(vcd_log, clk, "Clk");
sc_trace(vcd_log, rst, "Reset_n");
sc_trace(vcd_log, pins, "Pins");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_test.error_cnt;
}
int sc_main(int argc, char *argv[]) {
sc_set_time_resolution(1.0, SC_NS);
sc_signal<bool> rx_dp, rx_dn, tx_dp, tx_dn;
sc_signal<bool> uart_txd, uart_rxd;
sc_signal<bool> tx_oe_nc;
ft232r i_ft232r("FT232R");
test_ft232r i_test("TEST");
i_ft232r.tx_dp(tx_dp);
i_ft232r.tx_dn(tx_dn);
i_ft232r.tx_oe(tx_oe_nc);
i_ft232r.rx_dp(rx_dp);
i_ft232r.rx_dn(rx_dn);
i_ft232r.rx_d(rx_dp);
i_ft232r.uart_txd(uart_txd);
i_ft232r.uart_rxd(uart_rxd);
i_test.txdp(rx_dp);
i_test.txdn(rx_dn);
i_test.rxdp(tx_dp);
i_test.rxdn(tx_dn);
i_test.uart_txd(uart_rxd);
i_test.uart_rxd(uart_txd);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_FT232R");
sc_trace(vcd_log, uart_txd, "UART_TXD");
sc_trace(vcd_log, uart_rxd, "UART_RXD");
sc_trace(vcd_log, tx_dp, "USB_TXDP");
sc_trace(vcd_log, tx_dn, "USB_TXDN");
sc_trace(vcd_log, rx_dp, "USB_RXDP");
sc_trace(vcd_log, rx_dn, "USB_RXDN");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_test.error_cnt;
}
int sc_main(int argc, char *argv[]){
sc_signal<bool> clock, reset;
sc_signal<unsigned short int> count_val;
sc_signal<char> v_hi, v_lo;
sc_set_time_resolution(1, SC_US);
stimul stim("stimuli_mod");
stim.clk(clock);
stim.res(reset);
counter count("counter");
count.clk(clock);
count.res(reset);
count.cnt(count_val);
bcd_decoder bcd("bcd_decode");
bcd.val(count_val);
bcd.hi(v_hi);
bcd.lo(v_lo);
sc_trace_file *tf = sc_create_vcd_trace_file("traces");
sc_trace(tf, reset, "reset");
sc_trace(tf, clock, "clock");
sc_trace(tf, count_val, "counter_value");
sc_trace(tf, v_hi, "BCD_High");
sc_trace(tf, v_lo, "BCD_low");
int n_cycles;
if(argc != 2){
cout << "default n_cycles = 200\n";
n_cycles = 200;
}
else
n_cycles = atoi(argv[1]);
sc_start(n_cycles, SC_US);
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution(10.0, sc_core::SC_NS); // setting the time resolution
sca_tdf::sca_signal<double> sig_sine, sig_lpout, sig_mod, sig_abs; // The two signals we need
sca_tdf::sca_signal<bool> out;
sc_signal<bool> in;
sine src("sine", 1, 1000);
lowpass lp("lowpass", 1);
mult m("mult");
absx a("abs");
rec_bit r("rec_bit");
stim s("stim");
src.out(sig_sine);
m.in(sig_sine);
m.bitstream(in);
m.out(sig_mod);
a.in(sig_mod);
a.out(sig_abs);
lp.in(sig_mod);
lp.out(sig_lpout);
r.in(sig_lpout);
r.bitstream(out);
s.in(out);
s.out(in);
sca_util::sca_trace_file* tr = sca_util::sca_create_vcd_trace_file("tr");
sca_util::sca_trace(tr, in, "bit_in");
sca_util::sca_trace(tr, sig_sine ,"sine");
sca_util::sca_trace(tr, sig_mod,"mod");
sca_util::sca_trace(tr, sig_abs,"abs");
sca_util::sca_trace(tr, sig_lpout ,"lpout");
sca_util::sca_trace(tr, out, "bit_out");
sc_core::sc_start(20, sc_core::SC_MS);
return 0;
}
int sc_main (int argc, char *argv[] )
{
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_set_time_resolution(1,SC_NS);
TLL6219::bootConfig bc = TLL6219::BCONF_LINUX;
int i;
for(i=1; i < argc; i++) {
if (strcmp(argv[i], "u") == 0) {
bc = TLL6219::BCONF_UBOOT;
} else if (strcmp(argv[i], "l") == 0) {
bc = TLL6219::BCONF_LINUX;
} else if (strcmp(argv[i], "b") == 0) {
bc = TLL6219::BCONF_BAREMETAL;
} else {
cout << "Usage: TLL_tlm2.0.exe [u|l|b]" << endl;
cout << " u = U-Boot: l = Linux: b = Bare metal" << endl;
exit(0);
break;
}
}
// Ignore some of the Warning messages
icmIgnoreMessage ("ICM_NPF");
cout << "Constructing." << endl;
TLL5000 top("top", bc);
cout << "default time resolution = " << sc_get_time_resolution() << endl;
// start the simulation
cout << "Starting sc_main." << endl;
sc_start();
cout << "Finished sc_main." << endl;
return 0; // return okay status
}
int sc_main(int argc, char* argv[]) {
cout << "INFO: Elaborating ..." << endl;
sc_set_time_resolution(100,SC_PS);
sc_time period(2,SC_NS);
generator clock("clock", period);
test_generator test_generator_i("test_generator_i");
test_generator_i.clock(clock);
cout << "INFO: Simulating " << endl;
sc_start(20, SC_NS);
cout << "INFO: Post-processing ... " << endl;
system("pause");
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution(10.0, sc_core::SC_NS); // setting the time resolution
sca_tdf::sca_signal<double> sig_sine, sig_lpout ; // The two signals we need
sine src("sine", 50, 1000);
drain dr("drain");
lp_elec lp("lowpass", 160, 100e-6);
src.out(sig_sine);
lp.in(sig_sine);
lp.out(sig_lpout);
dr.in(sig_lpout);
sca_util::sca_trace_file* tr = sca_util::sca_create_vcd_trace_file("tr");
sca_util::sca_trace(tr, sig_sine ,"sine");
sca_util::sca_trace(tr, sig_lpout ,"lpout");
sc_core::sc_start(20, sc_core::SC_MS);
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution(1, SC_FS); // for solvers
sca_tdf::sca_signal<double> osc_out, osc_in, del_out;
sca_eln::sca_node v0, v1, v2;
sca_eln::sca_node_ref gnd;
char mn[64]; // used to create unique module name strings
osc *osc1; // oscilators with weighted sum input and pll generator
a_delay *del1; // delay for 90 degree phase delay in feedback loops
int temp;
// electrial network components
sca_eln::sca_tdf::sca_vsink *vsnk;
sca_eln::sca_tdf::sca_vsource *vsrc;
sca_eln::sca_r *r1, *rs;
sca_eln::sca_c *c1;
sca_eln::sca_l *l1;
srand(time(NULL));
/********** instantiating library-modules**********/
// generate oscilators and connections
sprintf(mn,"%s%i","osc",1);
osc1 = new osc(mn);
osc1->outp(osc_out);
osc1->inp(osc_in);
osc1->set_timestep(1, SC_PS);
sprintf(mn,"%s%i","del",1);
del1 = new a_delay(mn, 0.7, 25); // in timestep units
del1->inp(osc_out);
del1->outp(del_out);
vsrc = new sca_eln::sca_tdf::sca_vsource("vsrc");
vsrc->inp(del_out);
vsrc->p(v0);
vsrc->n(gnd);
rs = new sca_eln::sca_r("RS", 1.0e4);
rs->p(v0);
rs->n(v1);
c1 = new sca_eln::sca_c("C1", 1.0e-15);
c1->p(v1);
c1->n(gnd);
// r1 = new sca_eln::sca_r("R1", 1.0e6);
// r1->p(v1);
// r1->n(v2);
// l1 = new sca_eln::sca_l("L1", 1.0e-9);
// l1->p(v1);
// l1->n(v2);
vsnk = new sca_eln::sca_tdf::sca_vsink("vsnk");
vsnk->outp(osc_in);
vsnk->p(v1);
vsnk->n(gnd);
/********* tracing signals *************************/
sca_util::sca_trace_file* atf = sca_util::sca_create_vcd_trace_file( "osc" );
sprintf(mn,"%s%i","osc_out",1);
sca_util::sca_trace( atf, osc_out, mn);
sca_util::sca_trace(atf,del_out, "del_out");
sca_util::sca_trace(atf,v0, "v0");
sca_util::sca_trace(atf,v1, "v1");
sca_util::sca_trace(atf,v2, "v2");
sprintf(mn,"%s%i","osc_in",1);
sca_util::sca_trace( atf, osc_in, mn);
sc_start(10.0, SC_NS);
sca_util::sca_close_vcd_trace_file( atf );
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution(1, SC_NS); //
/********** defining signals and parameters *********** */
sca_tdf::sca_signal<double> modulation;
sca_tdf::sca_signal<double> source;
sca_tdf::sca_signal<double> vco_out_delay;
// pll loop signals
sca_tdf::sca_signal<double> lpf_out;
sca_tdf::sca_signal<double> pco;
sca_tdf::sca_signal<double> vco_out;
//
double s_freq = 1000.0, m_freq=10.0;
int rate = 1;
/********** setting parameters for simulation *********** */
cout <<"\n" << "source frequency = ";
cin >> s_freq;
std::cout <<"\n s_freq is " << s_freq <<"\n" ;
cout <<"\n" << "modulation frequency =";
cin >> m_freq;
std::cout <<"\n m_freq is " << m_freq <<"\n" ;
cout <<"\n" << "sample rate =";
cin >> rate;
std::cout <<"\n rate is " << rate << "\n";
/********** instantiating library-modules**********/
sine sinin("sinin",
s_freq, // freq_def
1.0, // amp_def
0.0, // phase
0.0, // offset
false, // amp_control
false, // freq_control
1 // datarate
);
//sinin.freq_in(modulation);
sinin.set_timestep(10.0, SC_US);
sinin.out(source);
// note this is a minor rewite of the pll in the tuv_ams bb library
/*****************************PLL***************************************/
phc phc_sub("phc_sub",
1, // phc_out_rate
100.0 // phc_gain (will be Mpyed by kvco)
);
phc_sub.in_ref(source);
phc_sub.in_vco(vco_out_delay);
phc_sub.out(pco);
lp lp_sub("lp_sub",
10.0 // lp_fc (about 1/100 of vco_freq)
);
lp_sub.in(pco);
lp_sub.out(lpf_out); //lpo output 2
a_vco vco_sub("vco_sub",
1000.0, // vco_freq,
1, // vco_out_rate
100.0, // kvco units are add/sub from freq (pull in range)
1.0 //vco_gain
);
vco_sub.in(lpf_out); // lpo
vco_sub.out(vco_out); // vcoo output 1
//vco_sub.out.set_delay(1); // does not work
a_delay vco_delay("vco_delay",
0.0, // initial value
1 // delay
);
vco_delay.inp(vco_out);
vco_delay.outp(vco_out_delay);
drain drn1("drn1");
drn1.in(vco_out_delay);
drain drn2("drn2");
drn2.in(lpf_out);
//drain drn3("drn3");
//drn2.in(vco_out);
/********* tracing signals *************************/
sca_util::sca_trace_file* atf = sca_util::sca_create_vcd_trace_file( "pll" );
sca_util::sca_trace( atf, source, "source" );
sca_util::sca_trace( atf, modulation ,"modulation" );
sca_util::sca_trace( atf, vco_out ,"vco_out" );
sca_util::sca_trace( atf, vco_out_delay ,"vco_out_delay" );
sca_util::sca_trace( atf, lpf_out ,"lpf_out" );
sc_start(1000.0, SC_MS);
sca_util::sca_close_vcd_trace_file( atf );
return 0;
}
int sc_main(int argc, char *argv[]) {
sc_set_time_resolution(1.0, SC_NS);
sc_clock clk("clock", 20.84, SC_NS);
sc_signal<bool> rst;
sc_signal<bool> txd, rxd;
sc_signal<bool> tx_data_wr;
sc_signal<sc_uint<8>> tx_data;
sc_signal<bool> tx_empty;
sc_signal<bool> rx_data_rd;
sc_signal<sc_uint<8>> rx_data;
sc_signal<bool> rx_avail;
uart i_uart("UART");
test_uart i_test("TEST");
i_uart.clk(clk);
i_uart.rst(rst);
i_uart.txd(txd);
i_uart.rxd(rxd);
i_uart.tx_data_wr(tx_data_wr);
i_uart.tx_data(tx_data);
i_uart.tx_empty(tx_empty);
i_uart.rx_data_rd(rx_data_rd);
i_uart.rx_data(rx_data);
i_uart.rx_avail(rx_avail);
i_test.clk(clk);
i_test.rst(rst);
i_test.txd(rxd);
i_test.rxd(txd);
i_test.tx_data_wr(tx_data_wr);
i_test.tx_data(tx_data);
i_test.tx_empty(tx_empty);
i_test.rx_data_rd(rx_data_rd);
i_test.rx_data(rx_data);
i_test.rx_avail(rx_avail);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_UART");
sc_trace(vcd_log, clk, "Clk");
sc_trace(vcd_log, rst, "Reset_n");
sc_trace(vcd_log, txd, "TXD");
sc_trace(vcd_log, rxd, "RXD");
sc_trace(vcd_log, tx_data_wr, "tx_data_wr");
sc_trace(vcd_log, tx_data, "tx_data");
sc_trace(vcd_log, tx_empty, "tx_empty");
sc_trace(vcd_log, rx_data_rd, "rx_data_rd");
sc_trace(vcd_log, rx_data, "rx_data");
sc_trace(vcd_log, rx_avail, "rx_avail");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_test.error_cnt;
}
int sc_main (int argc, char *argv[]) {
cout << "SYSTEMC_VERSION="<<dec<<SYSTEMC_VERSION<<endl;
cout << "Compiled with pointer size "<<((sizeof(char*)==8) ? "-m64":"-m32")<<endl;
// Timescale
#if (SYSTEMC_VERSION>=20070314)
sc_set_time_resolution(100.0, SC_FS);
#elif (SYSTEMC_VERSION>20011000)
sc_set_time_resolution(100.0, SC_FS);
sc_set_default_time_unit(1.0, SC_NS);
sc_report::make_warnings_errors(true);
#else
sc_time dut(1.0, sc_ns);
sc_set_default_time_unit(dut);
#endif // SYSTEMC_VERSION
#ifndef NC_SYSTEMC
// Simulation logfile
sp_log_file splog;
splog.open ("sim.log");
splog.redirect_cout();
#endif
// Pins
#if SYSTEMC_VERSION >= 20060505
sc_clock clk("clk",5,SC_NS); // We want a non-integer half period to prove VCD works
#else
sc_clock clk("clk",5);
#endif // SYSTEMC_VERSION
ExBench* bench;
SP_CELL (bench,ExBench);
SP_PIN (bench,clk,clk);
bench->configure(); // Verify the #sp include worked
#ifndef NC_SYSTEMC
# if SYSTEMC_VERSION < 20060505
sc_initialize();
# endif
#endif
// Example enumeration usage
MyENumClass enval = MyENumClass::ONE;
cout << "Assigned to enumeration = "<<enval<<endl; // Prints "ONE"
cout << "Iterating an enumeration =";
for (MyENumSimple::iterator it=MyENumSimple::begin();
it!=MyENumSimple::end(); ++it) {
cout << " " << (*it).ascii();
}
cout << endl;
#ifndef NC_SYSTEMC
// SystemC traces are flawed, you can't even trace ports
sc_trace_file *tf = sc_create_vcd_trace_file("sim_sc" );
sc_trace(tf, clk, "clk");
#if SYSTEMC_VERSION >= 20070314
tf->set_time_unit(1, SC_NS);
#endif
// SystemPerl traces
SpTraceFile* stp = new SpTraceFile;
bench->trace(stp,999);
stp->open("sim_sp.vcd");
// Alternative SystemPerl traces, allowing rollover
// After running, concat the two files to make the vcd file.
SpTraceFile* stp2 = new SpTraceFile;
stp2->rolloverMB(1); // Rollover logfiles when size > 1MB
bench->trace(stp2,999);
stp2->open("sim_sp2.vcd");
#endif // NC_SYSTEMC
cout << "Starting\n";
#if SYSTEMC_VERSION >= 20060505
sc_start();
#else
sc_start(-1);
#endif // SYSTEMC_VERSION
cout << "Done\n";
#ifndef NC_SYSTEMC
sc_close_vcd_trace_file(tf);
SpTraceVcd::flush_all();
#endif // NC_SYSTEMC
// Coverage
mkdir("logs", 0777);
SpCoverage::write(); // Writes logs/coverage.pl
return (0);
}
void test_rx_unit()
{
sc_set_time_resolution(1, SC_NS);
sc_signal<bool> reset, enable_tx, load, reg_empty, buf_empty;
sc_signal<bool> enable_rx, read, txd_rxd, d_rdy, o_err, f_err;
sc_signal<sc_uint<8> > tx_data, rx_data;
sc_clock clk("clk",25,SC_NS); // 40MHz
ClkUnit ClkUnit_inst("ClkUnit");
ClkUnit_inst.sys_clk(clk);
ClkUnit_inst.reset(reset);
ClkUnit_inst.enable_tx(enable_tx);
ClkUnit_inst.enable_rx(enable_rx);
TxUnit TxUnit_inst("TxUnit");
TxUnit_inst.sys_clk(clk);
TxUnit_inst.reset(reset);
TxUnit_inst.enable(enable_tx);
TxUnit_inst.load(load);
TxUnit_inst.data_in(tx_data);
TxUnit_inst.reg_empty(reg_empty);
TxUnit_inst.buf_empty(buf_empty);
TxUnit_inst.txd(txd_rxd);
RxUnit RxUnit_inst("RxUnit");
RxUnit_inst.sys_clk(clk);
RxUnit_inst.reset(reset);
RxUnit_inst.enable(enable_rx);
RxUnit_inst.read(read);
RxUnit_inst.data_out(rx_data);
RxUnit_inst.frame_err(f_err);
RxUnit_inst.output_err(o_err);
RxUnit_inst.data_rdy(d_rdy);
RxUnit_inst.rxd(txd_rxd);
sc_trace_file *tf = sc_create_vcd_trace_file("wave_rxunit");
sc_write_comment(tf, "Simulation of Tx Unit");
((vcd_trace_file*)tf)->set_time_unit(1, SC_NS); // 10exp(-9) = 1 ns
sc_trace(tf,clk, "clk");
sc_trace(tf,reset,"reset");
sc_trace(tf,load,"load");
sc_trace(tf,tx_data,"tx_data");
sc_trace(tf,buf_empty,"buf_empty");
sc_trace(tf,reg_empty,"reg_empty");
sc_trace(tf,txd_rxd,"txd_rxd");
sc_trace(tf,enable_rx,"enable_rx");
sc_trace(tf,read,"read");
sc_trace(tf,rx_data,"rx_data");
sc_trace(tf,f_err,"f_err");
sc_trace(tf,o_err,"o_err");
sc_trace(tf,d_rdy,"d_rdy");
// Reset
cout << "Reset ..." << endl;
load.write(false);
reset.write(true);
sc_start(1, SC_US);
reset.write(false);
sc_start(1, SC_US);
// Load
cout << "Load ..." << endl;
tx_data.write(0x4c);
load.write(true);
sc_start(10, SC_US);
// First Send
cout << "Send on TxD ..." << endl;
load.write(false);
sc_start(1.5, SC_MS);
// First Read
cout << "Read on RxD ..." << endl;
read.write(true);
sc_start(5, SC_US);
read.write(false);
sc_start(1, SC_US);
// Load
cout << "Load ..." << endl;
tx_data.write(0x6f);
load.write(true);
sc_start(10, SC_US);
// Second Send
cout << "Send on TxD ..." << endl;
load.write(false);
sc_start(1.5, SC_MS);
// Second Read
cout << "Read on RxD ..." << endl;
read.write(true);
sc_start(5, SC_US);
read.write(false);
sc_start(1, SC_US);
// Load
cout << "Load ..." << endl;
tx_data.write(0x4c);
load.write(true);
sc_start(10, SC_US);
// Third Send
cout << "Send on TxD ..." << endl;
load.write(false);
sc_start(1.5, SC_MS);
// Load
cout << "Load ..." << endl;
tx_data.write(0x0d);
load.write(true);
sc_start(10, SC_US);
// Fourth Send
cout << "Send on TxD ..." << endl;
load.write(false);
sc_start(1.5, SC_MS);
sc_close_vcd_trace_file(tf);
}
void Simulator::Init(wchar_t const* model)
{
m_model = model;
sc_set_time_resolution(1.0, SC_MS);
}
int sc_main(int argc, char *argv[]) {
std::cout << "sc_main() invoked" << std::endl;
sc_set_time_resolution(1.0, SC_NS);
// Signals
typedef sc_uint<10> analog_type;
typedef sc_uint<8> app_state_type;
sc_signal_resolved d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13;
sc_signal<Arduino::analog_type> a0, a1, a2, a3, a4, a5;
sc_signal<Arduino::app_state_type> app_state;
// Comopnents
Arduino i_uut("Arduino", ArduinoFirmware::setup, ArduinoFirmware::loop);
test_arduino i_tb("TEST");
// Port maps
i_uut.d0(d0);
i_uut.d1(d1);
i_uut.d2(d2);
i_uut.d3(d3);
i_uut.d4(d4);
i_uut.d5(d5);
i_uut.d6(d6);
i_uut.d7(d7);
i_uut.d8(d8);
i_uut.d9(d9);
i_uut.d10(d10);
i_uut.d11(d11);
i_uut.d12(d12);
i_uut.d13(d13);
i_uut.a0(a0);
i_uut.a1(a1);
i_uut.a2(a2);
i_uut.a3(a3);
i_uut.a4(a4);
i_uut.a5(a5);
i_uut.app_state(app_state);
i_tb.d0(d0);
i_tb.d1(d1);
i_tb.d2(d2);
i_tb.d3(d3);
i_tb.d4(d4);
i_tb.d5(d5);
i_tb.d6(d6);
i_tb.d7(d7);
i_tb.d8(d8);
i_tb.d9(d9);
i_tb.d10(d10);
i_tb.d11(d11);
i_tb.d12(d12);
i_tb.d13(d13);
i_tb.a0(a0);
i_tb.a1(a1);
i_tb.a2(a2);
i_tb.a3(a3);
i_tb.a4(a4);
i_tb.a5(a5);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_Arduino");
sc_trace(vcd_log, d0, "d0");
sc_trace(vcd_log, d1, "d1");
sc_trace(vcd_log, d2, "d2");
sc_trace(vcd_log, d3, "d3");
sc_trace(vcd_log, d4, "d4");
sc_trace(vcd_log, d5, "d5");
sc_trace(vcd_log, d6, "d6");
sc_trace(vcd_log, d7, "d7");
sc_trace(vcd_log, d8, "d8");
sc_trace(vcd_log, d9, "d9");
sc_trace(vcd_log, d10, "d10");
sc_trace(vcd_log, d11, "d11");
sc_trace(vcd_log, d12, "d12");
sc_trace(vcd_log, d13, "d13");
sc_trace(vcd_log, a0, "a0");
sc_trace(vcd_log, a1, "a1");
sc_trace(vcd_log, a1, "a2");
sc_trace(vcd_log, a1, "a3");
sc_trace(vcd_log, app_state, "app_state");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_tb.error_cnt;
}
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution(1, SC_NS); // for solvers
sca_tdf::sca_signal<double> vco[NN];
sca_tdf::sca_signal<double> vcod[NN];
sca_tdf::sca_signal<double> lpf[NN];
sca_tdf::sca_signal<double> sw[NN][NN];
sca_tdf::sca_signal<double> phco[NN];
sca_tdf::sca_signal<double> phcof[NN];
double phc_gain = 1.0/NN;//100 // phase comparitor gain
double lp_fc = 100.0; //10 // low pass filter cut off freq
double vco_freq = 1000.0; // natural frequency of vco
double kvco = 10.0;//1000 10 // control sensitivity for vco
double vco_gain = 1.0; // amplitude gain of vco
double phase = 0.0; // inital phase of vco in pll
double fphase, ophase, dphase = 0.0;
char mn[64]; // used to create unique module name strings
int ninety = (int) floor(0.25/(vco_freq*1e-5)); // # samples for 90 degree phase delay at vco_freq and sample rate
osc *oscp[NN]; // oscilators with weighted sum input and pll generator
a_delay *del[NN]; // delay for 90 degree phase delay in feedback loops
constant *con[NN][NN]; // constant sources for Sij weights
phc *phcomp[NN]; // for pairwise phase comparison
lp *plpf[NN]; // low pass filter
int temp;
// 90 degree phase delay mapped into sample points
// cout << "ninety degrees at this sample rate is:" << ninety << " time-steps" << endl;
srand(time(NULL));
//print out patterns
for(int i=0; i < NN; i++) {
dphase = pattern1[0][i%NN]-pattern1[0][(i+1)%NN];
if (dphase == 0)
cout << " +1 ";
else
cout << " -1 ";
if(i%(NN/4) == (NN/4-1)) cout << endl;
}
cout << endl;
for(int i=0; i < NN; i++) {
dphase = pattern2[0][i%NN]-pattern2[0][(i+1)%NN];
if (dphase == 0)
cout << " +1 ";
else
cout << " -1 ";
if(i%(NN/4) == (NN/4-1)) cout << endl;
}
cout << endl;
// zero diagonals
// for(int i=0; i < NN; i++) {
// pattern[i][i] = 0.0;
// }
/********** instantiating library-modules**********/
// generate oscilators and connections with loop
for(int i=0; i<NN; i++) {
sprintf(mn,"%s%i","osc",i);
phase = (rand() % (int)floor(2 * M_PI * 100))/100.0; // random phase 0-2*PI
if (i == 0) fphase = ophase = phase;
if(i>0) {
dphase = abs(phase-ophase);
if (dphase < M_PI/4.0) cout << " +1 ";
else if (dphase < 3*M_PI/4.0) cout << " 0 ";
else if (dphase < 5*M_PI/4.0) cout << " -1 ";
else if (dphase < 7*M_PI/4.0) cout << " 0 ";
else cout << " +1 ";
if(i%(NN/4) == (NN/4-1)) cout << endl;
// cout << endl;
}
if(i == NN-1) {
ophase = fphase;
dphase = abs(phase-ophase);
if (dphase < M_PI/4.0) cout << " +1 ";
else if (dphase < 3*M_PI/4.0) cout << " 0 ";
else if (dphase < 5*M_PI/4.0) cout << " -1 ";
else if (dphase < 7*M_PI/4.0) cout << " 0 ";
else cout << " +1 ";
if(i%(NN/4) == (NN/4-1)) cout << endl;
// cout << endl;
}
ophase = phase;
oscp[i] = new osc(mn, phc_gain, lp_fc, vco_freq, kvco, vco_gain, phase);
oscp[i]->VCO_OUT(vco[i]);
oscp[i]->LPF_OUT(lpf[i]);
sprintf(mn,"%s%i","del",i);
del[i] = new a_delay(mn, 0, ninety);
del[i]->inp(vco[i]);
del[i]->outp(vcod[i]);
sprintf(mn, "%s%i","ph",i);
phcomp[i] = new phc(mn, 1, M_PI); // phase compare in terms of pi
phcomp[i]->in_ref(vco[i]);
phcomp[i]->in_vco(vco[(i+1)%NN]);
phcomp[i]->out(phco[i]);
sprintf(mn, "%s%i","plpf",i);
plpf[i] = new lp(mn, 10.0);
plpf[i]->in(phco[i]);
plpf[i]->out(phcof[i]);
// connect up the NN inputs
for(int j=0; j<NN; j++) {
oscp[i]->VCO_IN[j](vcod[j]);
oscp[i]->W[j](sw[i][j]);
}
}
// Now we set the weights
for(int i=0; i<NN; i++) {
for(int j=0; j<NN; j++) {
temp = pattern[i][j];
sprintf(mn,"%s_%i_%i","con",i,j);
con[i][j] = new constant(mn, temp);
con[i][j]->out(sw[i][j]);
con[i][j]->set_timestep(10.0, SC_US);
}
}
/********* tracing signals *************************/
sca_util::sca_trace_file* atf = sca_util::sca_create_vcd_trace_file( "pll" );
for(int i = 0; i<NN; i++) {
// sprintf(mn,"%s%i","vco",i);
// sca_util::sca_trace( atf, vco[i], mn);
// sprintf(mn,"%s%i","lpf",i);
// sca_util::sca_trace( atf, lpf[i] ,mn);
sprintf(mn,"%s%i","phcf",i);
sca_util::sca_trace( atf, phcof[i] ,mn);
}
sc_start(1000.0, SC_MS);
sca_util::sca_close_vcd_trace_file( atf );
return 0;
}