static void xtensa_store_gregset (struct regcache *regcache, const void *buf) { const elf_greg_t* rset = (const elf_greg_t*)buf; int ar0_regnum; char *ptr; int i; /* Take care of AR registers. */ ar0_regnum = find_regno ("ar0"); ptr = (char *)&rset[R_A0]; for (i = ar0_regnum; i < ar0_regnum + XCHAL_NUM_AREGS; i++) { supply_register (regcache, i, ptr); ptr += register_size(i); } /* Loop registers, if hardware has it. */ #if XCHAL_HAVE_LOOP supply_register_by_name (regcache, "lbeg", (char*)&rset[R_LBEG]); supply_register_by_name (regcache, "lend", (char*)&rset[R_LEND]); supply_register_by_name (regcache, "lcount", (char*)&rset[R_LCOUNT]); #endif supply_register_by_name (regcache, "sar", (char*)&rset[R_SAR]); supply_register_by_name (regcache, "pc", (char*)&rset[R_PC]); supply_register_by_name (regcache, "ps", (char*)&rset[R_PS]); supply_register_by_name (regcache, "windowbase", (char*)&rset[R_WB]); supply_register_by_name (regcache, "windowstart", (char*)&rset[R_WS]); }
static void ppc_set_pc (CORE_ADDR pc) { if (register_size (0) == 4) { unsigned int newpc = pc; supply_register_by_name ("pc", &newpc); } else { unsigned long newpc = pc; supply_register_by_name ("pc", &newpc); } }
static void aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc) { if (register_size (regcache->tdesc, 0) == 8) { unsigned long newpc = pc; supply_register_by_name (regcache, "pc", &newpc); } else { unsigned int newpc = pc; supply_register_by_name (regcache, "pc", &newpc); } }
static void tile_set_pc (struct regcache *regcache, CORE_ADDR pc) { unsigned long newpc = pc; supply_register_by_name (regcache, "pc", &newpc); }
static void i386_set_pc (CORE_ADDR newpc) { if (debug_threads) fprintf (stderr, "set pc to %08lx\n", (long) newpc); supply_register_by_name ("eip", &newpc); }
static void ppc_set_pc (CORE_ADDR pc) { unsigned long newpc = pc; supply_register_by_name ("pc", &newpc); }
static void ppc_store_evrregset (const void *buf) { int i, ev0; const struct gdb_evrregset_t *regset = buf; if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)) return; ev0 = find_regno ("ev0h"); for (i = 0; i < 32; i++) supply_register (ev0 + i, ®set->evr[i]); supply_register_by_name ("acc", ®set->acc); supply_register_by_name ("spefscr", ®set->spefscr); }
static void ppc_store_vrregset (const void *buf) { int i, base; const char *regset = buf; if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)) return; base = find_regno ("vr0"); for (i = 0; i < 32; i++) supply_register (base + i, ®set[i * 16]); supply_register_by_name ("vscr", ®set[32 * 16 + 12]); supply_register_by_name ("vrsave", ®set[33 * 16]); }
static void m68k_set_pc (struct regcache *regcache, CORE_ADDR value) { unsigned long newpc = value; supply_register_by_name (regcache, "pc", &newpc); }
static void m68k_set_pc (CORE_ADDR value) { unsigned long newpc = value; supply_register_by_name ("pc", &newpc); }
static void s390_set_pc (struct regcache *regcache, CORE_ADDR newpc) { if (register_size (regcache->tdesc, 0) == 4) { unsigned int pswa; collect_register_by_name (regcache, "pswa", &pswa); pswa = (pswa & 0x80000000) | (newpc & 0x7fffffff); supply_register_by_name (regcache, "pswa", &pswa); } else { unsigned long pc = newpc; supply_register_by_name (regcache, "pswa", &pc); } }
static void nios2_set_pc (struct regcache *regcache, CORE_ADDR pc) { union nios2_register newpc; newpc.reg32 = pc; supply_register_by_name (regcache, "pc", newpc.buf); }
static void s390_store_last_break (struct regcache *regcache, const void *buf) { const char *p; p = (const char *) buf + 8 - register_size (regcache->tdesc, 0); supply_register_by_name (regcache, "last_break", p); }
static void nios2_set_pc (CORE_ADDR pc) { union nios2_register newpc; newpc.reg32 = pc; supply_register_by_name ("pc", newpc.buf); }
static void s390_set_pc (CORE_ADDR newpc) { unsigned long pc = newpc; #ifndef __s390x__ pc |= 0x80000000; #endif supply_register_by_name ("pswa", &pc); }
static void set_pc ( CORE_ADDR newpc ) { Bool mod; supply_register_by_name ("pc", &newpc, &mod); if (mod) dlog(1, "set pc to %p\n", C2v (newpc)); else dlog(1, "set pc not changed %p\n", C2v (newpc)); }
static void i386_store_gregset (const void *buf) { int i; for (i = 0; i < i386_num_regs; i++) supply_register (i, ((char *) buf) + i386_regmap[i]); supply_register_by_name ("orig_eax", ((char *) buf) + ORIG_EAX * 4); }
static void xtensa_store_xtregset (struct regcache *regcache, const void *buf) { const xtensa_regtable_t *ptr; for (ptr = xtensa_regmap_table; ptr->name; ptr++) { supply_register_by_name (regcache, ptr->name, (char*)buf + ptr->ptrace_offset); } }
static void mips_set_pc (struct regcache *regcache, CORE_ADDR pc) { union mips_register newpc; if (register_size (0) == 4) newpc.reg32 = pc; else newpc.reg64 = pc; supply_register_by_name (regcache, "pc", newpc.buf); }
void arm_store_vfpregset_num (struct regcache *regcache, const void *buf, int num) { int i, base; gdb_assert (num == 16 || num == 32); base = find_regno (regcache->tdesc, "d0"); for (i = 0; i < num; i++) supply_register (regcache, base + i, (char *) buf + i * 8); supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8); }
static void arm_store_vfpregset (struct regcache *regcache, const void *buf) { int i, num, base; if (!(arm_hwcap & HWCAP_VFP)) return; if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) num = 32; else num = 16; base = find_regno ("d0"); for (i = 0; i < num; i++) supply_register (regcache, base + i, (char *) buf + i * 8); supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8); }
static int cris_insert_point (char type, CORE_ADDR addr, int len) { int bp; unsigned long bp_ctrl; unsigned long start, end; unsigned long ccs; struct regcache *regcache; /* Breakpoint/watchpoint types (GDB terminology): 0 = memory breakpoint for instructions (not supported; done via memory write instead) 1 = hardware breakpoint for instructions (not supported) 2 = write watchpoint (supported) 3 = read watchpoint (supported) 4 = access watchpoint (supported). */ if (type < '2' || type > '4') { /* Unsupported. */ return 1; } regcache = get_thread_regcache (current_inferior, 1); /* Read watchpoints are set as access watchpoints, because of GDB's inability to deal with pure read watchpoints. */ if (type == '3') type = '4'; /* Get the configuration register. */ collect_register_by_name (regcache, "s0", &bp_ctrl); /* The watchpoint allocation scheme is the simplest possible. For example, if a region is watched for read and a write watch is requested, a new watchpoint will be used. Also, if a watch for a region that is already covered by one or more existing watchpoints, a new watchpoint will be used. */ /* First, find a free data watchpoint. */ for (bp = 0; bp < 6; bp++) { /* Each data watchpoint's control registers occupy 2 bits (hence the 3), starting at bit 2 for D0 (hence the 2) with 4 bits between for each watchpoint (yes, the 4). */ if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) break; } if (bp > 5) { /* We're out of watchpoints. */ return -1; } /* Configure the control register first. */ if (type == '3' || type == '4') { /* Trigger on read. */ bp_ctrl |= (1 << (2 + bp * 4)); } if (type == '2' || type == '4') { /* Trigger on write. */ bp_ctrl |= (2 << (2 + bp * 4)); } /* Setup the configuration register. */ supply_register_by_name (regcache, "s0", &bp_ctrl); /* Setup the range. */ start = addr; end = addr + len - 1; /* Configure the watchpoint register. */ cris_write_data_breakpoint (regcache, bp, start, end); collect_register_by_name (regcache, "ccs", &ccs); /* Set the S1 flag to enable watchpoints. */ ccs |= (1 << 19); supply_register_by_name (regcache, "ccs", &ccs); return 0; }
static void cris_write_data_breakpoint (struct regcache *regcache, int bp, unsigned long start, unsigned long end) { switch (bp) { case 0: supply_register_by_name (regcache, "s3", &start); supply_register_by_name (regcache, "s4", &end); break; case 1: supply_register_by_name (regcache, "s5", &start); supply_register_by_name (regcache, "s6", &end); break; case 2: supply_register_by_name (regcache, "s7", &start); supply_register_by_name (regcache, "s8", &end); break; case 3: supply_register_by_name (regcache, "s9", &start); supply_register_by_name (regcache, "s10", &end); break; case 4: supply_register_by_name (regcache, "s11", &start); supply_register_by_name (regcache, "s12", &end); break; case 5: supply_register_by_name (regcache, "s13", &start); supply_register_by_name (regcache, "s14", &end); break; } }
static int cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, int len, struct raw_breakpoint *bp) { int bp; unsigned long bp_ctrl; unsigned long start, end; unsigned long ccs; struct regcache *regcache; regcache = get_thread_regcache (current_thread, 1); /* Read watchpoints are set as access watchpoints, because of GDB's inability to deal with pure read watchpoints. */ if (type == raw_bkpt_type_read_wp) type = raw_bkpt_type_access_wp; /* Get the configuration register. */ collect_register_by_name (regcache, "s0", &bp_ctrl); /* The watchpoint allocation scheme is the simplest possible. For example, if a region is watched for read and a write watch is requested, a new watchpoint will be used. Also, if a watch for a region that is already covered by one or more existing watchpoints, a new watchpoint will be used. */ /* First, find a free data watchpoint. */ for (bp = 0; bp < 6; bp++) { /* Each data watchpoint's control registers occupy 2 bits (hence the 3), starting at bit 2 for D0 (hence the 2) with 4 bits between for each watchpoint (yes, the 4). */ if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) break; } if (bp > 5) { /* We're out of watchpoints. */ return -1; } /* Configure the control register first. */ if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp) { /* Trigger on read. */ bp_ctrl |= (1 << (2 + bp * 4)); } if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp) { /* Trigger on write. */ bp_ctrl |= (2 << (2 + bp * 4)); } /* Setup the configuration register. */ supply_register_by_name (regcache, "s0", &bp_ctrl); /* Setup the range. */ start = addr; end = addr + len - 1; /* Configure the watchpoint register. */ cris_write_data_breakpoint (regcache, bp, start, end); collect_register_by_name (regcache, "ccs", &ccs); /* Set the S1 flag to enable watchpoints. */ ccs |= (1 << 19); supply_register_by_name (regcache, "ccs", &ccs); return 0; }
static void s390_store_system_call (struct regcache *regcache, const void *buf) { supply_register_by_name (regcache, "system_call", buf); }