static int pmc_probe(struct of_device *ofdev, const struct of_device_id *id)
{
struct device_node *np = ofdev->dev.of_node;
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, "fsl,mpc8548-pmc");
if (node) {
pmc_regs = of_iomap(ofdev->dev.of_node, 0);
if (!pmc_regs)
return -ENOMEM;
if (of_device_is_compatible(np, "fsl,mpc8536-pmc")) {
has_deep_sleep = 1;
}
if (of_device_is_compatible(np, "fsl,p1022-pmc")) {
has_lossless = 1;
}
of_node_put(node);
}
pmc_dev = &ofdev->dev;
suspend_set_ops(&pmc_suspend_ops);
return 0;
}
static int __init sharpsl_pm_probe(struct platform_device *pdev)
{
int ret;
if (!pdev->dev.platform_data)
return -EINVAL;
sharpsl_pm.dev = &pdev->dev;
sharpsl_pm.machinfo = pdev->dev.platform_data;
sharpsl_pm.charge_mode = CHRG_OFF;
sharpsl_pm.flags = 0;
init_timer(&sharpsl_pm.ac_timer);
sharpsl_pm.ac_timer.function = sharpsl_ac_timer;
init_timer(&sharpsl_pm.chrg_full_timer);
sharpsl_pm.chrg_full_timer.function = sharpsl_chrg_full_timer;
led_trigger_register_simple("sharpsl-charge", &sharpsl_charge_led_trigger);
sharpsl_pm.machinfo->init();
ret = device_create_file(&pdev->dev, &dev_attr_battery_percentage);
ret |= device_create_file(&pdev->dev, &dev_attr_battery_voltage);
if (ret != 0)
dev_warn(&pdev->dev, "Failed to register attributes (%d)\n", ret);
apm_get_power_status = sharpsl_apm_get_power_status;
suspend_set_ops(&sharpsl_pm_ops);
mod_timer(&sharpsl_pm.ac_timer, jiffies + msecs_to_jiffies(250));
return 0;
}
static int __init pxa910_pm_init(void)
{
if (!cpu_is_pxa910())
return -EIO;
suspend_set_ops(&pxa910_pm_ops);
return 0;
}
static __init int exynos_pm_drvinit(void)
{
pr_info("Exynos PM intialize\n");
suspend_set_ops(&exynos_pm_ops);
return 0;
}
static int sharpsl_pm_remove(struct platform_device *pdev)
{
suspend_set_ops(NULL);
device_remove_file(&pdev->dev, &dev_attr_battery_percentage);
device_remove_file(&pdev->dev, &dev_attr_battery_voltage);
led_trigger_unregister_simple(sharpsl_charge_led_trigger);
free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
if (sharpsl_pm.machinfo->gpio_fatal)
free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
if (sharpsl_pm.machinfo->batfull_irq)
free_irq(gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
gpio_free(sharpsl_pm.machinfo->gpio_batlock);
gpio_free(sharpsl_pm.machinfo->gpio_batfull);
gpio_free(sharpsl_pm.machinfo->gpio_acin);
if (sharpsl_pm.machinfo->exit)
sharpsl_pm.machinfo->exit();
del_timer_sync(&sharpsl_pm.chrg_full_timer);
del_timer_sync(&sharpsl_pm.ac_timer);
return 0;
}
static int __init mx35_pm_init(void)
{
pr_info("Static Power Management for Freescale i.MX35\n");
suspend_set_ops(&mx35_suspend_ops);
return 0;
}
int __init pm_init(void)
{
printk("%s: Initializing Power Management ....\n", __func__);
suspend_set_ops(&suspend_ops);
return 0;
}
void __init ux500_pm_init(u32 phy_base, u32 size)
{
struct device_node *np;
prcmu_base = ioremap(phy_base, size);
if (!prcmu_base) {
pr_err("could not remap PRCMU for PM functions\n");
return;
}
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
dist_base = of_iomap(np, 0);
of_node_put(np);
if (!dist_base) {
pr_err("could not remap GIC dist base for PM functions\n");
return;
}
/*
* On watchdog reboot the GIC is in some cases decoupled.
* This will make sure that the GIC is correctly configured.
*/
prcmu_gic_recouple();
/* Set up ux500 suspend callbacks. */
suspend_set_ops(UX500_SUSPEND_OPS);
/* Initialize ux500 power domains */
ux500_pm_domains_init();
}
void __init exynos_pm_init(void)
{
const struct of_device_id *match;
struct device_node *np;
u32 tmp;
np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
if (!np) {
pr_err("Failed to find PMU node\n");
return;
}
if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
return;
}
pm_data = (const struct exynos_pm_data *) match->data;
/* All wakeup disable */
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
tmp |= pm_data->wake_disable_mask;
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
exynos_pm_syscore_ops.resume = pm_data->pm_resume;
register_syscore_ops(&exynos_pm_syscore_ops);
suspend_set_ops(&exynos_suspend_ops);
}
int __init s3c_pm_init(void)
{
#ifdef CONFIG_RTC_TICK_SLEEP_AGING_TEST
int err = -EINVAL;
#endif
printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
suspend_set_ops(&s3c_pm_ops);
#ifdef CONFIG_RTC_TICK_SLEEP_AGING_TEST
if (!power_kobj)
goto obj_err;
err = sysfs_create_file(power_kobj, &dev_attr_s3c_tick_wakeup_enable.attr);
if (err) {
pr_err("%s: failed to create /sys/power/s3c_tick_wakeup_enable\n", __func__);
}
obj_err:
return err;
#else
return 0;
#endif
}
int __init imap_pm_init(void)
{
printk("IMAP Power Management, Copyright 2010 Infotm\n");
suspend_set_ops(&imapx200_pm_ops);
return 0;
}
static int __init pnx4008_pm_init(void)
{
u32 sram_size_to_allocate;
pll4_clk = clk_get(0, "ck_pll4");
if (IS_ERR(pll4_clk)) {
printk(KERN_ERR
"PM Suspend cannot acquire ARM(PLL4) clock control\n");
return PTR_ERR(pll4_clk);
}
if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
sram_size_to_allocate = pnx4008_cpu_standby_sz;
else
sram_size_to_allocate = pnx4008_cpu_suspend_sz;
saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
if (!saved_sram) {
printk(KERN_ERR
"PM Suspend: cannot allocate memory to save portion of SRAM\n");
clk_put(pll4_clk);
return -ENOMEM;
}
suspend_set_ops(&pnx4008_pm_ops);
return 0;
}
static int __init mx31_pm_init(void)
{
printk(KERN_INFO "Power Management for Freescale MX31\n");
suspend_set_ops(&mx31_suspend_ops);
return 0;
}
static int __init mmp2_pm_init(void)
{
uint32_t apcr;
if (!cpu_is_mmp2())
return -EIO;
suspend_set_ops(&mmp2_pm_ops);
/*
* Set bit 0, Slow clock Select 32K clock input instead of VCXO
* VCXO is chosen by default, which would be disabled in suspend
*/
__raw_writel(0x5, MPMU_SCCR);
/*
* Clear bit 23 of CIU_CPU_CONF
* direct PJ4 to DDR access through Memory Controller slow queue
* fast queue has issue and cause lcd will flick
*/
__raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8));
/* Clear default low power control bit */
apcr = __raw_readl(MPMU_PCR_PJ);
apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD
| MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13);
__raw_writel(apcr, MPMU_PCR_PJ);
return 0;
}
static int am33xx_pm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
int ret;
if (!of_machine_is_compatible("ti,am33xx") &&
!of_machine_is_compatible("ti,am43"))
return -ENODEV;
pm_ops = dev->platform_data;
if (!pm_ops) {
dev_err(dev, "PM: Cannot get core PM ops!\n");
return -ENODEV;
}
pm_sram = pm_ops->get_sram_addrs();
if (!pm_sram) {
dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
return -ENODEV;
}
pm33xx_dev = dev;
ret = am33xx_pm_alloc_sram();
if (ret)
return ret;
ret = am33xx_push_sram_idle();
if (ret)
goto err_free_sram;
m3_ipc = wkup_m3_ipc_get();
if (!m3_ipc) {
dev_dbg(dev, "PM: Cannot get wkup_m3_ipc handle\n");
ret = -EPROBE_DEFER;
goto err_free_sram;
}
am33xx_pm_set_ipc_ops();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&am33xx_pm_ops);
#endif /* CONFIG_SUSPEND */
ret = pm_ops->init();
if (ret) {
dev_err(dev, "Unable to call core pm init!\n");
ret = -ENODEV;
goto err_put_wkup_m3_ipc;
}
return 0;
err_put_wkup_m3_ipc:
wkup_m3_ipc_put(m3_ipc);
err_free_sram:
am33xx_pm_free_sram();
pm33xx_dev = NULL;
return ret;
}
static int am33xx_pm_remove(struct platform_device *pdev)
{
suspend_set_ops(NULL);
wkup_m3_ipc_put(m3_ipc);
am33xx_pm_free_sram();
return 0;
}
int __init s3c_pm_init(void)
{
printk(KERN_INFO "S3C Power Management, Copyright 2004 Simtec Electronics\n");
suspend_set_ops(&s3c_pm_ops);
return 0;
}
void __init exynos_pm_init(void)
{
const struct of_device_id *match;
u32 tmp;
of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
if (!match) {
pr_err("Failed to find PMU node\n");
return;
}
pm_data = (struct exynos_pm_data *) match->data;
/* Platform-specific GIC callback */
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
/* All wakeup disable */
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
tmp |= pm_data->wake_disable_mask;
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
exynos_pm_syscore_ops.resume = pm_data->pm_resume;
register_syscore_ops(&exynos_pm_syscore_ops);
suspend_set_ops(&exynos_suspend_ops);
}
int __init sirfsoc_pm_init(void)
{
sirfsoc_of_pwrc_init();
sirfsoc_memc_init();
suspend_set_ops(&sirfsoc_pm_ops);
return 0;
}
int __init emxx_pm_init(void)
{
int ret;
printk(KERN_INFO "Power Management for EMXX.\n");
/* initialize static variable */
variable_init();
pm_idle = emxx_pm_idle;
suspend_set_ops(&emxx_pm_ops);
pm_loops_per_jiffy = loops_per_jiffy;
ret = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
if (ret)
printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
#ifdef CONFIG_PROC_FS
{
struct proc_dir_entry *entry;
entry = create_proc_read_entry("pm", S_IWUSR | S_IRUGO, NULL,
emxx_pm_read_proc, 0);
if (entry == NULL)
return -ENOENT;
entry->write_proc = (write_proc_t *)emxx_pm_write_proc;
}
#endif
pm_power_off = emxx_pm_power_off;
return 0;
}
int __init omap2_common_pm_late_init(void)
{
/*
* In the case of DT, the PMIC and SR initialization will be done using
* a completely different mechanism.
* Disable this part if a DT blob is available.
*/
if (of_have_populated_dt())
return 0;
/* Init the voltage layer */
omap_pmic_late_init();
omap_voltage_late_init();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Smartreflex device init */
omap_devinit_smartreflex();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops);
#endif
return 0;
}
static void am33xx_m3_fw_ready_cb(void)
{
int ret = 0;
ret = wkup_m3_prepare();
if (ret) {
pr_err("PM: Could not prepare WKUP_M3\n");
return;
}
ret = wait_for_completion_timeout(&am33xx_pm_sync,
msecs_to_jiffies(500));
if (WARN(ret == 0, "PM: MPU<->CM3 sync failure\n"))
return;
am33xx_pm->ver = wkup_m3_fw_version_read();
if (am33xx_pm->ver == M3_VERSION_UNKNOWN ||
am33xx_pm->ver < M3_BASELINE_VERSION) {
pr_warn("PM: CM3 Firmware Version %x not supported\n",
am33xx_pm->ver);
return;
} else {
pr_info("PM: CM3 Firmware Version = 0x%x\n",
am33xx_pm->ver);
}
if (soc_is_am33xx())
am33xx_idle_init(susp_params.wfi_flags & WFI_MEM_TYPE_DDR3);
#ifdef CONFIG_SUSPEND
suspend_set_ops(&am33xx_pm_ops);
#endif /* CONFIG_SUSPEND */
}
int __init magus_pm_init(void)
{
int error;
u32 sram_size_to_allocate;
printk("Power Management for MAGUS. %s\n", PM_VERSION);
init_addr_external_device();
if (magus_idle_loop_suspend_sz > magus_cpu_suspend_sz)
sram_size_to_allocate = magus_idle_loop_suspend_sz;
else
sram_size_to_allocate = magus_cpu_suspend_sz;
saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
if (!saved_sram) {
printk(KERN_ERR
"PM Suspend: cannot allocate memory to save portion of SRAM\n");
return -ENOMEM;
}
suspend_set_ops(&magus_pm_ops);
//pm_idle = magus_pm_idle;
error = subsys_create_file(&power_subsys, &sleep_while_idle_attr);
if (error)
printk(KERN_ERR "PM: subsys_create_file failed: %d\n", error);
return 0;
}
static int __init mx27_pm_init(void)
{
if (!cpu_is_mx27())
return 0;
suspend_set_ops(&mx27_suspend_ops);
return 0;
}
int __init ak7801_pm_init(void)
{
printk("AK88 Power Management, (c) 2010 ANYKA\n");
suspend_set_ops(&ak7801_pm_ops);
return 0;
}
/*
* Initialize power interface
*/
int __init jz_pm_init(void)
{
printk(JZ_SOC_NAME ": Power Management Interface Registered.\n");
suspend_set_ops(&jz_pm_ops);
return 0;
}
void __init tegra_init_suspend(void)
{
if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
return;
tegra_pmc_suspend_init();
suspend_set_ops(&tegra_suspend_ops);
}
static int __init am33xx_pm_init(void)
{
int ret;
if (!cpu_is_am33xx())
return -ENODEV;
pr_info("Power Management for AM33XX family\n");
#ifdef CONFIG_SUSPEND
#ifdef CONFIG_TI_PM_DISABLE_VT_SWITCH
pm_set_vt_switch(0);
#endif
(void) clkdm_for_each(clkdms_setup, NULL);
/* CEFUSE domain should be turned off post bootup */
cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
if (cefuse_pwrdm == NULL)
printk(KERN_ERR "Failed to get cefuse_pwrdm\n");
else
pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
if (gfx_pwrdm == NULL)
printk(KERN_ERR "Failed to get gfx_pwrdm\n");
gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
if (gfx_l3_clkdm == NULL)
printk(KERN_ERR "Failed to get gfx_l3_clkdm\n");
gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
if (gfx_l4ls_clkdm == NULL)
printk(KERN_ERR "Failed to get gfx_l4ls_gfx_clkdm\n");
mpu_dev = omap_device_get_by_hwmod_name("mpu");
if (!mpu_dev) {
pr_warning("%s: unable to get the mpu device\n", __func__);
return -EINVAL;
}
ret = wkup_m3_init();
if (ret) {
pr_err("Could not initialise WKUP_M3. "
"Power management will be compromised\n");
enable_deep_sleep = false;
}
if (enable_deep_sleep)
suspend_set_ops(&am33xx_pm_ops);
#endif /* CONFIG_SUSPEND */
return ret;
}
static int __init mx3_pm_init(void)
{
printk(KERN_INFO "Power Management for Freescale MX3x\n");
if (cpu_is_mx35())
mx3_suspend_ops.enter = mx35_suspend_enter;
suspend_set_ops(&mx3_suspend_ops);
return 0;
}
static int am33xx_pm_probe(struct platform_device *pdev)
{
int ret;
if (!of_machine_is_compatible("ti,am33xx") &&
!of_machine_is_compatible("ti,am43"))
return -ENODEV;
ret = am43xx_map_gic();
if (ret) {
pr_err("PM: Could not ioremap SCU\n");
return ret;
}
pm_sram = amx3_get_sram_addrs();
if (!pm_sram) {
pr_err("PM: Cannot get PM asm function addresses!!\n");
return -ENODEV;
}
pm_ops = amx3_get_pm_ops();
if (!pm_ops) {
pr_err("PM: Cannot get core PM ops!\n");
return -ENODEV;
}
ret = am33xx_prepare_push_sram_idle();
if (ret)
return ret;
ret = am33xx_pm_rtc_setup();
if (ret)
return ret;
am33xx_push_sram_idle();
am33xx_pm_set_ipc_ops();
#ifdef CONFIG_SUSPEND
suspend_set_ops(&am33xx_pm_ops);
#endif /* CONFIG_SUSPEND */
suspend_wfi_flags = 0;
suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
suspend_wfi_flags |= WFI_FLAG_DISABLE_EMIF;
suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
ret = pm_ops->init(am33xx_do_sram_idle);
if (ret) {
pr_err("Unable to call core pm init!\n");
return -ENODEV;
}
return 0;
}
