static void uhci_reset (hci_t *controller) { /* reset */ uhci_reg_write16 (controller, USBCMD, 4); mdelay (50); uhci_reg_write16 (controller, USBCMD, 0); mdelay (10); uhci_reg_write16 (controller, USBCMD, 2); while ((uhci_reg_read16 (controller, USBCMD) & 2) != 0) mdelay (1); uhci_reg_write32 (controller, FLBASEADD, (u32) virt_to_phys (UHCI_INST (controller)-> framelistptr)); //debug ("framelist at %p\n",UHCI_INST(controller)->framelistptr); /* disable irqs */ uhci_reg_write16 (controller, USBINTR, 0); /* reset framelist index */ uhci_reg_write16 (controller, FRNUM, 0); uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0); // max packets, configure flag uhci_start (controller); }
static void uhci_reinit (hci_t *controller) { uhci_reg_write32 (controller, FLBASEADD, (u32) virt_to_phys (UHCI_INST (controller)-> framelistptr)); //usb_debug ("framelist at %p\n",UHCI_INST(controller)->framelistptr); /* disable irqs */ uhci_reg_write16 (controller, USBINTR, 0); /* reset framelist index */ uhci_reg_write16 (controller, FRNUM, 0); uhci_reg_write16(controller, USBCMD, uhci_reg_read16(controller, USBCMD) | 0xc0); // max packets, configure flag uhci_start (controller); }
void uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask) { uhci_reg_write32 (ctrl, reg, (uhci_reg_read32 (ctrl, reg) & andmask) | ormask); }