static void dragrace_frame_callback(int dummy) { int i; for (i = 0; i < 2; i++) { switch (readinputport(5 + i)) { case 0x01: dragrace_gear[i] = 1; break; case 0x02: dragrace_gear[i] = 2; break; case 0x04: dragrace_gear[i] = 3; break; case 0x08: dragrace_gear[i] = 4; break; case 0x10: dragrace_gear[i] = 0; break; } } /* watchdog is disabled during service mode */ watchdog_enable(readinputport(0) & 0x20); }
static TIMER_CALLBACK( nmi_callback ) { int scanline = param + 64; if (scanline >= VTOTAL) { scanline = 32; } /* NMI and watchdog are disabled during service mode */ watchdog_enable(readinputport(0) & 0x40); if (readinputport(0) & 0x40) { cpunum_set_input_line(0, INPUT_LINE_NMI, PULSE_LINE); } timer_set(video_screen_get_time_until_pos(0, scanline, 0), NULL, scanline, nmi_callback); }
static void nmi_callback(int scanline) { scanline += 64; if (scanline >= 262) { scanline = 32; } /* NMI and watchdog are disabled during service mode */ watchdog_enable(readinputport(2) & 0x40); if (readinputport(2) & 0x40) { cpunum_set_input_line(0, INPUT_LINE_NMI, PULSE_LINE); } timer_set(cpu_getscanlinetime(scanline), scanline, nmi_callback); }
void user_init(unsigned char init) { if (init) { user_data.demand_voltage = 0; user_data.demand_current = 0; user_data.on = 0; } /* initialize UART1 */ uart_init(1, BD_9600); watchdog_enable(2); SFRPAGE = CONFIG_PAGE; P0MDOUT = 0x81; // P0.0: TX = Push Pull, P0.7 = Push Pull /* indicate we can receive data */ CTS = 0; output_flag = 1; }
static retval_t cmd_watchdog_enable(const subsystem_t *self, frame_t * iframe, frame_t * oframe) { uint32_t key; uint16_t seconds; retval_t rv; if (RV_SUCCESS != frame_get_u32(iframe, &key)) return RV_ILLEGAL; if (RV_SUCCESS != frame_get_u16(iframe, &seconds)) return RV_ILLEGAL; FUTURE_HOOK_4(pm_cmd_watchdog_enable, &key, &seconds, iframe, oframe); if (0xCACACECA != key) return RV_ILLEGAL; log_report_fmt(LOG_SS_PLATFORM, "PLATFORM: setting watchdog to %d\r\n", seconds); rv = watchdog_enable(seconds); if (RV_SUCCESS == rv) { log_report_fmt(LOG_SS_PLATFORM, "PLATFORM: set watchdog to %d!\r\n", seconds); } else { (void)frame_put_u32(oframe, rv); } return rv; }
void reset_cpu(ulong addr) { watchdog_enable(); while(1); }
void reset_cpu(ulong addr) { watchdog_enable(); loop_to_die: goto loop_to_die; }
static int sl351x_wdt_resume(struct platform_device *dev) { watchdog_set_timeout(wdt_margin); watchdog_enable(); }
/* trap handler: main entry point */ int __trap_to_gdb(struct cpu_user_regs *regs, unsigned long cookie) { int rc = 0; unsigned long flags; if ( gdb_ctx->serhnd < 0 ) { printk("Debugging connection not set up.\n"); return -EBUSY; } /* We rely on our caller to ensure we're only on one processor * at a time... We should probably panic here, but given that * we're a debugger we should probably be a little tolerant of * things going wrong. */ /* We don't want to use a spin lock here, because we're doing two distinct things: 1 -- we don't want to run on more than one processor at a time, and 2 -- we want to do something sensible if we re-enter ourselves. Spin locks are good for 1, but useless for 2. */ if ( !atomic_dec_and_test(&gdb_ctx->running) ) { printk("WARNING WARNING WARNING: Avoiding recursive gdb.\n"); atomic_inc(&gdb_ctx->running); return -EBUSY; } if ( !gdb_ctx->connected ) { printk("GDB connection activated.\n"); gdb_arch_print_state(regs); gdb_ctx->connected = 1; } gdb_smp_pause(); local_irq_save(flags); watchdog_disable(); console_start_sync(); /* Shouldn't really do this, but otherwise we stop for no obvious reason, which is Bad */ printk("Waiting for GDB to attach...\n"); gdb_arch_enter(regs); gdb_ctx->signum = gdb_arch_signal_num(regs, cookie); /* If gdb is already attached, tell it we've stopped again. */ if ( gdb_ctx->currently_attached ) { gdb_start_packet(gdb_ctx); gdb_cmd_signum(gdb_ctx); } do { if ( receive_command(gdb_ctx) < 0 ) { dbg_printk("Error in GDB session...\n"); rc = -EIO; break; } } while ( process_command(regs, gdb_ctx) == 0 ); gdb_smp_resume(); gdb_arch_exit(regs); console_end_sync(); watchdog_enable(); atomic_inc(&gdb_ctx->running); local_irq_restore(flags); return rc; }
void sbromsw_entry(void) { toc0_private_head_t *toc0 = (toc0_private_head_t *)CONFIG_SBROMSW_BASE; uint dram_size; int ret, flag; timer_init(); set_pll(); sunxi_serial_init(toc0_config->uart_port, toc0_config->uart_ctrl, 2); printf("try to probe rtc region\n"); flag = rtc_region_probe_fel_flag(); printf("flag=0x%x\n", flag); if(flag == SUNXI_RUN_EFEX_FLAG) { printf("sbromsw_entry sbromsw_probe_fel_flag\n"); rtc_region_clear_fel_flag(); goto __sbromsw_entry_err0; } #ifdef CONFIG_BOOT_A15 // printf("toc0_config->boot_cpu=0x%x\n", toc0_config->boot_cpu); // if(toc0_config->boot_cpu) // { // flag = BOOT_A7_FLAG; // } // else // { // flag = BOOT_A15_FLAG; // } /* boot_cpu 含义 bit0~7 bit8~15 0:不需要保存标志位 1:当前应该切换a15启动 1:通知u-boot保存 0:当前应该切换a7启动 每次从brom读取的boot_cpu只能是0x100或者0 */ if(flag == BOOT_A15_FLAG) { rtc_region_clear_fel_flag(); if(toc0_config->boot_cpu == 0x00) toc0_config->boot_cpu = 0x101; //a15启动,需要保存标志位 switch_to_a15(toc0_config->pwr_en); } else if(flag == BOOT_A7_FLAG) { rtc_region_clear_fel_flag(); if(toc0_config->boot_cpu == 0x100) //如果原本是a15启动 toc0_config->boot_cpu = 0x01; //a7启动,需要保存标志位 } else { if(toc0_config->boot_cpu == 0x100) { switch_to_a15(toc0_config->pwr_en); //a15启动,不需要保存标志位 } else { toc0_config->boot_cpu = 0x0; //a7启动,不需要保存标志位 } } //printf("toc0_config->boot_cpu=0x%x\n", toc0_config->boot_cpu); #endif printf("try to setup mmu\n"); //mmu init mmu_setup(); printf("mmu setup ok\n"); //dram init printf("try to init dram\n"); dram_size = init_DRAM(0, (void *)toc0_config->dram_para); if (dram_size) { printf("init dram ok, size=%dM\n", dram_size); } else { printf("init dram fail\n"); goto __sbromsw_entry_err; } printf("init heap\n"); create_heap(CONFIG_HEAP_BASE, CONFIG_HEAP_SIZE); printf("init gic\n"); gic_init(); printf("init flash\n"); ret = sunxi_flash_init(toc0->platform[0] & 0x0f); //初始化外部介质,准备读取TOC1数据 if(ret) { printf("sbromsw_entry sunxi_flash_init failed\n"); goto __sbromsw_entry_err; } ret = toc1_init(); //TOC1初始化,判断TOC1的头部是否合格 if(ret) { printf("sbromsw_entry toc1_init failed\n"); goto __sbromsw_entry_err; } ret = sbromsw_toc1_traverse(); if(ret) { printf("sbromsw_entry sbromsw_toc1_traverse failed\n"); goto __sbromsw_entry_err; } __sbromsw_entry_err: #ifdef CONFIG_BOOT_A15 if(!(toc0_config->boot_cpu & 0xff00)) { sbromsw_clear_env(); boot0_jump(SUNXI_FEL_ADDR_IN_SECURE); } else { rtc_region_set_flag(SUNXI_RUN_EFEX_FLAG); sbromsw_clear_env(); watchdog_enable(); } #endif __sbromsw_entry_err0: sbromsw_clear_env(); boot0_jump(SUNXI_FEL_ADDR_IN_SECURE); }
/******************************************************************************* *函数名称: Boot0_C_part *函数原型:void Boot0_C_part( void ) *函数功能: Boot0中用C语言编写的部分的主流程 *入口参数: void *返 回 值: void *备 注: *******************************************************************************/ void main( void ) { __u32 status; __s32 dram_size; int ddr_aotu_scan = 0; int pwr_en = 0; __u32 fel_flag; __u32 boot_cpu=0; bias_calibration(); timer_init(); sunxi_serial_init( BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 6 ); if( BT0_head.prvt_head.enable_jtag ) { boot_set_gpio((normal_gpio_cfg *)BT0_head.prvt_head.jtag_gpio, 6, 1); } printf("HELLO! BOOT0 is starting!\n"); print_version(); #ifdef CONFIG_ARCH_SUN7I reset_cpux(1); #endif fel_flag = rtc_region_probe_fel_flag(); if(fel_flag == SUNXI_RUN_EFEX_FLAG) { rtc_region_clear_fel_flag(); printf("eraly jump fel\n"); goto __boot0_entry_err0; } #ifdef CONFIG_BOOT_A15 // printf("BT0_head.boot_head.boot_cpu=0x%x\n", BT0_head.boot_head.boot_cpu); // if(BT0_head.boot_head.boot_cpu) // { // fel_flag = BOOT_A7_FLAG; // } // else // { // fel_flag = BOOT_A15_FLAG; // } /* boot_cpu 含义 bit0~7 bit8~15 0:不需要保存标志位 1:当前应该切换a15启动 1:通知u-boot保存 0:当前应该切换a7启动 每次从brom读取的boot_cpu只能是0x100或者0 */ boot_cpu = BT0_head.boot_head.boot_cpu; pwr_en = BT0_head.boot_head.pwr_en; if(fel_flag == BOOT_A15_FLAG) { rtc_region_clear_fel_flag(); if(boot_cpu == 0x00) //如果原本是a7启动 boot_cpu = 0x101; //a15启动,需要保存标志位 switch_to_a15(pwr_en); } else if(fel_flag == BOOT_A7_FLAG) { rtc_region_clear_fel_flag(); if(boot_cpu == 0x100) //如果原本是a15启动 boot_cpu = 0x01; //a7启动,需要保存标志位 } else { if(boot_cpu == 0x100) { switch_to_a15(pwr_en); //a15启动,不需要保存标志位 } else { boot_cpu = 0x0; //a7启动,不需要保存标志位 } } // printf("BT0_head.boot_head.boot_cpu=0x%x\n", BT0_head.boot_head.boot_cpu); #endif mmu_setup(); ddr_aotu_scan = 0; dram_size = init_DRAM(ddr_aotu_scan, (void *)BT0_head.prvt_head.dram_para); if(dram_size) { //mdfs_save_value(); printf("dram size =%d\n", dram_size); } else { printf("initializing SDRAM Fail.\n"); goto __boot0_entry_err; } #if defined(CONFIG_ARCH_SUN9IW1P1) __msdelay(100); #endif #ifdef CONFIG_ARCH_SUN7I check_super_standby_flag(); #endif status = load_boot1(); printf("Ready to disable icache.\n"); mmu_turn_off( ); // disable instruction cache if( status == 0 ) { //跳转之前,把所有的dram参数写到boot1中 set_dram_para((void *)&BT0_head.prvt_head.dram_para, dram_size, boot_cpu); printf("Jump to secend Boot.\n"); boot0_jump(CONFIG_SYS_TEXT_BASE); // 如果载入Boot1成功,跳转到Boot1处执行 } __boot0_entry_err: #ifdef CONFIG_BOOT_A15 if(!(boot_cpu & 0xff00)) { boot0_clear_env(); boot0_jump(FEL_BASE); } else { rtc_region_set_flag(SUNXI_RUN_EFEX_FLAG); boot0_clear_env(); watchdog_enable(); } #endif __boot0_entry_err0: boot0_clear_env(); boot0_jump(FEL_BASE); }
void platform_init() { // Enable watchdog if requested if (platform_should_start_watchdog && platform_should_start_watchdog()) { watchdog_enable(WATCHDOG_DIVIDER_256, 0xFFF); } // Enable floating point *cm3_scb_get_CPACR() |= 0xF << 20; /* set CP10 and CP11 Full Access */ // Enable syscfg rcc_apb_enable(RCC_APB_BUS_SYSCFG, RCC_APB_BIT_SYSCFG); // At reset, HCLK is 16MHz, set flash latency to 5 wait state to handle 168MHz flash_set_latency(5); // Configure PLL to have 336MHz VCO, then 48MHz for USB and 168 MHz for sysclk rcc_pll_enable(RCC_PLL_SOURCE_HSI, 8, 168, RCC_PLL_MAIN_DIV_2, 7); // Now SYSCLK is at 168MHz, set AHB divider to 1, APB1 to 4 and APB2 to 4 /* * The frequency of the AHB domain is 168 MHz. * The frequency of the APBx domain is 42 MHz. */ rcc_sysclk_set_prescalers(RCC_SYSCLK_AHB_PRE_1, RCC_SYSCLK_APB_PRE_4, RCC_SYSCLK_APB_PRE_4); // Select PLL as SYSCLK source clock rcc_sysclk_select_source(RCC_SYSCLK_SOURCE_PLL); // Setup the drivers platform_drivers_setup(); // Setup the LEDs platform_leds_setup(); // Setup the libraries platform_lib_setup(); // Setup the peripherals platform_periph_setup(); // Setup the net stack platform_net_setup(); // Feed the random number generator random_init(uid->uid32[2]); log_printf( "HCLK @%uMHz, SYSTICK @%uMHz", rcc_sysclk_get_clock_frequency(RCC_SYSCLK_CLOCK_HCLK) / 1000000, rcc_sysclk_get_clock_frequency(RCC_SYSCLK_CLOCK_SYSTICK_CLK) / 1000000); log_printf("\n\nPlatform starting in "); uint32_t i; for (i = 1; i > 0; i--) { log_printf("%u... ", i); soft_timer_delay_s(1); } log_printf("\nGO!\n"); }
void setup(void) { unsigned char adr, flags, d; unsigned short i; unsigned char *p; _flkey = 0; /* first disable watchdog */ watchdog_disable(); /* avoid any blocking of RS485 bus */ RS485_ENABLE = RS485_ENABLE_OFF; /* Port and oscillator configuration */ #if defined(CPU_C8051F120) SFRPAGE = CONFIG_PAGE; XBR0 = 0x04; // Enable XBar, UART0 & UART1 XBR1 = 0x00; XBR2 = 0x44; #ifdef CLK_25MHZ /* Select internal quartz oscillator */ SFRPAGE = LEGACY_PAGE; FLSCL = 0x00; // set flash read time for <25 MHz SFRPAGE = CONFIG_PAGE; OSCICN = 0x83; // divide by 1 CLKSEL = 0x00; // select internal oscillator #else // 98 MHz /* Select internal quartz oscillator */ SFRPAGE = LEGACY_PAGE; FLSCL = 0xB0; // set flash read time for 100 MHz SFRPAGE = CONFIG_PAGE; OSCICN = 0x83; // divide by 1 CLKSEL = 0x00; // select internal oscillator PLL0CN |= 0x01; PLL0DIV = 0x01; PLL0FLT = 0x01; PLL0MUL = 0x04; for (i = 0 ; i < 15; i++); // Wait 5us for initialization PLL0CN |= 0x02; for (i = 0 ; i<50000 && ((PLL0CN & 0x10) == 0) ; i++); CLKSEL = 0x02; // select PLL as sysclk src #endif #elif defined(CPU_C8051F020) XBR0 = 0x04; // Enable UART0 & UART1 XBR1 = 0x00; XBR2 = 0x44; /* Select external quartz oscillator */ OSCXCN = 0x67; // Crystal mode, Power Factor 22E6 OSCICN = 0x08; // CLKSL=1 (external) #elif defined(CPU_C8051F310) || defined(CPU_C8051F320) XBR0 = 0x01; // Enable RX/TX XBR1 = 0x40; // Enable crossbar /* Select internal quartz oscillator */ OSCICN = 0x83; // IOSCEN=1, SYSCLK=24.5 MHz CLKSEL = 0x00; // derive SYSCLK from internal source #else XBR0 = 0x04; // Enable RX/TX XBR1 = 0x00; XBR2 = 0x40; // Enable crossbar PRT0CF = 0x01; // P0.0: TX = Push Pull PRT1CF = 0x00; // P1 PRT2CF = 0x00; // P2 Open drain for 5V LCD PRT3CF = 0x20; // P3.5: RS485 enable = Push Pull /* Select external quartz oscillator */ OSCXCN = 0x67; // Crystal mode, Power Factor 22E6 OSCICN = 0x08; // CLKSL=1 (external) #endif #ifdef CFG_HAVE_LCD lcd_setup(); #endif #ifdef CFG_HAVE_EMIF /* initialize external memory interface */ d = emif_init(); /* do memory test on cold start */ SFRPAGE = LEGACY_PAGE; if (d > 0 && (RSTSRC & 0x02) > 0) emif_test(d); #endif /* start system clock */ sysclock_init(); /* enable watchdog with default timeout */ watchdog_enable(0); /* enable missing clock detector */ RSTSRC |= 0x04; /* default LED mode */ for (i=0 ; i<N_LED ; i++) led_mode(i, 1); /* initialize all memory */ CSR = 0; addressed = 0; flash_param = 0; flash_program = 0; flash_allowed = 0; wrong_cpu = 0; _flkey = 0; #ifdef CFG_HAVE_RTC rtc_set = 0; #endif i_in = i_out = n_out = 0; _cur_sub_addr = 0; for (i=0 ; i<sizeof(in_buf) ; i++) in_buf[i] = 0; for (i=0 ; i<sizeof(out_buf) ; i++) out_buf[i] = 0; /* check if we got reset by watchdog */ #if defined(CPU_C8051F120) SFRPAGE = LEGACY_PAGE; #endif WD_RESET = ((RSTSRC & 0x02) == 0 && (RSTSRC & 0x08) > 0); /* initialize UART(s) */ uart_init(0, BD_115200); #ifdef CFG_UART1_MSCB uart_init(1, BD_115200); #endif #ifdef CFG_DYN_VARIABLES setup_variables(); #endif /* count variables */ for (n_variables = _var_size = 0;; n_variables++) { _var_size += variables[n_variables].width; if (variables[n_variables].width == 0) break; } /* check if variables are in xdata and xdata is present */ if (n_variables > 0) { p = variables[0].ud; d = *p; *p = 0x55; if (*p != 0x55) wrong_cpu = 1; *p = 0xAA; if (*p != 0xAA) wrong_cpu = 1; *p = d; } /* retrieve EEPROM data */ #ifdef CPU_C8051F120 SFRPAGE = LEGACY_PAGE; #endif if ((RSTSRC & 0x02) > 0) flags = eeprom_retrieve(1); // vars on cold start else flags = eeprom_retrieve(0); if ((flags & (1 << 0)) == 0) { configured_addr = 0; /* set initial values */ sys_info.node_addr = 0xFFFF; sys_info.group_addr = 0xFFFF; memset(sys_info.node_name, 0, sizeof(sys_info.node_name)); strncpy(sys_info.node_name, node_name, sizeof(sys_info.node_name)); } else configured_addr = 1; /* store SVN revision */ sys_info.svn_revision = (svn_rev_main[6]-'0')*1000+ (svn_rev_main[7]-'0')*100+ (svn_rev_main[8]-'0')*10+ (svn_rev_main[9]-'0'); if ((flags & (1 << 1)) == 0) { /* init variables */ for (i = 0; variables[i].width; i++) if (!(variables[i].flags & MSCBF_DATALESS)) { /* do it for each sub-address */ for (adr = 0 ; adr < _n_sub_addr ; adr++) { memset((char*)variables[i].ud + _var_size*adr, 0, variables[i].width); } } /* call user initialization routine with initialization */ user_init(1); /* write current variables to flash later in main routine */ configured_vars = 0; } else { /* call user initialization routine without initialization */ user_init(0); configured_vars = 1; } /* Blink LEDs */ for (i=0 ; i<N_LED ; i++) led_blink(i, 3, 150); }