The Ultiparc Project (https://github.com/skarpenko/ultiparc)


Ultiparc is a small 32-bit RISC microprocessor that implements subset of
MIPS-I (TM) instructions. The major goals of the project are primarily
educational.


PREREQUISITES

  Here is the list of prerequisites required to play with current sources:

  * SystemC v2.3.1 (http://accellera.org/). Hardware simulation language
    based on C++. Ultiparc system model is developed using this tool.
    SystemC must be properly installed in the system and SYSTEMC_HOME
    environment variable should be set to SystemC installation path.

  * GTK Wave (http://gtkwave.sourceforge.net/). GTK+ based wave viewer
    which could be used for waveforms visualization.

  * GNU C/C++ for MIPS-I ISA (http://gcc.gnu.org/). GNU C/C++ cross-compiler
    is required for building firmware examples and verification tests.

  * Icarus Verilog v10.0 (http://iverilog.icarus.com/). Verilog simulation
    tool which is used for running Ultiparc RTL simulation.

  * Verilator v3.874 (https://www.veripool.org/projects/verilator/). Verilator
    converts synthesizable Verilog code into C++ or SystemC code. It is required
    for building cycle accurate Ultiparc system model.


DIRECTORY STRUCTURE

  /
  |- slm        - system level modeling related sources.
  |- rtl        - Verilog sources.
  |- verif      - verification firmware.
  -- setenv.sh  - environment configuration script.


CONTACTS

  Stepan Karpenko
  e-mail (1): carp@mail.ru
  e-mail (2): stepan.karpenko@gmail.com