static void move_all_thermals (int old_index, int new_index) { VIA_LOOP (PCB->Data); { move_one_thermal (old_index, new_index, via); } END_LOOP; ALLPIN_LOOP (PCB->Data); { move_one_thermal (old_index, new_index, pin); } ENDALL_LOOP; }
DrillInfoTypePtr GetDrillInfo (DataTypePtr top) { DrillInfoTypePtr AllDrills; DrillTypePtr Drill = NULL; DrillType savedrill, swapdrill; bool DrillFound = false; bool NewDrill; AllDrills = (DrillInfoTypePtr)calloc (1, sizeof (DrillInfoType)); ALLPIN_LOOP (top); { if (!DrillFound) { DrillFound = true; Drill = GetDrillInfoDrillMemory (AllDrills); InitializeDrill (Drill, pin, element); } else { if (Drill->DrillSize == pin->DrillingHole) FillDrill (Drill, element, pin); else { NewDrill = false; DRILL_LOOP (AllDrills); { if (drill->DrillSize == pin->DrillingHole) { Drill = drill; FillDrill (Drill, element, pin); break; } else if (drill->DrillSize > pin->DrillingHole) { if (!NewDrill) { NewDrill = true; InitializeDrill (&swapdrill, pin, element); Drill = GetDrillInfoDrillMemory (AllDrills); Drill->DrillSize = pin->DrillingHole + 1; Drill = drill; } savedrill = *drill; *drill = swapdrill; swapdrill = savedrill; } } END_LOOP; if (AllDrills->Drill[AllDrills->DrillN - 1].DrillSize < pin->DrillingHole) { Drill = GetDrillInfoDrillMemory (AllDrills); InitializeDrill (Drill, pin, element); } } } } ENDALL_LOOP; VIA_LOOP (top); { if (!DrillFound) { DrillFound = true; Drill = GetDrillInfoDrillMemory (AllDrills); Drill->DrillSize = via->DrillingHole; FillDrill (Drill, NULL, via); } else { if (Drill->DrillSize != via->DrillingHole) { DRILL_LOOP (AllDrills); { if (drill->DrillSize == via->DrillingHole) { Drill = drill; FillDrill (Drill, NULL, via); break; } } END_LOOP; if (Drill->DrillSize != via->DrillingHole) { Drill = GetDrillInfoDrillMemory (AllDrills); Drill->DrillSize = via->DrillingHole; FillDrill (Drill, NULL, via); } } else FillDrill (Drill, NULL, via); } } END_LOOP; qsort (AllDrills->Drill, AllDrills->DrillN, sizeof (DrillType), DrillQSort); return (AllDrills); }
static bool CheckShorts (LibraryMenuType *theNet) { bool newone, warn = false; PointerListType *generic = (PointerListType *)calloc (1, sizeof (PointerListType)); /* the first connection was starting point so * the menu is always non-null */ void **menu = GetPointerMemory (generic); *menu = theNet; ALLPIN_LOOP (PCB->Data); { if (TEST_FLAG (DRCFLAG, pin)) { warn = true; if (!pin->Spare) { Message (_("Warning! Net \"%s\" is shorted to %s pin %s\n"), &theNet->Name[2], UNKNOWN (NAMEONPCB_NAME (element)), UNKNOWN (pin->Number)); SET_FLAG (WARNFLAG, pin); continue; } newone = true; POINTER_LOOP (generic); { if (*ptr == pin->Spare) { newone = false; break; } } END_LOOP; if (newone) { menu = GetPointerMemory (generic); *menu = pin->Spare; Message (_("Warning! Net \"%s\" is shorted to net \"%s\"\n"), &theNet->Name[2], &((LibraryMenuType *) (pin->Spare))->Name[2]); SET_FLAG (WARNFLAG, pin); } } } ENDALL_LOOP; ALLPAD_LOOP (PCB->Data); { if (TEST_FLAG (DRCFLAG, pad)) { warn = true; if (!pad->Spare) { Message (_("Warning! Net \"%s\" is shorted to %s pad %s\n"), &theNet->Name[2], UNKNOWN (NAMEONPCB_NAME (element)), UNKNOWN (pad->Number)); SET_FLAG (WARNFLAG, pad); continue; } newone = true; POINTER_LOOP (generic); { if (*ptr == pad->Spare) { newone = false; break; } } END_LOOP; if (newone) { menu = GetPointerMemory (generic); *menu = pad->Spare; Message (_("Warning! Net \"%s\" is shorted to net \"%s\"\n"), &theNet->Name[2], &((LibraryMenuType *) (pad->Spare))->Name[2]); SET_FLAG (WARNFLAG, pad); } } } ENDALL_LOOP; FreePointerListMemory (generic); free (generic); return (warn); }
/*! * \brief Read the library-netlist build a true Netlist structure. */ NetListType * ProcNetlist (LibraryType *net_menu) { ConnectionType *connection; ConnectionType LastPoint; NetType *net; static NetListType *Wantlist = NULL; if (!net_menu->MenuN) return (NULL); FreeNetListMemory (Wantlist); free (Wantlist); badnet = false; /* find layer groups of the component side and solder side */ bottom_group = GetLayerGroupNumberBySide (BOTTOM_SIDE); top_group = GetLayerGroupNumberBySide (TOP_SIDE); Wantlist = (NetListType *)calloc (1, sizeof (NetListType)); if (Wantlist) { ALLPIN_LOOP (PCB->Data); { pin->Spare = NULL; CLEAR_FLAG (DRCFLAG, pin); } ENDALL_LOOP; ALLPAD_LOOP (PCB->Data); { pad->Spare = NULL; CLEAR_FLAG (DRCFLAG, pad); } ENDALL_LOOP; MENU_LOOP (net_menu); { if (menu->Name[0] == '*' || menu->flag == 0) { badnet = true; continue; } net = GetNetMemory (Wantlist); if (menu->Style) { STYLE_LOOP (PCB); { if (style->Name && !NSTRCMP (style->Name, menu->Style)) { net->Style = style; break; } } END_LOOP; } else /* default to NULL if none found */ net->Style = NULL; ENTRY_LOOP (menu); { if (SeekPad (entry, &LastPoint, false)) { if (TEST_FLAG (DRCFLAG, (PinType *) LastPoint.ptr2)) Message (_ ("Error! Element %s pin %s appears multiple times in the netlist file.\n"), NAMEONPCB_NAME ((ElementType *) LastPoint.ptr1), (LastPoint.type == PIN_TYPE) ? ((PinType *) LastPoint.ptr2)-> Number : ((PadType *) LastPoint.ptr2)->Number); else { connection = GetConnectionMemory (net); *connection = LastPoint; /* indicate expect net */ connection->menu = menu; /* mark as visited */ SET_FLAG (DRCFLAG, (PinType *) LastPoint.ptr2); if (LastPoint.type == PIN_TYPE) ((PinType *) LastPoint.ptr2)->Spare = (void *) menu; else ((PadType *) LastPoint.ptr2)->Spare = (void *) menu; } } else badnet = true; /* check for more pins with the same number */ for (; SeekPad (entry, &LastPoint, true);) { connection = GetConnectionMemory (net); *connection = LastPoint; /* indicate expect net */ connection->menu = menu; /* mark as visited */ SET_FLAG (DRCFLAG, (PinType *) LastPoint.ptr2); if (LastPoint.type == PIN_TYPE) ((PinType *) LastPoint.ptr2)->Spare = (void *) menu; else ((PadType *) LastPoint.ptr2)->Spare = (void *) menu; } } END_LOOP; } END_LOOP; } /* clear all visit marks */ ALLPIN_LOOP (PCB->Data); { CLEAR_FLAG (DRCFLAG, pin); } ENDALL_LOOP; ALLPAD_LOOP (PCB->Data); { CLEAR_FLAG (DRCFLAG, pad); } ENDALL_LOOP; return (Wantlist); }
/* --------------------------------------------------------------------------- * flip components/tracks from one side to the other */ static void SwapBuffer (BufferType *Buffer) { int j, k; Cardinal sgroup, cgroup; LayerType swap; ELEMENT_LOOP (Buffer->Data); { r_delete_element (Buffer->Data, element); MirrorElementCoordinates (Buffer->Data, element, 0); } END_LOOP; /* set buffer offset to 'mark' position */ Buffer->X = SWAP_X (Buffer->X); Buffer->Y = SWAP_Y (Buffer->Y); VIA_LOOP (Buffer->Data); { r_delete_entry (Buffer->Data->via_tree, (BoxType *)via); via->X = SWAP_X (via->X); via->Y = SWAP_Y (via->Y); SetPinBoundingBox (via); r_insert_entry (Buffer->Data->via_tree, (BoxType *)via, 0); } END_LOOP; ALLLINE_LOOP (Buffer->Data); { r_delete_entry (layer->line_tree, (BoxType *)line); line->Point1.X = SWAP_X (line->Point1.X); line->Point1.Y = SWAP_Y (line->Point1.Y); line->Point2.X = SWAP_X (line->Point2.X); line->Point2.Y = SWAP_Y (line->Point2.Y); SetLineBoundingBox (line); r_insert_entry (layer->line_tree, (BoxType *)line, 0); } ENDALL_LOOP; ALLARC_LOOP (Buffer->Data); { r_delete_entry (layer->arc_tree, (BoxType *)arc); arc->X = SWAP_X (arc->X); arc->Y = SWAP_Y (arc->Y); arc->StartAngle = SWAP_ANGLE (arc->StartAngle); arc->Delta = SWAP_DELTA (arc->Delta); SetArcBoundingBox (arc); r_insert_entry (layer->arc_tree, (BoxType *)arc, 0); } ENDALL_LOOP; ALLPOLYGON_LOOP (Buffer->Data); { r_delete_entry (layer->polygon_tree, (BoxType *)polygon); POLYGONPOINT_LOOP (polygon); { point->X = SWAP_X (point->X); point->Y = SWAP_Y (point->Y); } END_LOOP; SetPolygonBoundingBox (polygon); r_insert_entry (layer->polygon_tree, (BoxType *)polygon, 0); /* hmmm, how to handle clip */ } ENDALL_LOOP; ALLTEXT_LOOP (Buffer->Data); { r_delete_entry (layer->text_tree, (BoxType *)text); text->X = SWAP_X (text->X); text->Y = SWAP_Y (text->Y); TOGGLE_FLAG (ONSOLDERFLAG, text); SetTextBoundingBox (&PCB->Font, text); r_insert_entry (layer->text_tree, (BoxType *)text, 0); } ENDALL_LOOP; /* swap silkscreen layers */ swap = Buffer->Data->Layer[solder_silk_layer]; Buffer->Data->Layer[solder_silk_layer] = Buffer->Data->Layer[component_silk_layer]; Buffer->Data->Layer[component_silk_layer] = swap; /* swap layer groups when balanced */ sgroup = GetLayerGroupNumberByNumber (solder_silk_layer); cgroup = GetLayerGroupNumberByNumber (component_silk_layer); if (PCB->LayerGroups.Number[cgroup] == PCB->LayerGroups.Number[sgroup]) { for (j = k = 0; j < PCB->LayerGroups.Number[sgroup]; j++) { int t1, t2; Cardinal cnumber = PCB->LayerGroups.Entries[cgroup][k]; Cardinal snumber = PCB->LayerGroups.Entries[sgroup][j]; if (snumber >= max_copper_layer) continue; swap = Buffer->Data->Layer[snumber]; while (cnumber >= max_copper_layer) { k++; cnumber = PCB->LayerGroups.Entries[cgroup][k]; } Buffer->Data->Layer[snumber] = Buffer->Data->Layer[cnumber]; Buffer->Data->Layer[cnumber] = swap; k++; /* move the thermal flags with the layers */ ALLPIN_LOOP (Buffer->Data); { t1 = TEST_THERM (snumber, pin); t2 = TEST_THERM (cnumber, pin); ASSIGN_THERM (snumber, t2, pin); ASSIGN_THERM (cnumber, t1, pin); } ENDALL_LOOP; VIA_LOOP (Buffer->Data); { t1 = TEST_THERM (snumber, via); t2 = TEST_THERM (cnumber, via); ASSIGN_THERM (snumber, t2, via); ASSIGN_THERM (cnumber, t1, via); } END_LOOP; } } SetBufferBoundingBox (Buffer); SetCrosshairRangeToBuffer (); }
bool SelectObjectByName (int Type, char *Pattern, bool Flag) { bool changed = false; #if defined(HAVE_REGCOMP) #define REGEXEC(arg) (regexec_match_all(&compiled, (arg))) int result; regex_t compiled; /* compile the regular expression */ result = regcomp (&compiled, Pattern, REG_EXTENDED | REG_ICASE); if (result) { char errorstring[128]; regerror (result, &compiled, errorstring, 128); Message (_("regexp error: %s\n"), errorstring); regfree (&compiled); return (false); } #else #define REGEXEC(arg) (re_exec((arg)) == 1) char *compiled; /* compile the regular expression */ if ((compiled = re_comp (Pattern)) != NULL) { Message (_("re_comp error: %s\n"), compiled); return (false); } #endif /* loop over all visible objects with names */ if (Type & TEXT_TYPE) ALLTEXT_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, text) && TEXT_IS_VISIBLE (PCB, layer, text) && text->TextString && REGEXEC (text->TextString) && TEST_FLAG (SELECTEDFLAG, text) != Flag) { AddObjectToFlagUndoList (TEXT_TYPE, layer, text, text); ASSIGN_FLAG (SELECTEDFLAG, Flag, text); DrawText (layer, text, 0); changed = true; } } ENDALL_LOOP; if (PCB->ElementOn && (Type & ELEMENT_TYPE)) ELEMENT_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, element) && ((TEST_FLAG (ONSOLDERFLAG, element) != 0) == SWAP_IDENT || PCB->InvisibleObjectsOn) && TEST_FLAG (SELECTEDFLAG, element) != Flag) { String name = ELEMENT_NAME (PCB, element); if (name && REGEXEC (name)) { AddObjectToFlagUndoList (ELEMENT_TYPE, element, element, element); ASSIGN_FLAG (SELECTEDFLAG, Flag, element); PIN_LOOP (element); { AddObjectToFlagUndoList (PIN_TYPE, element, pin, pin); ASSIGN_FLAG (SELECTEDFLAG, Flag, pin); } END_LOOP; PAD_LOOP (element); { AddObjectToFlagUndoList (PAD_TYPE, element, pad, pad); ASSIGN_FLAG (SELECTEDFLAG, Flag, pad); } END_LOOP; ELEMENTTEXT_LOOP (element); { AddObjectToFlagUndoList (ELEMENTNAME_TYPE, element, text, text); ASSIGN_FLAG (SELECTEDFLAG, Flag, text); } END_LOOP; DrawElementName (element, 0); DrawElement (element, 0); changed = true; } } } END_LOOP; if (PCB->PinOn && (Type & PIN_TYPE)) ALLPIN_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, element) && pin->Name && REGEXEC (pin->Name) && TEST_FLAG (SELECTEDFLAG, pin) != Flag) { AddObjectToFlagUndoList (PIN_TYPE, element, pin, pin); ASSIGN_FLAG (SELECTEDFLAG, Flag, pin); DrawPin (pin, 0); changed = true; } } ENDALL_LOOP; if (PCB->PinOn && (Type & PAD_TYPE)) ALLPAD_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, element) && ((TEST_FLAG (ONSOLDERFLAG, pad) != 0) == SWAP_IDENT || PCB->InvisibleObjectsOn) && TEST_FLAG (SELECTEDFLAG, pad) != Flag) if (pad->Name && REGEXEC (pad->Name)) { AddObjectToFlagUndoList (PAD_TYPE, element, pad, pad); ASSIGN_FLAG (SELECTEDFLAG, Flag, pad); DrawPad (pad, 0); changed = true; } } ENDALL_LOOP; if (PCB->ViaOn && (Type & VIA_TYPE)) VIA_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, via) && via->Name && REGEXEC (via->Name) && TEST_FLAG (SELECTEDFLAG, via) != Flag) { AddObjectToFlagUndoList (VIA_TYPE, via, via, via); ASSIGN_FLAG (SELECTEDFLAG, Flag, via); DrawVia (via, 0); changed = true; } } END_LOOP; #if defined(HAVE_REGCOMP) #if !defined(sgi) regfree (&compiled); #endif #endif if (changed) { IncrementUndoSerialNumber (); Draw (); } return (changed); }
/* ---------------------------------------------------------------------- * selects/unselects all objects which were found during a connection scan * Flag determines if they are to be selected or unselected * returns true if the state of any object has changed * * text objects and elements cannot be selected by this routine */ bool SelectConnection (bool Flag) { bool changed = false; if (PCB->RatOn) RAT_LOOP (PCB->Data); { if (TEST_FLAG (FOUNDFLAG, line)) { AddObjectToFlagUndoList (RATLINE_TYPE, line, line, line); ASSIGN_FLAG (SELECTEDFLAG, Flag, line); DrawRat (line, 0); changed = true; } } END_LOOP; VISIBLELINE_LOOP (PCB->Data); { if (TEST_FLAG (FOUNDFLAG, line) && !TEST_FLAG (LOCKFLAG, line)) { AddObjectToFlagUndoList (LINE_TYPE, layer, line, line); ASSIGN_FLAG (SELECTEDFLAG, Flag, line); DrawLine (layer, line, 0); changed = true; } } ENDALL_LOOP; VISIBLEARC_LOOP (PCB->Data); { if (TEST_FLAG (FOUNDFLAG, arc) && !TEST_FLAG (LOCKFLAG, arc)) { AddObjectToFlagUndoList (ARC_TYPE, layer, arc, arc); ASSIGN_FLAG (SELECTEDFLAG, Flag, arc); DrawArc (layer, arc, 0); changed = true; } } ENDALL_LOOP; VISIBLEPOLYGON_LOOP (PCB->Data); { if (TEST_FLAG (FOUNDFLAG, polygon) && !TEST_FLAG (LOCKFLAG, polygon)) { AddObjectToFlagUndoList (POLYGON_TYPE, layer, polygon, polygon); ASSIGN_FLAG (SELECTEDFLAG, Flag, polygon); DrawPolygon (layer, polygon, 0); changed = true; } } ENDALL_LOOP; if (PCB->PinOn && PCB->ElementOn) { ALLPIN_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, element) && TEST_FLAG (FOUNDFLAG, pin)) { AddObjectToFlagUndoList (PIN_TYPE, element, pin, pin); ASSIGN_FLAG (SELECTEDFLAG, Flag, pin); DrawPin (pin, 0); changed = true; } } ENDALL_LOOP; ALLPAD_LOOP (PCB->Data); { if (!TEST_FLAG (LOCKFLAG, element) && TEST_FLAG (FOUNDFLAG, pad)) { AddObjectToFlagUndoList (PAD_TYPE, element, pad, pad); ASSIGN_FLAG (SELECTEDFLAG, Flag, pad); DrawPad (pad, 0); changed = true; } } ENDALL_LOOP; } if (PCB->ViaOn) VIA_LOOP (PCB->Data); { if (TEST_FLAG (FOUNDFLAG, via) && !TEST_FLAG (LOCKFLAG, via)) { AddObjectToFlagUndoList (VIA_TYPE, via, via, via); ASSIGN_FLAG (SELECTEDFLAG, Flag, via); DrawVia (via, 0); changed = true; } } END_LOOP; Draw (); return (changed); }