unsigned check_reboot_mode(void)
{
unsigned rst_mode= 0;
rst_mode = ANA_REG_GET(ANA_HWRST_STATUS);
rst_mode &= HWRST_STATUS_POWERON_MASK;
ANA_REG_SET(ANA_HWRST_STATUS, 0); //clear flag
if(rst_mode == HWRST_STATUS_RECOVERY)
return RECOVERY_MODE;
else if(rst_mode == HWRST_STATUS_FASTBOOT)
return FASTBOOT_MODE;
else if(rst_mode == HWRST_STATUS_NORMAL)
return NORMAL_MODE;
else if(rst_mode == HWRST_STATUS_NORMAL2)
return WATCHDOG_REBOOT;
else if(rst_mode == HWRST_STATUS_PANIC)
return PANIC_REBOOT;
else if(rst_mode == HWRST_STATUS_SPECIAL)
return SPECIAL_MODE;
else if(rst_mode == HWRST_STATUS_ALARM)
return ALARM_MODE;
else if(rst_mode == HWRST_STATUS_SLEEP)
return SLEEP_MODE;
else
return 0;
}
static void ldo_set_exxtl(struct ldo_lowpower_cfg *cfg, struct ldo_reg_bit *reg)
{
unsigned int v = 0, tmp = 0;
unsigned int shft = 0;
if (reg->ext_xtl_reg != -1) {
shft = __ffs(reg->ext_xtl_reg_bitmsk);
if (cfg->select_by_ext_xtl & BY_EXT_XTL0)
v |= BIT(0);
if (cfg->select_by_ext_xtl & BY_EXT_XTL1)
v |= BIT(1);
/* no xtl1 in 7715 */
/*if (cfg->select_by_ext_xtl & BY_EXT_XTL2)
v |= BIT(2);*/
v = v << shft;
v &= reg->ext_xtl_reg_bitmsk;
tmp = ANA_REG_GET(reg->ext_xtl_reg);
tmp &= ~reg->ext_xtl_reg_bitmsk;
tmp |= v;
ANA_REG_SET(reg->ext_xtl_reg, tmp);
}
}
void sprd_rtc_set_sec(unsigned long secs)
{
unsigned sec, min, hour, day;
unsigned set_mask = 0, int_rsts;
unsigned long temp;
sec = secs % 60;
temp = (secs - sec)/60;
min = temp%60;
temp = (temp - min)/60;
hour = temp%24;
temp = (temp - hour)/24;
day = temp;
ANA_REG_OR(ANA_RTC_INT_CLR, RTC_UPD_TIME_MASK);
if(sec != get_sec()){
ANA_REG_SET(ANA_RTC_SEC_UPDATE, sec);
set_mask |= RTC_SEC_ACK_BIT;
}
if(min != get_min()){
ANA_REG_SET(ANA_RTC_MIN_UPDATE, min);
set_mask |= RTC_MIN_ACK_BIT;
}
if(hour != get_hour()){
ANA_REG_SET(ANA_RTC_HOUR_UPDATE, hour);
set_mask |= RTC_HOUR_ACK_BIT;
}
if(day != get_day()){
ANA_REG_SET(ANA_RTC_DAY_UPDATE, day);
set_mask |= RTC_DAY_ACK_BIT;
}
//wait till all update done
do{
int_rsts = ANA_REG_GET(ANA_RTC_INT_RSTS) & RTC_UPD_TIME_MASK;
if(set_mask == int_rsts)
break;
}while(1);
ANA_REG_OR(ANA_RTC_INT_CLR, RTC_UPD_TIME_MASK);
return;
}
void LDO_TurnOffAllLDO(void)
{
unsigned int reg_val;
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
do{
reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
}while(reg_val == 0);
ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,0x0FFF);
ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,0x7FFF);
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x0000));
//never return here and wait power down action
while(1);
}
void sprd_rtc_set_alarm_sec(unsigned long secs)
{
unsigned sec, min, hour, day;
unsigned long temp;
sec = secs % 60;
temp = (secs - sec)/60;
min = temp%60;
temp = (temp - min)/60;
hour = temp%24;
temp = (temp - hour)/24;
day = temp;
ANA_REG_SET(ANA_RTC_SEC_ALM, sec);
ANA_REG_SET(ANA_RTC_MIN_ALM, min);
ANA_REG_SET(ANA_RTC_HOUR_ALM, hour);
ANA_REG_SET(ANA_RTC_DAY_ALM, day);
return;
}
static void wr_prot_dis(void)
{
unsigned int reg_val = 0;
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
BITS_PWR_WR_PROT_VALUE(0x6e7f));
do{
reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE)
& BIT_PWR_WR_PROT);
}while(reg_val == 0);
}
static void lowpower_earlyinit(void)
{
unsigned int reg_val;
ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
BIT_DCDC_TOP_CLKF_EN|BIT_DCDC_TOP_OSC_EN);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0, BIT_SLP_IO_EN);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1, BIT_SLP_LDO_PD_EN);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN);
CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,0x1FFF81);
reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
reg_val &= ~BITS_DCDC_CORE_CTL_DS_SW(7);
reg_val |= BITS_DCDC_CORE_CTL_DS_SW(4);
ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL0,reg_val);
ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,0x0908);
/*plls wait, xtl0/1 wait, xtlbuf0/1 wait time*/
if (ANA_GET_CHIP_ID() != 0x2711a000) {
CHIP_REG_SET(REG_AON_CLK_FM_CFG,
//BIT_CLK_FM_PAD_SEL |
//BIT_CLK_FM_SEL |
0 );
CHIP_REG_SET(REG_AON_APB_GPS_26M_REF_SEL,
//BIT_XTLBUF1_GPS_SEL |
BIT_XTLBUF0_GPS_SEL |
//BIT_GPS_26M_REF_SEL |
0 );
}
}
void alarm_mode(void)
{
printf("%s\n", __func__);
unsigned rst_mode = 0;
rst_mode = 0;
ANA_REG_SET(ANA_HWRST_STATUS, rst_mode);
#if BOOT_NATIVE_LINUX
vlx_nand_boot(BOOT_PART, CONFIG_BOOTARGS " androidboot.mode=alarm", BACKLIGHT_OFF);
#else
vlx_nand_boot(BOOT_PART, "androidboot.mode=alarm", BACKLIGHT_OFF);
#endif
}
//MFP_ANA_CFG_X(CHIP_RSTN, AF0, DS1, F_PULL_DOWN,S_PULL_UP, IO_IE);
int charger_connected(void)
{
#if 0 //mingwei
struct gpio_chip chg_chip;
sprd_mfp_config(&chg_gpio_cfg, 1);
sprd_gpio_request(&chg_chip, CHG_GPIO_NUM);
sprd_gpio_direction_input(&chg_chip,CHG_GPIO_NUM);
return sprd_gpio_get(&chg_chip, CHG_GPIO_NUM);
#else
ANA_REG_OR(ANA_APB_CLK_EN, BIT_3|BIT_11);
ANA_REG_SET(ADI_EIC_MASK, 0xff);
udelay(3000);
int status = ANA_REG_GET(ADI_EIC_DATA);
//printf("charger_connected eica status %x\n", status);
return !!(status & (1 << 2));
#endif
}
int power_button_pressed(void)
{
#if 0
struct gpio_chip power_button_chip;
sprd_gpio_init();
sprd_mfp_config(&pwr_gpio_cfg, 1);
sprd_gpio_request(&power_button_chip, POWER_BUTTON_GPIO_NUM);
sprd_gpio_direction_input(&power_button_chip,POWER_BUTTON_GPIO_NUM);
return sprd_gpio_get(&power_button_chip, POWER_BUTTON_GPIO_NUM);
#else
ANA_REG_OR(ANA_APB_CLK_EN, BIT_3|BIT_11);
ANA_REG_SET(ADI_EIC_MASK, 0xff);
udelay(3000);
int status = ANA_REG_GET(ADI_EIC_DATA);
//printf("eica status %x\n", status);
return !!(status & (1 << 3)/*PBINT*/);//low level if pb hold
#endif
}
int charger_connected(void)
{
#if 1
static int init_done = 0;
if(init_done == 0){
gpio_request(EIC_CHARGER_DETECT, "charger_key");
gpio_direction_input(EIC_CHARGER_DETECT);
init_done = 1;
}
return !! gpio_get_value_cansleep(EIC_CHARGER_DETECT);
#else
ANA_REG_OR(ANA_APB_CLK_EN, BIT_3|BIT_11);
ANA_REG_SET(ADI_EIC_MASK, 0xff);
udelay(3000);
int status = ANA_REG_GET(ADI_EIC_DATA);
//printf("charger_connected eica status %x\n", status);
return !!(status & (1 << 2));
#endif
}
void reboot_devices(unsigned reboot_mode)
{
unsigned rst_mode = 0;
if(reboot_mode == RECOVERY_MODE){
rst_mode = HWRST_STATUS_RECOVERY;
}
else if(reboot_mode == FASTBOOT_MODE){
rst_mode = HWRST_STATUS_FASTBOOT;
}else if(reboot_mode == NORMAL_MODE){
rst_mode = HWRST_STATUS_NORMAL;
}else{
rst_mode = 0;
}
ANA_REG_SET(ANA_HWRST_STATUS, rst_mode);
reset_cpu(0);
#if 0
asm volatile("ldr r1,=0x20900218"); //remap ROM to 0x0000_0000
asm volatile("ldr r2,=1");
asm volatile("str r2,[r1]");
asm volatile("mov pc,#0");
#endif
}
int power_button_pressed(void)
{
#if 1
static int init_done = 0;
if(init_done == 0){
gpio_request(EIC_KEY_POWER, "power_key");
gpio_direction_input(EIC_KEY_POWER);
init_done = 1;
}
return ! gpio_get_value_cansleep(EIC_KEY_POWER);
#else
ANA_REG_OR(ANA_APB_CLK_EN, BIT_3|BIT_11);
ANA_REG_SET(ADI_EIC_MASK, 0xff);
udelay(3000);
int status = ANA_REG_GET(ADI_EIC_DATA);
//printf("eica status %x\n", status);
#if !(defined (CONFIG_SC8825))
return !!(status & (1 << 3)/*PBINT*/);//low level if pb hold
#else
return !(status & (1 << 3)/*PBINT*/);
#endif
#endif
}
void init_ldo_sleep_gr(void)
{
unsigned int reg_val;
#if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
BITS_PWR_WR_PROT_VALUE(0x5e6f) |
0
);
while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) == BIT_PWR_WR_PROT);
ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
BIT_LDO_EMM_PD |
//BIT_DCDC_TOPCLK6M_PD |
//BIT_DCDC_RF_PD |
//BIT_DCDC_GEN_PD |
//BIT_DCDC_MEM_PD |
//BIT_DCDC_ARM_PD |
//BIT_DCDC_CORE_PD |
//BIT_LDO_RF0_PD |
//BIT_LDO_EMMCCORE_PD |
//BIT_LDO_GEN1_PD |
//BIT_LDO_DCXO_PD |
//BIT_LDO_GEN0_PD |
//BIT_LDO_VDD25_PD |
//BIT_LDO_VDD28_PD |
//BIT_LDO_VDD18_PD |
//BIT_BG_PD |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,
BITS_PWR_WR_PROT_VALUE(0x0000) |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL,
BIT_LDO_LPREF_PD_SW |
BIT_DCDC_WPA_PD |
BIT_DCDC_CON_PD |
BIT_LDO_WIFIPA_PD |
BIT_LDO_SDCORE_PD |
BIT_LDO_USB_PD |
BIT_LDO_CAMMOT_PD |
BIT_LDO_CAMIO_PD |
BIT_LDO_CAMD_PD |
BIT_LDO_CAMA_PD |
BIT_LDO_SIM2_PD |
//BIT_LDO_SIM1_PD |
//BIT_LDO_SIM0_PD |
//BIT_LDO_SDIO_PD |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
BIT_SLP_IO_EN |
BIT_SLP_DCDCRF_PD_EN |
BIT_SLP_DCDCCON_PD_EN |
//BIT_SLP_DCDCGEN_PD_EN |
BIT_SLP_DCDCWPA_PD_EN |
BIT_SLP_DCDCARM_PD_EN |
BIT_SLP_LDOVDD25_PD_EN |
BIT_SLP_LDORF0_PD_EN |
BIT_SLP_LDOEMMCCORE_PD_EN |
BIT_SLP_LDOGEN0_PD_EN |
BIT_SLP_LDODCXO_PD_EN |
//BIT_SLP_LDOGEN1_PD_EN |
BIT_SLP_LDOWIFIPA_PD_EN |
//BIT_SLP_LDOVDD28_PD_EN |
//BIT_SLP_LDOVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
BIT_SLP_LDO_PD_EN |
BIT_SLP_LDOLPREF_PD_EN |
BIT_SLP_LDOSDCORE_PD_EN |
BIT_SLP_LDOUSB_PD_EN |
BIT_SLP_LDOCAMMOT_PD_EN |
BIT_SLP_LDOCAMIO_PD_EN |
BIT_SLP_LDOCAMD_PD_EN |
BIT_SLP_LDOCAMA_PD_EN |
BIT_SLP_LDOSIM2_PD_EN |
//BIT_SLP_LDOSIM1_PD_EN |
//BIT_SLP_LDOSIM0_PD_EN |
BIT_SLP_LDOSDIO_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
//BIT_SLP_DCDCRF_LP_EN |
//BIT_SLP_DCDCCON_LP_EN |
//BIT_SLP_DCDCCORE_LP_EN |
//BIT_SLP_DCDCMEM_LP_EN |
//BIT_SLP_DCDCARM_LP_EN |
//BIT_SLP_DCDCGEN_LP_EN |
//BIT_SLP_DCDCWPA_LP_EN |
//BIT_SLP_LDORF0_LP_EN |
//BIT_SLP_LDOEMMCCORE_LP_EN |
//BIT_SLP_LDOGEN0_LP_EN |
//BIT_SLP_LDODCXO_LP_EN |
//BIT_SLP_LDOGEN1_LP_EN |
//BIT_SLP_LDOWIFIPA_LP_EN |
//BIT_SLP_LDOVDD28_LP_EN |
//BIT_SLP_LDOVDD18_LP_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
//BIT_SLP_BG_LP_EN |
//BIT_LDOVDD25_LP_EN_SW |
//BIT_LDOSDCORE_LP_EN_SW |
//BIT_LDOUSB_LP_EN_SW |
//BIT_SLP_LDOVDD25_LP_EN |
//BIT_SLP_LDOSDCORE_LP_EN |
//BIT_SLP_LDOUSB_LP_EN |
//BIT_SLP_LDOCAMMOT_LP_EN |
//BIT_SLP_LDOCAMIO_LP_EN |
//BIT_SLP_LDOCAMD_LP_EN |
//BIT_SLP_LDOCAMA_LP_EN |
//BIT_SLP_LDOSIM2_LP_EN |
//BIT_SLP_LDOSIM1_LP_EN |
//BIT_SLP_LDOSIM0_LP_EN |
//BIT_SLP_LDOSDIO_LP_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4,
//BIT_LDOCAMIO_LP_EN_SW |
//BIT_LDOCAMMOT_LP_EN_SW |
//BIT_LDOCAMD_LP_EN_SW |
//BIT_LDOCAMA_LP_EN_SW |
//BIT_LDOSIM2_LP_EN_SW |
//BIT_LDOSIM1_LP_EN_SW |
//BIT_LDOSIM0_LP_EN_SW |
//BIT_LDOSDIO_LP_EN_SW |
//BIT_LDORF0_LP_EN_SW |
//BIT_LDOEMMCCORE_LP_EN_SW |
//BIT_LDOGEN0_LP_EN_SW |
//BIT_LDODCXO_LP_EN_SW |
//BIT_LDOGEN1_LP_EN_SW |
//BIT_LDOWIFIPA_LP_EN_SW |
//BIT_LDOVDD28_LP_EN_SW |
//BIT_LDOVDD18_LP_EN_SW |
0
);
ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
BIT_SLP_XTLBUF_PD_EN |
BIT_XTL_EN |
BITS_XTL_WAIT(0x32) |
0
);
/****************************************
* Following is CP LDO Sleep Control *
****************************************/
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
BIT_LDO_XTL_EN |
//BIT_LDO_GEN0_EXT_XTL0_EN |
//BIT_LDO_GEN0_XTL1_EN |
BIT_LDO_GEN0_XTL0_EN |
//BIT_LDO_GEN1_EXT_XTL0_EN |
//BIT_LDO_GEN1_XTL1_EN |
//BIT_LDO_GEN1_XTL0_EN |
BIT_LDO_DCXO_EXT_XTL0_EN |
BIT_LDO_DCXO_XTL1_EN |
BIT_LDO_DCXO_XTL0_EN |
//BIT_LDO_VDD18_EXT_XTL0_EN |
//BIT_LDO_VDD18_XTL1_EN |
//BIT_LDO_VDD18_XTL0_EN |
//BIT_LDO_VDD28_EXT_XTL0_EN |
//BIT_LDO_VDD28_XTL1_EN |
//BIT_LDO_VDD28_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
BIT_LDO_RF0_EXT_XTL0_EN |
BIT_LDO_RF0_XTL1_EN |
BIT_LDO_RF0_XTL0_EN |
BIT_LDO_WIFIPA_EXT_XTL0_EN |
BIT_LDO_WIFIPA_XTL1_EN |
BIT_LDO_WIFIPA_XTL0_EN |
//BIT_LDO_SIM2_EXT_XTL0_EN |
//BIT_LDO_SIM2_XTL1_EN |
//BIT_LDO_SIM2_XTL0_EN |
BIT_LDO_SIM1_EXT_XTL0_EN |
BIT_LDO_SIM1_XTL1_EN |
BIT_LDO_SIM1_XTL0_EN |
BIT_LDO_SIM0_EXT_XTL0_EN |
BIT_LDO_SIM0_XTL1_EN |
BIT_LDO_SIM0_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
BIT_LDO_VDD25_EXT_XTL0_EN |
BIT_LDO_VDD25_XTL1_EN |
BIT_LDO_VDD25_XTL0_EN |
BIT_DCDC_RF_EXT_XTL0_EN |
BIT_DCDC_RF_XTL1_EN |
BIT_DCDC_RF_XTL0_EN |
BIT_XO_EXT_XTL0_EN |
BIT_XO_XTL1_EN |
BIT_XO_XTL0_EN |
BIT_BG_EXT_XTL0_EN |
BIT_BG_XTL1_EN |
BIT_BG_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
BIT_DCDC_CON_EXT_XTL0_EN |
BIT_DCDC_CON_XTL1_EN |
BIT_DCDC_CON_XTL0_EN |
BIT_DCDC_WPA_EXT_XTL0_EN |
BIT_DCDC_WPA_XTL1_EN |
BIT_DCDC_WPA_XTL0_EN |
BIT_DCDC_MEM_EXT_XTL0_EN |
BIT_DCDC_MEM_XTL1_EN |
BIT_DCDC_MEM_XTL0_EN |
BIT_DCDC_GEN_EXT_XTL0_EN |
BIT_DCDC_GEN_XTL1_EN |
BIT_DCDC_GEN_XTL0_EN |
BIT_DCDC_CORE_EXT_XTL0_EN |
BIT_DCDC_CORE_XTL1_EN |
BIT_DCDC_CORE_XTL0_EN |
0
);
#else
ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR,
//BIT_LDO_AVDD18_PD_RTCCLR |
BIT_DCDC_OTP_PD_RTCCLR |
//BIT_DCDC_WRF_PD_RTCCLR |
BIT_DCDC_GEN_PD_RTCCLR |
BIT_DCDC_MEM_PD_RTCCLR |
BIT_DCDC_ARM_PD_RTCCLR |
BIT_DCDC_CORE_PD_RTCCLR|
BIT_LDO_EMMCCORE_PD_RTCCLR |
BIT_LDO_EMMCIO_PD_RTCCLR |
BIT_LDO_RF2_PD_RTCCLR |
//BIT_LDO_RF1_PD_RTCCLR |
BIT_LDO_RF0_PD_RTCCLR |
BIT_LDO_VDD25_PD_RTCCLR |
BIT_LDO_VDD28_PD_RTCCLR |
BIT_LDO_VDD18_PD_RTCCLR |
BIT_BG_PD_RTCCLR |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET,
BIT_LDO_AVDD18_PD_RTCSET |
//BIT_DCDC_OTP_PD_RTCSET |
BIT_DCDC_WRF_PD_RTCSET |
//BIT_DCDC_GEN_PD_RTCSET |
//BIT_DCDC_MEM_PD_RTCSET |
//BIT_DCDC_ARM_PD_RTCSET |
//BIT_DCDC_CORE_PD_RTCSET|
//BIT_LDO_EMMCCORE_PD_RTCSET |
//BIT_LDO_EMMCIO_PD_RTCSET |
//BIT_LDO_RF2_PD_RTCSET |
BIT_LDO_RF1_PD_RTCSET |
//BIT_LDO_RF0_PD_RTCSET |
//BIT_LDO_VDD25_PD_RTCSET |
//BIT_LDO_VDD28_PD_RTCSET |
//BIT_LDO_VDD18_PD_RTCSET |
//BIT_BG_PD_RTCSET |
0
);
/**********************************************
* Following is AP LDO A DIE Sleep Control *
*********************************************/
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
BIT_SLP_IO_EN |
BIT_SLP_DCDC_OTP_PD_EN |
//BIT_SLP_DCDCGEN_PD_EN |
BIT_SLP_DCDCWPA_PD_EN |
//BIT_SLP_DCDCWRF_PD_EN |
BIT_SLP_DCDCARM_PD_EN |
BIT_SLP_LDOEMMCCORE_PD_EN |
BIT_SLP_LDOEMMCIO_PD_EN |
BIT_SLP_LDORF2_PD_EN |
//BIT_SLP_LDORF1_PD_EN |
BIT_SLP_LDORF0_PD_EN |
BIT_SLP_LDOVDD25_PD_EN |
//BIT_SLP_LDOVDD28_PD_EN |
//BIT_SLP_LDOVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
BIT_SLP_LDO_PD_EN |
BIT_SLP_LDOLPREF_PD_EN |
BIT_SLP_LDOCLSG_PD_EN |
BIT_SLP_LDOUSB_PD_EN |
BIT_SLP_LDOCAMMOT_PD_EN |
BIT_SLP_LDOCAMIO_PD_EN |
BIT_SLP_LDOCAMD_PD_EN |
BIT_SLP_LDOCAMA_PD_EN |
BIT_SLP_LDOSIM2_PD_EN |
//BIT_SLP_LDOSIM1_PD_EN |
//BIT_SLP_LDOSIM0_PD_EN |
BIT_SLP_LDOSD_PD_EN |
BIT_SLP_LDOAVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
//BIT_SLP_DCDC_BG_LP_EN |
//BIT_SLP_DCDCCORE_LP_EN |
//BIT_SLP_DCDCMEM_LP_EN |
//BIT_SLP_DCDCARM_LP_EN |
//BIT_SLP_DCDCGEN_LP_EN |
//BIT_SLP_DCDCWPA_LP_EN |
//BIT_SLP_DCDCWRF_LP_EN |
//BIT_SLP_LDOEMMCCORE_LP_EN |
//BIT_SLP_LDOEMMCIO_LP_EN |
//BIT_SLP_LDORF2_LP_EN |
//BIT_SLP_LDORF1_LP_EN |
//BIT_SLP_LDORF0_LP_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
//BIT_SLP_BG_LP_EN |
//BIT_SLP_LDOVDD25_LP_EN |
//BIT_SLP_LDOVDD28_LP_EN |
//BIT_SLP_LDOVDD18_LP_EN |
//BIT_SLP_LDOCLSG_LP_EN |
//BIT_SLP_LDOUSB_LP_EN |
//BIT_SLP_LDOCAMMOT_LP_EN |
//BIT_SLP_LDOCAMIO_LP_EN |
//BIT_SLP_LDOCAMD_LP_EN |
//BIT_SLP_LDOCAMA_LP_EN |
//BIT_SLP_LDOSIM2_LP_EN |
//BIT_SLP_LDOSIM1_LP_EN |
//BIT_SLP_LDOSIM0_LP_EN |
//BIT_SLP_LDOSD_LP_EN |
//BIT_SLP_LDOAVDD18_LP_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL,
BIT_SLP_XTLBUF_PD_EN |
BIT_XTL_EN |
BITS_XTL_WAIT(0x32)|
0
);
ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL,
BIT_DDR2_BUF_PD_HW |
BITS_DDR2_BUF_S_DS(0x0) |
BITS_DDR2_BUF_CHNS_DS(0x0) |
//BIT_DDR2_BUF_PD |
BITS_DDR2_BUF_S(0x3) |
BITS_DDR2_BUF_CHNS(0x0) |
0
);
/****************************************
* Following is CP LDO Sleep Control *
****************************************/
ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
//BIT_LDO_VDD18_EXT_XTL2_EN |
//BIT_LDO_VDD18_EXT_XTL1_EN |
//BIT_LDO_VDD18_EXT_XTL0_EN |
//BIT_LDO_VDD18_XTL2_EN |
//BIT_LDO_VDD18_XTL1_EN |
//BIT_LDO_VDD18_XTL0_EN |
//BIT_LDO_VDD28_EXT_XTL2_EN |
//BIT_LDO_VDD28_EXT_XTL1_EN |
//BIT_LDO_VDD28_EXT_XTL0_EN |
//BIT_LDO_VDD28_XTL2_EN |
//BIT_LDO_VDD28_XTL1_EN |
//BIT_LDO_VDD28_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
BIT_LDO_XTL_EN |
//BIT_LDO_RF1_EXT_XTL2_EN |
//BIT_LDO_RF1_EXT_XTL1_EN |
//BIT_LDO_RF1_EXT_XTL0_EN |
//BIT_LDO_RF1_XTL2_EN |
//BIT_LDO_RF1_XTL1_EN |
//BIT_LDO_RF1_XTL0_EN |
//BIT_LDO_RF0_EXT_XTL2_EN |
//BIT_LDO_RF0_EXT_XTL1_EN |
//BIT_LDO_RF0_EXT_XTL0_EN |
BIT_LDO_RF0_XTL2_EN |
BIT_LDO_RF0_XTL1_EN |
BIT_LDO_RF0_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
//BIT_LDO_VDD25_EXT_XTL2_EN |
//BIT_LDO_VDD25_EXT_XTL1_EN |
//BIT_LDO_VDD25_EXT_XTL0_EN |
BIT_LDO_VDD25_XTL2_EN |
BIT_LDO_VDD25_XTL1_EN |
BIT_LDO_VDD25_XTL0_EN |
//BIT_LDO_RF2_EXT_XTL2_EN |
//BIT_LDO_RF2_EXT_XTL1_EN |
//BIT_LDO_RF2_EXT_XTL0_EN |
BIT_LDO_RF2_XTL2_EN |
BIT_LDO_RF2_XTL1_EN |
BIT_LDO_RF2_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
//BIT_LDO_AVDD18_EXT_XTL2_EN |
//BIT_LDO_AVDD18_EXT_XTL1_EN |
//BIT_LDO_AVDD18_EXT_XTL0_EN |
//BIT_LDO_AVDD18_XTL2_EN |
//BIT_LDO_AVDD18_XTL1_EN |
//BIT_LDO_AVDD18_XTL0_EN |
//BIT_LDO_SIM2_EXT_XTL2_EN |
//BIT_LDO_SIM2_EXT_XTL1_EN |
//BIT_LDO_SIM2_EXT_XTL0_EN |
//BIT_LDO_SIM2_XTL2_EN |
//BIT_LDO_SIM2_XTL1_EN |
//BIT_LDO_SIM2_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
//BIT_DCDC_BG_EXT_XTL2_EN |
//BIT_DCDC_BG_EXT_XTL1_EN |
//BIT_DCDC_BG_EXT_XTL0_EN |
BIT_DCDC_BG_XTL2_EN |
BIT_DCDC_BG_XTL1_EN |
BIT_DCDC_BG_XTL0_EN |
//BIT_BG_EXT_XTL2_EN |
//BIT_BG_EXT_XTL1_EN |
//BIT_BG_EXT_XTL0_EN |
//BIT_BG_XTL2_EN |
//BIT_BG_XTL1_EN |
//BIT_BG_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
//BIT_DCDC_WRF_XTL2_EN |
//BIT_DCDC_WRF_XTL1_EN |
//BIT_DCDC_WRF_XTL0_EN |
BIT_DCDC_WPA_XTL2_EN |
//BIT_DCDC_WPA_XTL1_EN |
//BIT_DCDC_WPA_XTL0_EN |
BIT_DCDC_MEM_XTL2_EN |
BIT_DCDC_MEM_XTL1_EN |
BIT_DCDC_MEM_XTL0_EN |
BIT_DCDC_GEN_XTL2_EN |
BIT_DCDC_GEN_XTL1_EN |
BIT_DCDC_GEN_XTL0_EN |
BIT_DCDC_CORE_XTL2_EN |
BIT_DCDC_CORE_XTL1_EN |
BIT_DCDC_CORE_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
//BIT_DCDC_WRF_EXT_XTL2_EN |
//BIT_DCDC_WRF_EXT_XTL1_EN |
//BIT_DCDC_WRF_EXT_XTL0_EN |
//BIT_DCDC_WPA_EXT_XTL2_EN |
//BIT_DCDC_WPA_EXT_XTL1_EN |
//BIT_DCDC_WPA_EXT_XTL0_EN |
//BIT_DCDC_MEM_EXT_XTL2_EN |
//BIT_DCDC_MEM_EXT_XTL1_EN |
//BIT_DCDC_MEM_EXT_XTL0_EN |
//BIT_DCDC_GEN_EXT_XTL2_EN |
//BIT_DCDC_GEN_EXT_XTL1_EN |
//BIT_DCDC_GEN_EXT_XTL0_EN |
//BIT_DCDC_CORE_EXT_XTL2_EN |
//BIT_DCDC_CORE_EXT_XTL1_EN |
//BIT_DCDC_CORE_EXT_XTL0_EN |
0
);
#endif
/************************************************
* Following is AP/CP LDO D DIE Sleep Control *
*************************************************/
CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
BIT_XTL0_AP_SEL |
BIT_XTL0_CP0_SEL |
BIT_XTL0_CP1_SEL |
BIT_XTL0_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
BIT_XTL1_AP_SEL |
BIT_XTL1_CP0_SEL |
BIT_XTL1_CP1_SEL |
BIT_XTL1_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
//BIT_XTL2_AP_SEL |
//BIT_XTL2_CP0_SEL |
//BIT_XTL2_CP1_SEL |
BIT_XTL2_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
BIT_XTLBUF0_CP2_SEL |
BIT_XTLBUF0_CP1_SEL |
BIT_XTLBUF0_CP0_SEL |
BIT_XTLBUF0_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
BIT_XTLBUF1_CP2_SEL |
BIT_XTLBUF1_CP1_SEL |
BIT_XTLBUF1_CP0_SEL |
BIT_XTLBUF1_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
//BIT_MPLL_REF_SEL |
//BIT_MPLL_CP2_SEL |
//BIT_MPLL_CP1_SEL |
//BIT_MPLL_CP0_SEL |
BIT_MPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
//BIT_DPLL_REF_SEL |
BIT_DPLL_CP2_SEL |
BIT_DPLL_CP1_SEL |
BIT_DPLL_CP0_SEL |
BIT_DPLL_AP_SEL |
0
);
/*caution tdpll & wpll sel config in spl*/
reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG);
reg_val &= ~0xF;
reg_val |= (
BIT_TDPLL_CP2_SEL|
BIT_TDPLL_CP1_SEL|
BIT_TDPLL_CP0_SEL|
BIT_TDPLL_AP_SEL |
0);
CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val);
reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG);
reg_val &= ~0xF;
reg_val |= (
//BIT_WPLL_CP2_SEL|
//BIT_WPLL_CP1_SEL|
BIT_WPLL_CP0_SEL|
//BIT_WPLL_AP_SEL |
0);
CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val);
CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
//BIT_CPLL_REF_SEL |
BIT_CPLL_CP2_SEL |
//BIT_CPLL_CP1_SEL |
//BIT_CPLL_CP0_SEL |
//BIT_CPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
BIT_WIFIPLL1_REF_SEL |
BIT_WIFIPLL1_CP2_SEL |
//BIT_WIFIPLL1_CP1_SEL |
//BIT_WIFIPLL1_CP0_SEL |
//BIT_WIFIPLL1_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
BIT_WIFIPLL2_REF_SEL |
BIT_WIFIPLL2_CP2_SEL |
//BIT_WIFIPLL2_CP1_SEL |
//BIT_WIFIPLL2_CP0_SEL |
//BIT_WIFIPLL2_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_C0_PWR_ON_DLY(8) |
BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
BITS_PD_CA7_C0_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
BIT_PD_CA7_C1_FORCE_SHUTDOWN |
BITS_PD_CA7_C1_PWR_ON_DLY(8) |
BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C1_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
BIT_PD_CA7_C2_FORCE_SHUTDOWN |
BITS_PD_CA7_C2_PWR_ON_DLY(8) |
BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C2_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
BIT_PD_CA7_C3_FORCE_SHUTDOWN |
BITS_PD_CA7_C3_PWR_ON_DLY(8) |
BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C3_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_AP_SYS_PWR_ON_DLY(8) |
BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_AP_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
BIT_PD_MM_TOP_FORCE_SHUTDOWN |
BITS_PD_MM_TOP_PWR_ON_DLY(8) |
BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_MM_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG,
BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN |
BITS_PD_DDR_PUBL_PWR_ON_DLY(8) |
BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0) |
BITS_PD_DDR_PUBL_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG,
BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN |
BITS_PD_DDR_PHY_PWR_ON_DLY(8) |
BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0) |
BITS_PD_DDR_PHY_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
BITS_XTL1_WAIT_CNT(0x39) |
BITS_XTL0_WAIT_CNT(0x39) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
BITS_XTLBUF1_WAIT_CNT(7) |
BITS_XTLBUF0_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
BITS_WPLL_WAIT_CNT(7) |
BITS_TDPLL_WAIT_CNT(7) |
BITS_DPLL_WAIT_CNT(7) |
BITS_MPLL_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
BITS_WIFIPLL2_WAIT_CNT(7) |
BITS_WIFIPLL1_WAIT_CNT(7) |
BITS_CPLL_WAIT_CNT(7) |
0
);
ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
BITS_SLP_IN_WAIT_DCDCARM(7) |
BITS_SLP_OUT_WAIT_DCDCARM(8) |
0
);
/*chip service package init*/
CSP_Init(0);
}
void init_ldo_sleep_gr(void)
{
u32 reg_val;
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f));
do{
reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT);
}while(reg_val == 0);
ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD,
BIT_DCDC_TOP_CLKF_EN|
BIT_DCDC_TOP_OSC_EN|
//BIT_DCDC_GEN_PD|
//BIT_DCDC_MEM_PD|
//BIT_DCDC_ARM_PD|
//BIT_DCDC_CORE_PD|
//BIT_LDO_RF0_PD|
//BIT_LDO_EMMCCORE_PD|
//BIT_LDO_EMMCIO_PD|
//BIT_LDO_DCXO_PD|
BIT_LDO_CON_PD|
//BIT_LDO_VDD25_PD|
//BIT_LDO_VDD28_PD|
//BIT_LDO_VDD18_PD|
//BIT_BG_PD|
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0));
/**********************************************
* Following is AP LDO A DIE Sleep Control *
*********************************************/
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0,
BIT_SLP_IO_EN |
//BIT_SLP_DCDCGEN_PD_EN |
BIT_SLP_DCDCWPA_PD_EN |
BIT_SLP_DCDCARM_PD_EN |
BIT_SLP_LDORF0_PD_EN |
BIT_SLP_LDOEMMCCORE_PD_EN |
BIT_SLP_LDOEMMCIO_PD_EN |
BIT_SLP_LDODCXO_PD_EN |
BIT_SLP_LDOCON_PD_EN |
BIT_SLP_LDOVDD25_PD_EN |
//BIT_SLP_LDOVDD28_PD_EN |
//BIT_SLP_LODVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1,
BIT_SLP_LDO_PD_EN |
BIT_SLP_LDOLPREF_PD_EN |
BIT_SLP_LDOCLSG_PD_EN |
BIT_SLP_LDOUSB_PD_EN |
BIT_SLP_LDOCAMMOT_PD_EN |
BIT_SLP_LDOCAMIO_PD_EN |
BIT_SLP_LDOCAMD_PD_EN |
BIT_SLP_LDOCAMA_PD_EN |
BIT_SLP_LDOSIM2_PD_EN |
//BIT_SLP_LDOSIM1_PD_EN |
//BIT_SLP_LDOSIM0_PD_EN |
BIT_SLP_LDOSD_PD_EN |
0);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2,
BIT_SLP_DCDCCORE_LP_EN |
BIT_SLP_DCDCMEM_LP_EN |
//BIT_SLP_DCDCARM_LP_EN |
//BIT_SLP_DCDCGEN_LP_EN |
//BIT_SLP_DCDCWPA_LP_EN |
//BIT_SLP_LDORF0_LP_EN |
//BIT_SLP_LDOEMMCCORE_LP_EN |
//BIT_SLP_LDOEMMCIO_LP_EN |
//BIT_SLP_LDODCXO_LP_EN |
//BIT_SLP_LDOCON_LP_EN |
//BIT_SLP_LDOVDD25_LP_EN |
//BIT_SLP_LDOVDD28_LP_EN |
//BIT_SLP_LDOVDD18_LP_EN |
0);
ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3,
BIT_SLP_BG_LP_EN|
//BIT_SLP_LDOCLSG_LP_EN |
//BIT_SLP_LDOUSB_LP_EN |
//BIT_SLP_LDOCAMMOT_LP_EN |
//BIT_SLP_LDOCAMIO_LP_EN |
//BIT_SLP_LDOCAMD_LP_EN |
//BIT_SLP_LDOCAMA_LP_EN |
//BIT_SLP_LDOSIM2_LP_EN |
//BIT_SLP_LDOSIM1_LP_EN |
//BIT_SLP_LDOSIM0_LP_EN |
//BIT_SLP_LDOSD_LP_EN |
0);
/****************************************
* Following is CP LDO Sleep Control *
****************************************/
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
BIT_LDO_XTL_EN |
BIT_LDO_DCXO_EXT_XTL1_EN |
BIT_LDO_DCXO_EXT_XTL0_EN |
BIT_LDO_DCXO_XTL2_EN |
BIT_LDO_DCXO_XTL0_EN |
//BIT_LDO_VDD18_EXT_XTL1_EN |
//BIT_LDO_VDD18_EXT_XTL0_EN |
//BIT_LDO_VDD18_XTL2_EN |
//BIT_LDO_VDD18_XTL0_EN |
//BIT_LDO_VDD28_EXT_XTL1_EN |
//BIT_LDO_VDD28_EXT_XTL0_EN |
//BIT_LDO_VDD28_XTL2_EN |
//BIT_LDO_VDD28_XTL0_EN |
0);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
BIT_LDO_RF0_EXT_XTL1_EN |
BIT_LDO_RF0_EXT_XTL0_EN |
BIT_LDO_RF0_XTL2_EN |
BIT_LDO_RF0_XTL0_EN |
//BIT_LDO_VDD25_EXT_XTL1_EN |
//BIT_LDO_VDD25_EXT_XTL0_EN |
BIT_LDO_VDD25_XTL2_EN |
BIT_LDO_VDD25_XTL0_EN |
//BIT_LDO_CON_EXT_XTL1_EN |
//BIT_LDO_CON_EXT_XTL0_EN |
//BIT_LDO_CON_XTL2_EN |
//BIT_LDO_CON_XTL0_EN |
0);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
//BIT_LDO_SIM2_EXT_XTL1_EN |
//BIT_LDO_SIM2_EXT_XTL0_EN |
//BIT_LDO_SIM2_XTL2_EN |
//BIT_LDO_SIM2_XTL0_EN |
//BIT_LDO_SIM1_EXT_XTL1_EN |
//BIT_LDO_SIM1_EXT_XTL0_EN |
//BIT_LDO_SIM1_XTL2_EN |
//BIT_LDO_SIM1_XTL0_EN |
//BIT_LDO_SIM0_EXT_XTL1_EN |
//BIT_LDO_SIM0_EXT_XTL0_EN |
//BIT_LDO_SIM0_XTL2_EN |
//BIT_LDO_SIM0_XTL0_EN |
0);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
//BIT_XO_EXT_XTL1_EN |
//BIT_XO_EXT_XTL0_EN |
//BIT_XO_XTL2_EN |
//BIT_XO_XTL0_EN |
//BIT_BG_EXT_XTL1_EN |
//BIT_BG_EXT_XTL0_EN |
BIT_BG_XTL2_EN |
BIT_BG_XTL0_EN |
0);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
//BIT_DCDC_WPA_EXT_XTL1_EN |
//BIT_DCDC_WPA_EXT_XTL0_EN |
//BIT_DCDC_WPA_XTL2_EN |
BIT_DCDC_WPA_XTL0_EN |
//BIT_DCDC_MEM_EXT_XTL1_EN |
//BIT_DCDC_MEM_EXT_XTL0_EN |
//BIT_DCDC_MEM_XTL2_EN |
//BIT_DCDC_MEM_XTL0_EN |
//BIT_DCDC_GEN_EXT_XTL1_EN |
//BIT_DCDC_GEN_EXT_XTL0_EN |
//BIT_DCDC_GEN_XTL2_EN |
//BIT_DCDC_GEN_XTL0_EN |
//BIT_DCDC_CORE_EXT_XTL1_EN |
//BIT_DCDC_CORE_EXT_XTL0_EN |
BIT_DCDC_CORE_XTL2_EN |
BIT_DCDC_CORE_XTL0_EN |
0);
/************************************************
* Following is AP/CP LDO D DIE Sleep Control *
*************************************************/
CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
BIT_XTL0_AP_SEL |
BIT_XTL0_CP0_SEL |
//BIT_XTL0_CP1_SEL |
BIT_XTL0_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
BIT_XTL1_AP_SEL |
BIT_XTL1_CP0_SEL |
//BIT_XTL1_CP1_SEL |
BIT_XTL1_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
//BIT_XTL2_AP_SEL |
//BIT_XTL2_CP0_SEL |
//BIT_XTL2_CP1_SEL |
BIT_XTL2_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
BIT_XTLBUF0_CP2_SEL |
BIT_XTLBUF0_CP1_SEL |
BIT_XTLBUF0_CP0_SEL |
BIT_XTLBUF0_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
BIT_XTLBUF1_CP2_SEL |
//BIT_XTLBUF1_CP1_SEL |
BIT_XTLBUF1_CP0_SEL |
BIT_XTLBUF1_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
//BIT_MPLL_REF_SEL |
//BIT_MPLL_CP2_SEL |
//BIT_MPLL_CP1_SEL |
//BIT_MPLL_CP0_SEL |
BIT_MPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
//BIT_DPLL_REF_SEL |
BIT_DPLL_CP2_SEL |
//BIT_DPLL_CP1_SEL |
BIT_DPLL_CP0_SEL |
BIT_DPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
//BIT_TDPLL_REF_SEL |
BIT_TDPLL_CP2_SEL |
//BIT_TDPLL_CP1_SEL |
BIT_TDPLL_CP0_SEL |
BIT_TDPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
//BIT_WPLL_REF_SEL |
//BIT_WPLL_CP2_SEL |
//BIT_WPLL_CP1_SEL |
BIT_WPLL_CP0_SEL |
//BIT_WPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
//BIT_CPLL_REF_SEL |
BIT_CPLL_CP2_SEL |
//BIT_CPLL_CP1_SEL |
//BIT_CPLL_CP0_SEL |
//BIT_CPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG,
//BIT_WIFIPLL1_REF_SEL |
BIT_WIFIPLL1_CP2_SEL |
//BIT_WIFIPLL1_CP1_SEL |
//BIT_WIFIPLL1_CP0_SEL |
//BIT_WIFIPLL1_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG,
//BIT_WIFIPLL2_REF_SEL |
BIT_WIFIPLL2_CP2_SEL |
//BIT_WIFIPLL2_CP1_SEL |
//BIT_WIFIPLL2_CP0_SEL |
//BIT_WIFIPLL2_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,
BIT_CGM_208M_AP_EN |
BIT_CGM_12M_AP_EN |
BIT_CGM_24M_AP_EN |
BIT_CGM_48M_AP_EN |
BIT_CGM_51M2_AP_EN |
BIT_CGM_64M_AP_EN |
BIT_CGM_76M8_AP_EN |
BIT_CGM_96M_AP_EN |
BIT_CGM_128M_AP_EN |
BIT_CGM_153M6_AP_EN |
BIT_CGM_192M_AP_EN |
BIT_CGM_256M_AP_EN |
BIT_CGM_384M_AP_EN |
BIT_CGM_312M_AP_EN |
BIT_CGM_MPLL_AP_EN |
//BIT_CGM_WPLL_AP_EN |
//BIT_CGM_WIFIPLL1_AP_EN |
BIT_CGM_TDPLL_AP_EN |
//BIT_CGM_CPLL_AP_EN |
BIT_CGM_DPLL_AP_EN |
BIT_CGM_26M_AP_EN |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_C0_PWR_ON_DLY(8) |
BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
BITS_PD_CA7_C0_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
BIT_PD_CA7_C1_FORCE_SHUTDOWN |
BITS_PD_CA7_C1_PWR_ON_DLY(8) |
BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C1_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
BIT_PD_CA7_C2_FORCE_SHUTDOWN |
BITS_PD_CA7_C2_PWR_ON_DLY(8) |
BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C2_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
BIT_PD_CA7_C3_FORCE_SHUTDOWN |
BITS_PD_CA7_C3_PWR_ON_DLY(8) |
BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C3_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_AP_SYS_PWR_ON_DLY(8) |
BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_AP_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
BIT_PD_MM_TOP_FORCE_SHUTDOWN |
BITS_PD_MM_TOP_PWR_ON_DLY(8) |
BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_MM_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
BITS_XTL1_WAIT_CNT(0x39) |
BITS_XTL0_WAIT_CNT(0x39) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
BITS_XTLBUF1_WAIT_CNT(7) |
BITS_XTLBUF0_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
BITS_WPLL_WAIT_CNT(7) |
BITS_TDPLL_WAIT_CNT(7) |
BITS_DPLL_WAIT_CNT(7) |
BITS_MPLL_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
BITS_WIFIPLL2_WAIT_CNT(7) |
BITS_WIFIPLL1_WAIT_CNT(7) |
BITS_CPLL_WAIT_CNT(7) |
0
);
ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
BITS_SLP_IN_WAIT_DCDCARM(9) |
BITS_SLP_OUT_WAIT_DCDCARM(8) |
0
);
/*work round sin0 disconnect*/
reg_val = CHIP_REG_GET(REG_AON_APB_SINDRV_CTRL);
reg_val |= BIT_SINDRV_ENA_SQUARE;
CHIP_REG_SET(REG_AON_APB_SINDRV_CTRL, reg_val);
}
void init_ldo_sleep_gr(void)
{
ANA_REG_OR(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, (BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET));
ANA_REG_AND(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, (~(BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET)));
ANA_REG_OR(ANA_REG_GLB_LDO_PD_CTRL, (BIT_DCDC_WPA_PD));
/**********************************************
* Following is AP LDO A DIE Sleep Control *
*********************************************/
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0,
BIT_SLP_IO_EN |
BIT_SLP_DCDC_OTP_PD_EN |
//BIT_SLP_DCDCGEN_PD_EN |
//BIT_SLP_DCDCWPA_PD_EN |
//BIT_SLP_DCDCWRF_PD_EN |
BIT_SLP_DCDCARM_PD_EN |
BIT_SLP_LDOEMMCCORE_PD_EN |
BIT_SLP_LDOEMMCIO_PD_EN |
BIT_SLP_LDORF2_PD_EN |
//BIT_SLP_LDORF1_PD_EN |
BIT_SLP_LDORF0_PD_EN |
BIT_SLP_LDOVDD25_PD_EN |
//BIT_SLP_LDOVDD28_PD_EN |
//BIT_SLP_LDOVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1,
BIT_SLP_LDO_PD_EN |
BIT_SLP_LDOLPREF_PD_EN |
BIT_SLP_LDOCLSG_PD_EN |
BIT_SLP_LDOUSB_PD_EN |
BIT_SLP_LDOCAMMOT_PD_EN |
BIT_SLP_LDOCAMIO_PD_EN |
BIT_SLP_LDOCAMD_PD_EN |
BIT_SLP_LDOCAMA_PD_EN |
BIT_SLP_LDOSIM2_PD_EN |
//BIT_SLP_LDOSIM1_PD_EN |
//BIT_SLP_LDOSIM0_PD_EN |
BIT_SLP_LDOSD_PD_EN |
BIT_SLP_LDOAVDD18_PD_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2,
//BIT_SLP_DCDC_BG_LP_EN |
//BIT_SLP_DCDCCORE_LP_EN |
//BIT_SLP_DCDCMEM_LP_EN |
//BIT_SLP_DCDCARM_LP_EN |
//BIT_SLP_DCDCGEN_LP_EN |
//BIT_SLP_DCDCWPA_LP_EN |
//BIT_SLP_DCDCWRF_LP_EN |
//BIT_SLP_LDOEMMCCORE_LP_EN |
//BIT_SLP_LDOEMMCIO_LP_EN |
//BIT_SLP_LDORF2_LP_EN |
//BIT_SLP_LDORF1_LP_EN |
//BIT_SLP_LDORF0_LP_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3,
//BIT_SLP_BG_LP_EN |
//BIT_SLP_LDOVDD25_LP_EN |
//BIT_SLP_LDOVDD28_LP_EN |
//BIT_SLP_LDOVDD18_LP_EN |
//BIT_SLP_LDOCLSG_LP_EN |
//BIT_SLP_LDOUSB_LP_EN |
//BIT_SLP_LDOCAMMOT_LP_EN |
//BIT_SLP_LDOCAMIO_LP_EN |
//BIT_SLP_LDOCAMD_LP_EN |
//BIT_SLP_LDOCAMA_LP_EN |
//BIT_SLP_LDOSIM2_LP_EN |
//BIT_SLP_LDOSIM1_LP_EN |
//BIT_SLP_LDOSIM0_LP_EN |
//BIT_SLP_LDOSD_LP_EN |
//BIT_SLP_LDOAVDD18_LP_EN |
0
);
/****************************************
* Following is CP LDO Sleep Control *
****************************************/
ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL,
//BIT_LDO_VDD18_EXT_XTL2_EN |
//BIT_LDO_VDD18_EXT_XTL1_EN |
//BIT_LDO_VDD18_EXT_XTL0_EN |
//BIT_LDO_VDD18_XTL2_EN |
//BIT_LDO_VDD18_XTL1_EN |
//BIT_LDO_VDD18_XTL0_EN |
//BIT_LDO_VDD28_EXT_XTL2_EN |
//BIT_LDO_VDD28_EXT_XTL1_EN |
//BIT_LDO_VDD28_EXT_XTL0_EN |
//BIT_LDO_VDD28_XTL2_EN |
//BIT_LDO_VDD28_XTL1_EN |
//BIT_LDO_VDD28_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0,
BIT_LDO_XTL_EN |
//BIT_LDO_RF1_EXT_XTL2_EN |
//BIT_LDO_RF1_EXT_XTL1_EN |
//BIT_LDO_RF1_EXT_XTL0_EN |
//BIT_LDO_RF1_XTL2_EN |
//BIT_LDO_RF1_XTL1_EN |
//BIT_LDO_RF1_XTL0_EN |
//BIT_LDO_RF0_EXT_XTL2_EN |
//BIT_LDO_RF0_EXT_XTL1_EN |
//BIT_LDO_RF0_EXT_XTL0_EN |
BIT_LDO_RF0_XTL2_EN |
BIT_LDO_RF0_XTL1_EN |
BIT_LDO_RF0_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1,
//BIT_LDO_VDD25_EXT_XTL2_EN |
//BIT_LDO_VDD25_EXT_XTL1_EN |
//BIT_LDO_VDD25_EXT_XTL0_EN |
BIT_LDO_VDD25_XTL2_EN |
BIT_LDO_VDD25_XTL1_EN |
BIT_LDO_VDD25_XTL0_EN |
//BIT_LDO_RF2_EXT_XTL2_EN |
//BIT_LDO_RF2_EXT_XTL1_EN |
//BIT_LDO_RF2_EXT_XTL0_EN |
BIT_LDO_RF2_XTL2_EN |
BIT_LDO_RF2_XTL1_EN |
BIT_LDO_RF2_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2,
//BIT_LDO_AVDD18_EXT_XTL2_EN |
//BIT_LDO_AVDD18_EXT_XTL1_EN |
//BIT_LDO_AVDD18_EXT_XTL0_EN |
//BIT_LDO_AVDD18_XTL2_EN |
//BIT_LDO_AVDD18_XTL1_EN |
//BIT_LDO_AVDD18_XTL0_EN |
//BIT_LDO_SIM2_EXT_XTL2_EN |
//BIT_LDO_SIM2_EXT_XTL1_EN |
//BIT_LDO_SIM2_EXT_XTL0_EN |
//BIT_LDO_SIM2_XTL2_EN |
//BIT_LDO_SIM2_XTL1_EN |
//BIT_LDO_SIM2_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3,
//BIT_DCDC_BG_EXT_XTL2_EN |
//BIT_DCDC_BG_EXT_XTL1_EN |
//BIT_DCDC_BG_EXT_XTL0_EN |
BIT_DCDC_BG_XTL2_EN |
BIT_DCDC_BG_XTL1_EN |
BIT_DCDC_BG_XTL0_EN |
//BIT_BG_EXT_XTL2_EN |
//BIT_BG_EXT_XTL1_EN |
//BIT_BG_EXT_XTL0_EN |
//BIT_BG_XTL2_EN |
//BIT_BG_XTL1_EN |
//BIT_BG_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4,
//BIT_DCDC_WRF_XTL2_EN |
//BIT_DCDC_WRF_XTL1_EN |
//BIT_DCDC_WRF_XTL0_EN |
//BIT_DCDC_WPA_XTL2_EN |
//BIT_DCDC_WPA_XTL1_EN |
//BIT_DCDC_WPA_XTL0_EN |
BIT_DCDC_MEM_XTL2_EN |
BIT_DCDC_MEM_XTL1_EN |
BIT_DCDC_MEM_XTL0_EN |
BIT_DCDC_GEN_XTL2_EN |
BIT_DCDC_GEN_XTL1_EN |
BIT_DCDC_GEN_XTL0_EN |
BIT_DCDC_CORE_XTL2_EN |
BIT_DCDC_CORE_XTL1_EN |
BIT_DCDC_CORE_XTL0_EN |
0
);
ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5,
//BIT_DCDC_WRF_EXT_XTL2_EN |
//BIT_DCDC_WRF_EXT_XTL1_EN |
//BIT_DCDC_WRF_EXT_XTL0_EN |
//BIT_DCDC_WPA_EXT_XTL2_EN |
//BIT_DCDC_WPA_EXT_XTL1_EN |
//BIT_DCDC_WPA_EXT_XTL0_EN |
//BIT_DCDC_MEM_EXT_XTL2_EN |
//BIT_DCDC_MEM_EXT_XTL1_EN |
//BIT_DCDC_MEM_EXT_XTL0_EN |
//BIT_DCDC_GEN_EXT_XTL2_EN |
//BIT_DCDC_GEN_EXT_XTL1_EN |
//BIT_DCDC_GEN_EXT_XTL0_EN |
//BIT_DCDC_CORE_EXT_XTL2_EN |
//BIT_DCDC_CORE_EXT_XTL1_EN |
//BIT_DCDC_CORE_EXT_XTL0_EN |
0
);
/************************************************
* Following is AP/CP LDO D DIE Sleep Control *
*************************************************/
CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG,
BIT_XTL0_AP_SEL |
BIT_XTL0_CP0_SEL |
BIT_XTL0_CP1_SEL |
BIT_XTL0_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG,
BIT_XTL1_AP_SEL |
BIT_XTL1_CP0_SEL |
BIT_XTL1_CP1_SEL |
BIT_XTL1_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG,
BIT_XTL2_AP_SEL |
BIT_XTL2_CP0_SEL |
BIT_XTL2_CP1_SEL |
BIT_XTL2_CP2_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG,
BIT_XTLBUF0_CP2_SEL |
BIT_XTLBUF0_CP1_SEL |
BIT_XTLBUF0_CP0_SEL |
BIT_XTLBUF0_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG,
BIT_XTLBUF1_CP2_SEL |
BIT_XTLBUF1_CP1_SEL |
BIT_XTLBUF1_CP0_SEL |
BIT_XTLBUF1_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG,
//BIT_MPLL_REF_SEL |
//BIT_MPLL_CP2_SEL |
//BIT_MPLL_CP1_SEL |
//BIT_MPLL_CP0_SEL |
BIT_MPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG,
//BIT_DPLL_REF_SEL |
BIT_DPLL_CP2_SEL |
BIT_DPLL_CP1_SEL |
BIT_DPLL_CP0_SEL |
BIT_DPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,
//BIT_TDPLL_REF_SEL |
BIT_TDPLL_CP2_SEL |
BIT_TDPLL_CP1_SEL |
BIT_TDPLL_CP0_SEL |
BIT_TDPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,
//BIT_WPLL_REF_SEL |
//BIT_WPLL_CP2_SEL |
//BIT_WPLL_CP1_SEL |
BIT_WPLL_CP0_SEL |
//BIT_WPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG,
//BIT_CPLL_REF_SEL |
BIT_CPLL_CP2_SEL |
BIT_CPLL_CP1_SEL |
//BIT_CPLL_CP0_SEL |
//BIT_CPLL_AP_SEL |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_TOP_PWR_ON_DLY(8) |
BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) |
BITS_PD_CA7_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
BITS_PD_CA7_C0_PWR_ON_DLY(8) |
BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) |
BITS_PD_CA7_C0_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
BIT_PD_CA7_C1_FORCE_SHUTDOWN |
BITS_PD_CA7_C1_PWR_ON_DLY(8) |
BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C1_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
BIT_PD_CA7_C2_FORCE_SHUTDOWN |
BITS_PD_CA7_C2_PWR_ON_DLY(8) |
BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C2_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
BIT_PD_CA7_C3_FORCE_SHUTDOWN |
BITS_PD_CA7_C3_PWR_ON_DLY(8) |
BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) |
BITS_PD_CA7_C3_ISO_ON_DLY(2) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_AP_SYS_PWR_ON_DLY(8) |
BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_AP_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
BIT_PD_MM_TOP_FORCE_SHUTDOWN |
BITS_PD_MM_TOP_PWR_ON_DLY(8) |
BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_MM_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
BITS_PD_GPU_TOP_PWR_ON_DLY(8) |
BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) |
BITS_PD_GPU_TOP_ISO_ON_DLY(4) |
0
);
CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
BITS_PD_PUB_SYS_PWR_ON_DLY(8) |
BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) |
BITS_PD_PUB_SYS_ISO_ON_DLY(6) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
BITS_XTL1_WAIT_CNT(0x39) |
BITS_XTL0_WAIT_CNT(0x39) |
0
);
CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
BITS_XTLBUF1_WAIT_CNT(7) |
BITS_XTLBUF0_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
BITS_WPLL_WAIT_CNT(7) |
BITS_TDPLL_WAIT_CNT(7) |
BITS_DPLL_WAIT_CNT(7) |
BITS_MPLL_WAIT_CNT(7) |
0
);
CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
BITS_WIFIPLL2_WAIT_CNT(7) |
BITS_WIFIPLL1_WAIT_CNT(7) |
BITS_CPLL_WAIT_CNT(7) |
0
);
ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
BITS_SLP_IN_WAIT_DCDCARM(9) |
BITS_SLP_OUT_WAIT_DCDCARM(8) |
0
);
}
static void wr_prot_en(void)
{
ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE, BITS_PWR_WR_PROT_VALUE(0));
}